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1 #
2 # Copyright (c) 2011-2013, ARM Limited. All rights reserved.
3 #
4 # This program and the accompanying materials
5 # are licensed and made available under the terms and conditions of the BSD License
6 # which accompanies this distribution. The full text of the license may be found at
7 # http://opensource.org/licenses/bsd-license.php
8 #
9 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11 #
12 #
13
14 #include <AsmMacroIoLibV8.h>
15 #include <Base.h>
16 #include <Library/ArmLib.h>
17 #include <Library/PcdLib.h>
18 #include <AutoGen.h>
19
20 .text
21 .align 2
22
23 GCC_ASM_EXPORT(ArmPlatformPeiBootAction)
24 GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)
25 GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)
26 GCC_ASM_EXPORT(ArmPlatformGetCorePosition)
27 GCC_ASM_EXPORT(ArmGetPhysAddrTop)
28
29 GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)
30 GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)
31 GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdCoreCount)
32
33 .LArm64LinuxMagic:
34 .byte 0x41, 0x52, 0x4d, 0x64
35
36 // VOID
37 // ArmPlatformPeiBootAction (
38 // VOID *DeviceTreeBaseAddress, // passed by loader in x0
39 // VOID *ImageBase // passed by FDF trampoline in x1
40 // );
41 ASM_PFX(ArmPlatformPeiBootAction):
42 //
43 // If we are booting from RAM using the Linux kernel boot protocol, x0 will
44 // point to the DTB image in memory. Otherwise, use the default value defined
45 // by the platform.
46 //
47 cbnz x0, 0f
48 ldr x0, PcdGet64 (PcdDeviceTreeInitialBaseAddress)
49
50 0:mov x29, x30 // preserve LR
51 mov x28, x0 // preserve DTB pointer
52 mov x27, x1 // preserve base of image pointer
53
54 //
55 // The base of the runtime image has been preserved in x1. Check whether
56 // the expected magic number can be found in the header.
57 //
58 ldr w8, .LArm64LinuxMagic
59 ldr w9, [x1, #0x38]
60 cmp w8, w9
61 bne .Lout
62
63 //
64 //
65 // OK, so far so good. We have confirmed that we likely have a DTB and are
66 // booting via the arm64 Linux boot protocol. Update the base-of-image PCD
67 // to the actual relocated value, and add the shift of PcdFdBaseAddress to
68 // PcdFvBaseAddress as well
69 //
70 adr x8, PcdGet64 (PcdFdBaseAddress)
71 adr x9, PcdGet64 (PcdFvBaseAddress)
72 ldr x6, [x8]
73 ldr x7, [x9]
74 sub x7, x7, x6
75 add x7, x7, x1
76 str x1, [x8]
77 str x7, [x9]
78
79 //
80 // Discover the memory size and offset from the DTB, and record in the
81 // respective PCDs. This will also return false if a corrupt DTB is
82 // encountered. Since we are calling a C function, use the window at the
83 // beginning of the FD image as a temp stack.
84 //
85 adr x1, PcdGet64 (PcdSystemMemorySize)
86 adr x2, PcdGet64 (PcdSystemMemoryBase)
87 mov sp, x7
88 bl FindMemnode
89 cbz x0, .Lout
90
91 //
92 // Copy the DTB to the slack space right after the 64 byte arm64/Linux style
93 // image header at the base of this image (defined in the FDF), and record the
94 // pointer in PcdDeviceTreeInitialBaseAddress.
95 //
96 adr x8, PcdGet64 (PcdDeviceTreeInitialBaseAddress)
97 add x27, x27, #0x40
98 str x27, [x8]
99
100 mov x0, x27
101 mov x1, x28
102 bl CopyFdt
103
104 .Lout:
105 ret x29
106
107 //UINTN
108 //ArmPlatformGetPrimaryCoreMpId (
109 // VOID
110 // );
111 ASM_PFX(ArmPlatformGetPrimaryCoreMpId):
112 LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x0)
113 ldrh w0, [x0]
114 ret
115
116 //UINTN
117 //ArmPlatformIsPrimaryCore (
118 // IN UINTN MpId
119 // );
120 ASM_PFX(ArmPlatformIsPrimaryCore):
121 mov x0, #1
122 ret
123
124 //UINTN
125 //ArmPlatformGetCorePosition (
126 // IN UINTN MpId
127 // );
128 // With this function: CorePos = (ClusterId * 4) + CoreId
129 ASM_PFX(ArmPlatformGetCorePosition):
130 and x1, x0, #ARM_CORE_MASK
131 and x0, x0, #ARM_CLUSTER_MASK
132 add x0, x1, x0, LSR #6
133 ret
134
135 //EFI_PHYSICAL_ADDRESS
136 //GetPhysAddrTop (
137 // VOID
138 // );
139 ASM_PFX(ArmGetPhysAddrTop):
140 mrs x0, id_aa64mmfr0_el1
141 adr x1, .LPARanges
142 and x0, x0, #7
143 ldrb w1, [x1, x0]
144 mov x0, #1
145 lsl x0, x0, x1
146 ret
147
148 //
149 // Bits 0..2 of the AA64MFR0_EL1 system register encode the size of the
150 // physical address space support on this CPU:
151 // 0 == 32 bits, 1 == 36 bits, etc etc
152 // 6 and 7 are reserved
153 //
154 .LPARanges:
155 .byte 32, 36, 40, 42, 44, 48, -1, -1
156
157 ASM_FUNCTION_REMOVE_IF_UNREFERENCED