2 ArmGicArchLib library class implementation for DT based virt platforms
4 Copyright (c) 2015 - 2016, Linaro Ltd. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
13 #include <Library/ArmGicLib.h>
14 #include <Library/ArmGicArchLib.h>
15 #include <Library/BaseLib.h>
16 #include <Library/DebugLib.h>
17 #include <Library/PcdLib.h>
18 #include <Library/UefiBootServicesTableLib.h>
20 #include <Protocol/FdtClient.h>
22 STATIC ARM_GIC_ARCH_REVISION mGicArchRevision
;
26 ArmVirtGicArchLibConstructor (
31 FDT_CLIENT_PROTOCOL
*FdtClient
;
34 UINTN AddressCells
, SizeCells
;
37 UINT64 DistBase
, CpuBase
, RedistBase
;
38 RETURN_STATUS PcdStatus
;
40 Status
= gBS
->LocateProtocol (&gFdtClientProtocolGuid
, NULL
,
42 ASSERT_EFI_ERROR (Status
);
45 Status
= FdtClient
->FindCompatibleNodeReg (FdtClient
, "arm,cortex-a15-gic",
46 (CONST VOID
**)&Reg
, &AddressCells
, &SizeCells
,
48 if (Status
== EFI_NOT_FOUND
) {
50 Status
= FdtClient
->FindCompatibleNodeReg (FdtClient
, "arm,gic-v3",
51 (CONST VOID
**)&Reg
, &AddressCells
, &SizeCells
,
54 if (EFI_ERROR (Status
)) {
58 switch (GicRevision
) {
62 // The GIC v3 DT binding describes a series of at least 3 physical (base
63 // addresses, size) pairs: the distributor interface (GICD), at least one
64 // redistributor region (GICR) containing dedicated redistributor
65 // interfaces for all individual CPUs, and the CPU interface (GICC).
66 // Under virtualization, we assume that the first redistributor region
67 // listed covers the boot CPU. Also, our GICv3 driver only supports the
68 // system register CPU interface, so we can safely ignore the MMIO version
69 // which is listed after the sequence of redistributor interfaces.
70 // This means we are only interested in the first two memory regions
71 // supplied, and ignore everything else.
73 ASSERT (RegSize
>= 32);
75 // RegProp[0..1] == { GICD base, GICD size }
76 DistBase
= SwapBytes64 (Reg
[0]);
77 ASSERT (DistBase
< MAX_UINTN
);
79 // RegProp[2..3] == { GICR base, GICR size }
80 RedistBase
= SwapBytes64 (Reg
[2]);
81 ASSERT (RedistBase
< MAX_UINTN
);
83 PcdStatus
= PcdSet64S (PcdGicDistributorBase
, DistBase
);
84 ASSERT_RETURN_ERROR (PcdStatus
);
85 PcdStatus
= PcdSet64S (PcdGicRedistributorsBase
, RedistBase
);
86 ASSERT_RETURN_ERROR (PcdStatus
);
88 DEBUG ((EFI_D_INFO
, "Found GIC v3 (re)distributor @ 0x%Lx (0x%Lx)\n",
89 DistBase
, RedistBase
));
92 // The default implementation of ArmGicArchLib is responsible for enabling
93 // the system register interface on the GICv3 if one is found. So let's do
96 IccSre
= ArmGicV3GetControlSystemRegisterEnable ();
97 if (!(IccSre
& ICC_SRE_EL2_SRE
)) {
98 ArmGicV3SetControlSystemRegisterEnable (IccSre
| ICC_SRE_EL2_SRE
);
99 IccSre
= ArmGicV3GetControlSystemRegisterEnable ();
103 // Unlike the default implementation, there is no fall through to GICv2
104 // mode if this GICv3 cannot be driven in native mode due to the fact
105 // that the System Register interface is unavailable.
107 ASSERT (IccSre
& ICC_SRE_EL2_SRE
);
109 mGicArchRevision
= ARM_GIC_ARCH_REVISION_3
;
113 ASSERT (RegSize
== 32);
115 DistBase
= SwapBytes64 (Reg
[0]);
116 CpuBase
= SwapBytes64 (Reg
[2]);
117 ASSERT (DistBase
< MAX_UINTN
);
118 ASSERT (CpuBase
< MAX_UINTN
);
120 PcdStatus
= PcdSet64S (PcdGicDistributorBase
, DistBase
);
121 ASSERT_RETURN_ERROR (PcdStatus
);
122 PcdStatus
= PcdSet64S (PcdGicInterruptInterfaceBase
, CpuBase
);
123 ASSERT_RETURN_ERROR (PcdStatus
);
125 DEBUG ((EFI_D_INFO
, "Found GIC @ 0x%Lx/0x%Lx\n", DistBase
, CpuBase
));
127 mGicArchRevision
= ARM_GIC_ARCH_REVISION_2
;
131 DEBUG ((EFI_D_ERROR
, "%a: No GIC revision specified!\n", __FUNCTION__
));
132 return RETURN_NOT_FOUND
;
134 return RETURN_SUCCESS
;
137 ARM_GIC_ARCH_REVISION
139 ArmGicGetSupportedArchRevision (
143 return mGicArchRevision
;