ArmVirtPkg/PciHostBridgeDxe/PciHostBridge.c

   1 /** @file
   2   Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation
   3
   4 Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
   5 This program and the accompanying materials are
   6 licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include "PciHostBridge.h"
  16
  17 //
  18 // Hard code: Root Bridge Number within the host bridge
  19 //            Root Bridge's attribute
  20 //            Root Bridge's device path
  21 //            Root Bridge's resource aperture
  22 //
  23 UINTN RootBridgeNumber[1] = { 1 };
  24
  25 UINT64 RootBridgeAttribute[1][1] = { { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM } };
  26
  27 EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {
  28   {
  29     {
  30       {
  31         {
  32           ACPI_DEVICE_PATH,
  33           ACPI_DP,
  34           {
  35             (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  36             (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  37           }
  38         },
  39         EISA_PNP_ID(0x0A03),
  40         0
  41       },
  42
  43       {
  44         END_DEVICE_PATH_TYPE,
  45         END_ENTIRE_DEVICE_PATH_SUBTYPE,
  46         {
  47           END_DEVICE_PATH_LENGTH,
  48           0
  49         }
  50       }
  51     }
  52   }
  53 };
  54
  55 STATIC PCI_ROOT_BRIDGE_RESOURCE_APERTURE  mResAperture[1][1];
  56
  57 EFI_HANDLE mDriverImageHandle;
  58
  59 PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {
  60   PCI_HOST_BRIDGE_SIGNATURE,  // Signature
  61   NULL,                       // HostBridgeHandle
  62   0,                          // RootBridgeNumber
  63   {NULL, NULL},               // Head
  64   FALSE,                      // ResourceSubiteed
  65   TRUE,                       // CanRestarted
  66   {
  67     NotifyPhase,
  68     GetNextRootBridge,
  69     GetAttributes,
  70     StartBusEnumeration,
  71     SetBusNumbers,
  72     SubmitResources,
  73     GetProposedResources,
  74     PreprocessController
  75   }
  76 };
  77
  78 //
  79 // Implementation
  80 //
  81
  82 STATIC
  83 VOID
  84 SetLinuxPciProbeOnlyProperty (
  85   IN FDT_CLIENT_PROTOCOL         *FdtClient
  86   )
  87 {
  88   INT32         Node;
  89   UINT32        Tmp;
  90   EFI_STATUS    Status;
  91
  92   if (!FeaturePcdGet (PcdPureAcpiBoot)) {
  93     //
  94     // Set the /chosen/linux,pci-probe-only property to 1, so that the PCI
  95     // setup we will perform in the firmware is honored by the Linux OS,
  96     // rather than torn down and done from scratch. This is generally a more
  97     // sensible approach, and aligns with what ACPI based OSes do typically.
  98     //
  99     // In case we are exposing an emulated VGA PCI device to the guest, which
 100     // may subsequently get exposed via the Graphics Output protocol and
 101     // driven as an efifb by Linux, we need this setting to prevent the
 102     // framebuffer from becoming unresponsive.
 103     //
 104     Status = FdtClient->GetOrInsertChosenNode (FdtClient, &Node);
 105
 106     if (!EFI_ERROR (Status)) {
 107       Tmp = SwapBytes32 (1);
 108       Status = FdtClient->SetNodeProperty (FdtClient, Node,
 109                             "linux,pci-probe-only", &Tmp, sizeof (Tmp));
 110     }
 111     if (EFI_ERROR (Status)) {
 112       DEBUG ((EFI_D_WARN,
 113         "Failed to set /chosen/linux,pci-probe-only property\n"));
 114     }
 115   }
 116 }
 117
 118 //
 119 // We expect the "ranges" property of "pci-host-ecam-generic" to consist of
 120 // records like this.
 121 //
 122 #pragma pack (1)
 123 typedef struct {
 124   UINT32 Type;
 125   UINT64 ChildBase;
 126   UINT64 CpuBase;
 127   UINT64 Size;
 128 } DTB_PCI_HOST_RANGE_RECORD;
 129 #pragma pack ()
 130
 131 #define DTB_PCI_HOST_RANGE_RELOCATABLE  BIT31
 132 #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
 133 #define DTB_PCI_HOST_RANGE_ALIASED      BIT29
 134 #define DTB_PCI_HOST_RANGE_MMIO32       BIT25
 135 #define DTB_PCI_HOST_RANGE_MMIO64       (BIT25 | BIT24)
 136 #define DTB_PCI_HOST_RANGE_IO           BIT24
 137 #define DTB_PCI_HOST_RANGE_TYPEMASK     (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
 138
 139 STATIC
 140 EFI_STATUS
 141 ProcessPciHost (
 142   OUT  UINT64    *IoBase,
 143   OUT  UINT64    *IoSize,
 144   OUT  UINT64    *IoTranslation,
 145   OUT  UINT64    *MmioBase,
 146   OUT  UINT64    *MmioSize,
 147   OUT  UINT64    *MmioTranslation,
 148   OUT  UINT32    *BusMin,
 149   OUT  UINT32    *BusMax
 150   )
 151 {
 152   FDT_CLIENT_PROTOCOL         *FdtClient;
 153   INT32                       Node;
 154   UINT64                      ConfigBase, ConfigSize;
 155   CONST VOID                  *Prop;
 156   UINT32                      Len;
 157   UINT32                      RecordIdx;
 158   EFI_STATUS                  Status;
 159
 160   //
 161   // The following output arguments are initialized only in
 162   // order to suppress '-Werror=maybe-uninitialized' warnings
 163   // *incorrectly* emitted by some gcc versions.
 164   //
 165   *IoBase = 0;
 166   *IoTranslation = 0;
 167   *MmioBase = 0;
 168   *MmioTranslation = 0;
 169   *BusMin = 0;
 170   *BusMax = 0;
 171
 172   //
 173   // *IoSize and *MmioSize are initialized to zero because the logic below
 174   // requires it. However, since they are also affected by the issue reported
 175   // above, they are initialized early.
 176   //
 177   *IoSize = 0;
 178   *MmioSize = 0;
 179
 180   Status = gBS->LocateProtocol (&gFdtClientProtocolGuid, NULL,
 181                   (VOID **)&FdtClient);
 182   ASSERT_EFI_ERROR (Status);
 183
 184   Status = FdtClient->FindCompatibleNode (FdtClient, "pci-host-ecam-generic",
 185                         &Node);
 186   if (EFI_ERROR (Status)) {
 187     DEBUG ((EFI_D_INFO,
 188       "%a: No 'pci-host-ecam-generic' compatible DT node found\n",
 189       __FUNCTION__));
 190     return EFI_NOT_FOUND;
 191   }
 192
 193   DEBUG_CODE (
 194     INT32 Tmp;
 195
 196     //
 197     // A DT can legally describe multiple PCI host bridges, but we are not
 198     // equipped to deal with that. So assert that there is only one.
 199     //
 200     Status = FdtClient->FindNextCompatibleNode (FdtClient,
 201                           "pci-host-ecam-generic", Node, &Tmp);
 202     ASSERT (Status == EFI_NOT_FOUND);
 203   );
 204
 205   Status = FdtClient->GetNodeProperty (FdtClient, Node, "reg", &Prop, &Len);
 206   if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT64)) {
 207     DEBUG ((EFI_D_ERROR, "%a: 'reg' property not found or invalid\n",
 208       __FUNCTION__));
 209     return EFI_PROTOCOL_ERROR;
 210   }
 211
 212   //
 213   // Fetch the ECAM window.
 214   //
 215   ConfigBase = SwapBytes64 (((CONST UINT64 *)Prop)[0]);
 216   ConfigSize = SwapBytes64 (((CONST UINT64 *)Prop)[1]);
 217
 218   //
 219   // Fetch the bus range (note: inclusive).
 220   //
 221   Status = FdtClient->GetNodeProperty (FdtClient, Node, "bus-range", &Prop,
 222                         &Len);
 223   if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT32)) {
 224     DEBUG ((EFI_D_ERROR, "%a: 'bus-range' not found or invalid\n",
 225       __FUNCTION__));
 226     return EFI_PROTOCOL_ERROR;
 227   }
 228   *BusMin = SwapBytes32 (((CONST UINT32 *)Prop)[0]);
 229   *BusMax = SwapBytes32 (((CONST UINT32 *)Prop)[1]);
 230
 231   //
 232   // Sanity check: the config space must accommodate all 4K register bytes of
 233   // all 8 functions of all 32 devices of all buses.
 234   //
 235   if (*BusMax < *BusMin || *BusMax - *BusMin == MAX_UINT32 ||
 236       DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < *BusMax - *BusMin + 1) {
 237     DEBUG ((EFI_D_ERROR, "%a: invalid 'bus-range' and/or 'reg'\n",
 238       __FUNCTION__));
 239     return EFI_PROTOCOL_ERROR;
 240   }
 241
 242   //
 243   // Iterate over "ranges".
 244   //
 245   Status = FdtClient->GetNodeProperty (FdtClient, Node, "ranges", &Prop, &Len);
 246   if (EFI_ERROR (Status) || Len == 0 ||
 247       Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0) {
 248     DEBUG ((EFI_D_ERROR, "%a: 'ranges' not found or invalid\n", __FUNCTION__));
 249     return EFI_PROTOCOL_ERROR;
 250   }
 251
 252   for (RecordIdx = 0; RecordIdx < Len / sizeof (DTB_PCI_HOST_RANGE_RECORD);
 253        ++RecordIdx) {
 254     CONST DTB_PCI_HOST_RANGE_RECORD *Record;
 255
 256     Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx;
 257     switch (SwapBytes32 (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK) {
 258     case DTB_PCI_HOST_RANGE_IO:
 259       *IoBase = SwapBytes64 (Record->ChildBase);
 260       *IoSize = SwapBytes64 (Record->Size);
 261       *IoTranslation = SwapBytes64 (Record->CpuBase) - *IoBase;
 262       break;
 263
 264     case DTB_PCI_HOST_RANGE_MMIO32:
 265       *MmioBase = SwapBytes64 (Record->ChildBase);
 266       *MmioSize = SwapBytes64 (Record->Size);
 267       *MmioTranslation = SwapBytes64 (Record->CpuBase) - *MmioBase;
 268
 269       if (*MmioBase > MAX_UINT32 || *MmioSize > MAX_UINT32 ||
 270           *MmioBase + *MmioSize > SIZE_4GB) {
 271         DEBUG ((EFI_D_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__));
 272         return EFI_PROTOCOL_ERROR;
 273       }
 274
 275       if (*MmioTranslation != 0) {
 276         DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO32 translation "
 277           "0x%Lx\n", __FUNCTION__, *MmioTranslation));
 278         return EFI_UNSUPPORTED;
 279       }
 280
 281       break;
 282     }
 283   }
 284   if (*IoSize == 0 || *MmioSize == 0) {
 285     DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__,
 286       (*IoSize == 0) ? "IO" : "MMIO32"));
 287     return EFI_PROTOCOL_ERROR;
 288   }
 289
 290   //
 291   // The dynamic PCD PcdPciExpressBaseAddress should have already been set,
 292   // and should match the value we found in the DT node.
 293   //
 294   ASSERT (PcdGet64 (PcdPciExpressBaseAddress) == ConfigBase);
 295
 296   SetLinuxPciProbeOnlyProperty (FdtClient);
 297
 298   DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "
 299     "Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x%Lx\n", __FUNCTION__, ConfigBase,
 300     ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, *IoTranslation, *MmioBase,
 301     *MmioSize, *MmioTranslation));
 302   return EFI_SUCCESS;
 303 }
 304
 305
 306 /**
 307   Entry point of this driver
 308
 309   @param ImageHandle     Handle of driver image
 310   @param SystemTable     Point to EFI_SYSTEM_TABLE
 311
 312   @retval EFI_ABORTED           PCI host bridge not present
 313   @retval EFI_OUT_OF_RESOURCES  Can not allocate memory resource
 314   @retval EFI_DEVICE_ERROR      Can not install the protocol instance
 315   @retval EFI_SUCCESS           Success to initialize the Pci host bridge.
 316 **/
 317 EFI_STATUS
 318 EFIAPI
 319 InitializePciHostBridge (
 320   IN EFI_HANDLE        ImageHandle,
 321   IN EFI_SYSTEM_TABLE  *SystemTable
 322   )
 323 {
 324   UINT64                      MmioAttributes;
 325   EFI_STATUS                  Status;
 326   UINTN                       Loop1;
 327   UINTN                       Loop2;
 328   PCI_HOST_BRIDGE_INSTANCE    *HostBridge;
 329   PCI_ROOT_BRIDGE_INSTANCE    *PrivateData;
 330   UINT64                      IoBase, IoSize, IoTranslation;
 331   UINT64                      MmioBase, MmioSize, MmioTranslation;
 332   UINT32                      BusMin, BusMax;
 333
 334   if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {
 335     DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));
 336     return EFI_ABORTED;
 337   }
 338
 339   Status = ProcessPciHost (&IoBase, &IoSize, &IoTranslation, &MmioBase,
 340              &MmioSize, &MmioTranslation, &BusMin, &BusMax);
 341   if (EFI_ERROR (Status)) {
 342     return Status;
 343   }
 344
 345   mDriverImageHandle = ImageHandle;
 346
 347   mResAperture[0][0].BusBase  = BusMin;
 348   mResAperture[0][0].BusLimit = BusMax;
 349
 350   mResAperture[0][0].MemBase  = MmioBase;
 351   mResAperture[0][0].MemLimit = MmioBase + MmioSize - 1;
 352
 353   mResAperture[0][0].IoBase        = IoBase;
 354   mResAperture[0][0].IoLimit       = IoBase + IoSize - 1;
 355   mResAperture[0][0].IoTranslation = IoTranslation;
 356
 357   //
 358   // Add IO and MMIO memory space, so that resources can be allocated in the
 359   // EfiPciHostBridgeAllocateResources phase.
 360   //
 361   Status = gDS->AddIoSpace (
 362                   EfiGcdIoTypeIo,
 363                   IoBase,
 364                   IoSize
 365                   );
 366   ASSERT_EFI_ERROR (Status);
 367
 368   MmioAttributes = EFI_MEMORY_UC;
 369
 370   Status = gDS->AddMemorySpace (
 371                   EfiGcdMemoryTypeMemoryMappedIo,
 372                   MmioBase,
 373                   MmioSize,
 374                   MmioAttributes
 375                   );
 376   if (EFI_ERROR (Status)) {
 377     DEBUG ((EFI_D_ERROR, "%a: AddMemorySpace: %r\n", __FUNCTION__, Status));
 378     return Status;
 379   }
 380
 381   Status = gDS->SetMemorySpaceAttributes (
 382                   MmioBase,
 383                   MmioSize,
 384                   MmioAttributes
 385                   );
 386   if (EFI_ERROR (Status)) {
 387     DEBUG ((EFI_D_ERROR, "%a: SetMemorySpaceAttributes: %r\n", __FUNCTION__,
 388       Status));
 389     return Status;
 390   }
 391
 392   //
 393   // Create Host Bridge Device Handle
 394   //
 395   for (Loop1 = 0; Loop1 < HOST_BRIDGE_NUMBER; Loop1++) {
 396     HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE), &mPciHostBridgeInstanceTemplate);
 397     if (HostBridge == NULL) {
 398       return EFI_OUT_OF_RESOURCES;
 399     }
 400
 401     HostBridge->RootBridgeNumber = RootBridgeNumber[Loop1];
 402     InitializeListHead (&HostBridge->Head);
 403
 404     Status = gBS->InstallMultipleProtocolInterfaces (
 405                     &HostBridge->HostBridgeHandle,
 406                     &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,
 407                     NULL
 408                     );
 409     if (EFI_ERROR (Status)) {
 410       FreePool (HostBridge);
 411       return EFI_DEVICE_ERROR;
 412     }
 413
 414     //
 415     // Create Root Bridge Device Handle in this Host Bridge
 416     //
 417
 418     for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) {
 419       PrivateData = AllocateZeroPool (sizeof(PCI_ROOT_BRIDGE_INSTANCE));
 420       if (PrivateData == NULL) {
 421         return EFI_OUT_OF_RESOURCES;
 422       }
 423
 424       PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
 425       PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2];
 426
 427       RootBridgeConstructor (
 428         &PrivateData->Io,
 429         HostBridge->HostBridgeHandle,
 430         RootBridgeAttribute[Loop1][Loop2],
 431         &mResAperture[Loop1][Loop2]
 432         );
 433
 434       Status = gBS->InstallMultipleProtocolInterfaces(
 435                       &PrivateData->Handle,
 436                       &gEfiDevicePathProtocolGuid,      PrivateData->DevicePath,
 437                       &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io,
 438                       NULL
 439                       );
 440       if (EFI_ERROR (Status)) {
 441         FreePool(PrivateData);
 442         return EFI_DEVICE_ERROR;
 443       }
 444
 445       InsertTailList (&HostBridge->Head, &PrivateData->Link);
 446     }
 447   }
 448
 449   return EFI_SUCCESS;
 450 }
 451
 452
 453 /**
 454    These are the notifications from the PCI bus driver that it is about to enter a certain
 455    phase of the PCI enumeration process.
 456
 457    This member function can be used to notify the host bridge driver to perform specific actions,
 458    including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
 459    Eight notification points are defined at this time. See belows:
 460    EfiPciHostBridgeBeginEnumeration       Resets the host bridge PCI apertures and internal data
 461                                           structures. The PCI enumerator should issue this notification
 462                                           before starting a fresh enumeration process. Enumeration cannot
 463                                           be restarted after sending any other notification such as
 464                                           EfiPciHostBridgeBeginBusAllocation.
 465    EfiPciHostBridgeBeginBusAllocation     The bus allocation phase is about to begin. No specific action is
 466                                           required here. This notification can be used to perform any
 467                                           chipset-specific programming.
 468    EfiPciHostBridgeEndBusAllocation       The bus allocation and bus programming phase is complete. No
 469                                           specific action is required here. This notification can be used to
 470                                           perform any chipset-specific programming.
 471    EfiPciHostBridgeBeginResourceAllocation
 472                                           The resource allocation phase is about to begin. No specific
 473                                           action is required here. This notification can be used to perform
 474                                           any chipset-specific programming.
 475    EfiPciHostBridgeAllocateResources      Allocates resources per previously submitted requests for all the PCI
 476                                           root bridges. These resource settings are returned on the next call to
 477                                           GetProposedResources(). Before calling NotifyPhase() with a Phase of
 478                                           EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
 479                                           for gathering I/O and memory requests for
 480                                           all the PCI root bridges and submitting these requests using
 481                                           SubmitResources(). This function pads the resource amount
 482                                           to suit the root bridge hardware, takes care of dependencies between
 483                                           the PCI root bridges, and calls the Global Coherency Domain (GCD)
 484                                           with the allocation request. In the case of padding, the allocated range
 485                                           could be bigger than what was requested.
 486    EfiPciHostBridgeSetResources           Programs the host bridge hardware to decode previously allocated
 487                                           resources (proposed resources) for all the PCI root bridges. After the
 488                                           hardware is programmed, reassigning resources will not be supported.
 489                                           The bus settings are not affected.
 490    EfiPciHostBridgeFreeResources          Deallocates resources that were previously allocated for all the PCI
 491                                           root bridges and resets the I/O and memory apertures to their initial
 492                                           state. The bus settings are not affected. If the request to allocate
 493                                           resources fails, the PCI enumerator can use this notification to
 494                                           deallocate previous resources, adjust the requests, and retry
 495                                           allocation.
 496    EfiPciHostBridgeEndResourceAllocation  The resource allocation phase is completed. No specific action is
 497                                           required here. This notification can be used to perform any chipsetspecific
 498                                           programming.
 499
 500    @param[in] This                The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
 501    @param[in] Phase               The phase during enumeration
 502
 503    @retval EFI_NOT_READY          This phase cannot be entered at this time. For example, this error
 504                                   is valid for a Phase of EfiPciHostBridgeAllocateResources if
 505                                   SubmitResources() has not been called for one or more
 506                                   PCI root bridges before this call
 507    @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error. This error is valid
 508                                   for a Phase of EfiPciHostBridgeSetResources.
 509    @retval EFI_INVALID_PARAMETER  Invalid phase parameter
 510    @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
 511                                   This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
 512                                   previously submitted resource requests cannot be fulfilled or
 513                                   were only partially fulfilled.
 514    @retval EFI_SUCCESS            The notification was accepted without any errors.
 515
 516 **/
 517 EFI_STATUS
 518 EFIAPI
 519 NotifyPhase(
 520   IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
 521   IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE    Phase
 522   )
 523 {
 524   PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
 525   PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
 526   PCI_RESOURCE_TYPE                     Index;
 527   LIST_ENTRY                            *List;
 528   EFI_PHYSICAL_ADDRESS                  BaseAddress;
 529   UINT64                                AddrLen;
 530   UINTN                                 BitsOfAlignment;
 531   EFI_STATUS                            Status;
 532   EFI_STATUS                            ReturnStatus;
 533
 534   HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
 535
 536   switch (Phase) {
 537
 538   case EfiPciHostBridgeBeginEnumeration:
 539     if (HostBridgeInstance->CanRestarted) {
 540       //
 541       // Reset the Each Root Bridge
 542       //
 543       List = HostBridgeInstance->Head.ForwardLink;
 544
 545       while (List != &HostBridgeInstance->Head) {
 546         RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
 547         for (Index = TypeIo; Index < TypeMax; Index++) {
 548           RootBridgeInstance->ResAllocNode[Index].Type      = Index;
 549           RootBridgeInstance->ResAllocNode[Index].Base      = 0;
 550           RootBridgeInstance->ResAllocNode[Index].Length    = 0;
 551           RootBridgeInstance->ResAllocNode[Index].Status    = ResNone;
 552         }
 553
 554         List = List->ForwardLink;
 555       }
 556
 557       HostBridgeInstance->ResourceSubmited = FALSE;
 558       HostBridgeInstance->CanRestarted     = TRUE;
 559     } else {
 560       //
 561       // Can not restart
 562       //
 563       return EFI_NOT_READY;
 564     }
 565     break;
 566
 567   case EfiPciHostBridgeEndEnumeration:
 568     break;
 569
 570   case EfiPciHostBridgeBeginBusAllocation:
 571     //
 572     // No specific action is required here, can perform any chipset specific programing
 573     //
 574     HostBridgeInstance->CanRestarted = FALSE;
 575     break;
 576
 577   case EfiPciHostBridgeEndBusAllocation:
 578     //
 579     // No specific action is required here, can perform any chipset specific programing
 580     //
 581     //HostBridgeInstance->CanRestarted = FALSE;
 582     break;
 583
 584   case EfiPciHostBridgeBeginResourceAllocation:
 585     //
 586     // No specific action is required here, can perform any chipset specific programing
 587     //
 588     //HostBridgeInstance->CanRestarted = FALSE;
 589     break;
 590
 591   case EfiPciHostBridgeAllocateResources:
 592     ReturnStatus = EFI_SUCCESS;
 593     if (HostBridgeInstance->ResourceSubmited) {
 594       //
 595       // Take care of the resource dependencies between the root bridges
 596       //
 597       List = HostBridgeInstance->Head.ForwardLink;
 598
 599       while (List != &HostBridgeInstance->Head) {
 600         RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
 601         for (Index = TypeIo; Index < TypeBus; Index++) {
 602           if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
 603
 604             AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
 605
 606             //
 607             // Get the number of '1' in Alignment.
 608             //
 609             BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);
 610
 611             switch (Index) {
 612
 613               case TypeIo:
 614                 //
 615                 // It is impossible for this chipset to align 0xFFFF for IO16
 616                 // So clear it
 617                 //
 618                 if (BitsOfAlignment >= 16) {
 619                   BitsOfAlignment = 0;
 620                 }
 621
 622                 BaseAddress = mResAperture[0][0].IoLimit;
 623                 Status = gDS->AllocateIoSpace (
 624                                 EfiGcdAllocateMaxAddressSearchTopDown,
 625                                 EfiGcdIoTypeIo,
 626                                 BitsOfAlignment,
 627                                 AddrLen,
 628                                 &BaseAddress,
 629                                 mDriverImageHandle,
 630                                 NULL
 631                                 );
 632
 633                 if (!EFI_ERROR (Status)) {
 634                   RootBridgeInstance->ResAllocNode[Index].Base   = (UINTN)BaseAddress;
 635                   RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;
 636                 } else {
 637                   ReturnStatus = Status;
 638                   if (Status != EFI_OUT_OF_RESOURCES) {
 639                     RootBridgeInstance->ResAllocNode[Index].Length = 0;
 640                   }
 641                 }
 642
 643                 break;
 644
 645
 646               case TypeMem32:
 647                 //
 648                 // It is impossible for this chipset to align 0xFFFFFFFF for Mem32
 649                 // So clear it
 650                 //
 651
 652                 if (BitsOfAlignment >= 32) {
 653                   BitsOfAlignment = 0;
 654                 }
 655
 656                 BaseAddress = mResAperture[0][0].MemLimit;
 657                 Status = gDS->AllocateMemorySpace (
 658                                 EfiGcdAllocateMaxAddressSearchTopDown,
 659                                 EfiGcdMemoryTypeMemoryMappedIo,
 660                                 BitsOfAlignment,
 661                                 AddrLen,
 662                                 &BaseAddress,
 663                                 mDriverImageHandle,
 664                                 NULL
 665                                 );
 666
 667                 if (!EFI_ERROR (Status)) {
 668                   // We were able to allocate the PCI memory
 669                   RootBridgeInstance->ResAllocNode[Index].Base   = (UINTN)BaseAddress;
 670                   RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;
 671
 672                 } else {
 673                   // Not able to allocate enough PCI memory
 674                   ReturnStatus = Status;
 675
 676                   if (Status != EFI_OUT_OF_RESOURCES) {
 677                     RootBridgeInstance->ResAllocNode[Index].Length = 0;
 678                   }
 679                   ASSERT (FALSE);
 680                 }
 681                 break;
 682
 683               case TypePMem32:
 684               case TypeMem64:
 685               case TypePMem64:
 686                   ReturnStatus = EFI_ABORTED;
 687                   break;
 688               default:
 689                 ASSERT (FALSE);
 690                 break;
 691               }; //end switch
 692           }
 693         }
 694
 695         List = List->ForwardLink;
 696       }
 697
 698       return ReturnStatus;
 699     } else {
 700       return EFI_NOT_READY;
 701     }
 702
 703   case EfiPciHostBridgeSetResources:
 704     break;
 705
 706   case EfiPciHostBridgeFreeResources:
 707     ReturnStatus = EFI_SUCCESS;
 708     List = HostBridgeInstance->Head.ForwardLink;
 709     while (List != &HostBridgeInstance->Head) {
 710       RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
 711       for (Index = TypeIo; Index < TypeBus; Index++) {
 712         if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {
 713           AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
 714           BaseAddress = RootBridgeInstance->ResAllocNode[Index].Base;
 715           switch (Index) {
 716
 717           case TypeIo:
 718             Status = gDS->FreeIoSpace (BaseAddress, AddrLen);
 719             if (EFI_ERROR (Status)) {
 720               ReturnStatus = Status;
 721             }
 722             break;
 723
 724           case TypeMem32:
 725             Status = gDS->FreeMemorySpace (BaseAddress, AddrLen);
 726             if (EFI_ERROR (Status)) {
 727               ReturnStatus = Status;
 728             }
 729             break;
 730
 731           case TypePMem32:
 732             break;
 733
 734           case TypeMem64:
 735             break;
 736
 737           case TypePMem64:
 738             break;
 739
 740           default:
 741             ASSERT (FALSE);
 742             break;
 743
 744           }; //end switch
 745           RootBridgeInstance->ResAllocNode[Index].Type      = Index;
 746           RootBridgeInstance->ResAllocNode[Index].Base      = 0;
 747           RootBridgeInstance->ResAllocNode[Index].Length    = 0;
 748           RootBridgeInstance->ResAllocNode[Index].Status    = ResNone;
 749         }
 750       }
 751
 752       List = List->ForwardLink;
 753     }
 754
 755     HostBridgeInstance->ResourceSubmited = FALSE;
 756     HostBridgeInstance->CanRestarted     = TRUE;
 757     return ReturnStatus;
 758
 759   case EfiPciHostBridgeEndResourceAllocation:
 760     HostBridgeInstance->CanRestarted = FALSE;
 761     break;
 762
 763   default:
 764     return EFI_INVALID_PARAMETER;
 765   }
 766
 767   return EFI_SUCCESS;
 768 }
 769
 770 /**
 771    Return the device handle of the next PCI root bridge that is associated with this Host Bridge.
 772
 773    This function is called multiple times to retrieve the device handles of all the PCI root bridges that
 774    are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI
 775    root bridges. On each call, the handle that was returned by the previous call is passed into the
 776    interface, and on output the interface returns the device handle of the next PCI root bridge. The
 777    caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
 778    for that root bridge. When there are no more PCI root bridges to report, the interface returns
 779    EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they
 780    are returned by this function.
 781    For D945 implementation, there is only one root bridge in PCI host bridge.
 782
 783    @param[in]       This              The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
 784    @param[in, out]  RootBridgeHandle  Returns the device handle of the next PCI root bridge.
 785
 786    @retval EFI_SUCCESS            If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the
 787                                   specific Host bridge and return EFI_SUCCESS.
 788    @retval EFI_NOT_FOUND          Can not find the any more root bridge in specific host bridge.
 789    @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not an EFI_HANDLE that was
 790                                   returned on a previous call to GetNextRootBridge().
 791 **/
 792 EFI_STATUS
 793 EFIAPI
 794 GetNextRootBridge(
 795   IN       EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
 796   IN OUT   EFI_HANDLE                                       *RootBridgeHandle
 797   )
 798 {
 799   BOOLEAN                               NoRootBridge;
 800   LIST_ENTRY                            *List;
 801   PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
 802   PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
 803
 804   NoRootBridge = TRUE;
 805   HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
 806   List = HostBridgeInstance->Head.ForwardLink;
 807
 808
 809   while (List != &HostBridgeInstance->Head) {
 810     NoRootBridge = FALSE;
 811     RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
 812     if (*RootBridgeHandle == NULL) {
 813       //
 814       // Return the first Root Bridge Handle of the Host Bridge
 815       //
 816       *RootBridgeHandle = RootBridgeInstance->Handle;
 817       return EFI_SUCCESS;
 818     } else {
 819       if (*RootBridgeHandle == RootBridgeInstance->Handle) {
 820         //
 821         // Get next if have
 822         //
 823         List = List->ForwardLink;
 824         if (List!=&HostBridgeInstance->Head) {
 825           RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
 826           *RootBridgeHandle = RootBridgeInstance->Handle;
 827           return EFI_SUCCESS;
 828         } else {
 829           return EFI_NOT_FOUND;
 830         }
 831       }
 832     }
 833
 834     List = List->ForwardLink;
 835   } //end while
 836
 837   if (NoRootBridge) {
 838     return EFI_NOT_FOUND;
 839   } else {
 840     return EFI_INVALID_PARAMETER;
 841   }
 842 }
 843
 844 /**
 845    Returns the allocation attributes of a PCI root bridge.
 846
 847    The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary
 848    from one PCI root bridge to another. These attributes are different from the decode-related
 849    attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
 850    RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device
 851    handles of all the root bridges that are associated with this host bridge must be obtained by calling
 852    GetNextRootBridge(). The attributes are static in the sense that they do not change during or
 853    after the enumeration process. The hardware may provide mechanisms to change the attributes on
 854    the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is
 855    installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
 856    "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.
 857    For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to
 858    include requests for the prefetchable memory in the nonprefetchable memory pool and not request any
 859    prefetchable memory.
 860       Attribute                                 Description
 861    ------------------------------------         ----------------------------------------------------------------------
 862    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM         If this bit is set, then the PCI root bridge does not support separate
 863                                                 windows for nonprefetchable and prefetchable memory. A PCI bus
 864                                                 driver needs to include requests for prefetchable memory in the
 865                                                 nonprefetchable memory pool.
 866
 867    EFI_PCI_HOST_BRIDGE_MEM64_DECODE             If this bit is set, then the PCI root bridge supports 64-bit memory
 868                                                 windows. If this bit is not set, the PCI bus driver needs to include
 869                                                 requests for a 64-bit memory address in the corresponding 32-bit
 870                                                 memory pool.
 871
 872    @param[in]   This               The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
 873    @param[in]   RootBridgeHandle   The device handle of the PCI root bridge in which the caller is interested. Type
 874                                    EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
 875    @param[out]  Attributes         The pointer to attribte of root bridge, it is output parameter
 876
 877    @retval EFI_INVALID_PARAMETER   Attribute pointer is NULL
 878    @retval EFI_INVALID_PARAMETER   RootBridgehandle is invalid.
 879    @retval EFI_SUCCESS             Success to get attribute of interested root bridge.
 880
 881 **/
 882 EFI_STATUS
 883 EFIAPI
 884 GetAttributes(
 885   IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
 886   IN  EFI_HANDLE                                       RootBridgeHandle,
 887   OUT UINT64                                           *Attributes
 888   )
 889 {
 890   LIST_ENTRY                            *List;
 891   PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
 892   PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
 893
 894   if (Attributes == NULL) {
 895     return EFI_INVALID_PARAMETER;
 896   }
 897
 898   HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
 899   List = HostBridgeInstance->Head.ForwardLink;
 900
 901   while (List != &HostBridgeInstance->Head) {
 902     RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
 903     if (RootBridgeHandle == RootBridgeInstance->Handle) {
 904       *Attributes = RootBridgeInstance->RootBridgeAttrib;
 905       return EFI_SUCCESS;
 906     }
 907     List = List->ForwardLink;
 908   }
 909
 910   //
 911   // RootBridgeHandle is not an EFI_HANDLE
 912   // that was returned on a previous call to GetNextRootBridge()
 913   //
 914   return EFI_INVALID_PARAMETER;
 915 }
 916
 917 /**
 918    Sets up the specified PCI root bridge for the bus enumeration process.
 919
 920    This member function sets up the root bridge for bus enumeration and returns the PCI bus range
 921    over which the search should be performed in ACPI 2.0 resource descriptor format.
 922
 923    @param[in]   This              The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
 924    @param[in]   RootBridgeHandle  The PCI Root Bridge to be set up.
 925    @param[out]  Configuration     Pointer to the pointer to the PCI bus resource descriptor.
 926
 927    @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
 928    @retval EFI_OUT_OF_RESOURCES  Fail to allocate ACPI resource descriptor tag.
 929    @retval EFI_SUCCESS           Sucess to allocate ACPI resource descriptor.
 930
 931 **/
 932 EFI_STATUS
 933 EFIAPI
 934 StartBusEnumeration(
 935   IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
 936   IN  EFI_HANDLE                                       RootBridgeHandle,
 937   OUT VOID                                             **Configuration
 938   )
 939 {
 940   LIST_ENTRY                            *List;
 941   PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
 942   PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
 943   VOID                                  *Buffer;
 944   UINT8                                 *Temp;
 945   UINT64                                BusStart;
 946   UINT64                                BusEnd;
 947
 948   HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
 949   List = HostBridgeInstance->Head.ForwardLink;
 950
 951   while (List != &HostBridgeInstance->Head) {
 952     RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
 953     if (RootBridgeHandle == RootBridgeInstance->Handle) {
 954       //
 955       // Set up the Root Bridge for Bus Enumeration
 956       //
 957       BusStart = RootBridgeInstance->BusBase;
 958       BusEnd   = RootBridgeInstance->BusLimit;
 959       //
 960       // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR
 961       //
 962
 963       Buffer = AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
 964       if (Buffer == NULL) {
 965         return EFI_OUT_OF_RESOURCES;
 966       }
 967
 968       Temp = (UINT8 *)Buffer;
 969
 970       ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = 0x8A;
 971       ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len  = 0x2B;
 972       ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = 2;
 973       ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0;
 974       ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = 0;
 975       ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = 0;
 976       ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;
 977       ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;
 978       ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;
 979       ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = BusEnd - BusStart + 1;
 980
 981       Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
 982       ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
 983       ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
 984
 985       *Configuration = Buffer;
 986       return EFI_SUCCESS;
 987     }
 988     List = List->ForwardLink;
 989   }
 990
 991   return EFI_INVALID_PARAMETER;
 992 }
 993
 994 /**
 995    Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
 996
 997    This member function programs the specified PCI root bridge to decode the bus range that is
 998    specified by the input parameter Configuration.
 999    The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.
1000
1001    @param[in] This              The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
1002    @param[in] RootBridgeHandle  The PCI Root Bridge whose bus range is to be programmed
1003    @param[in] Configuration     The pointer to the PCI bus resource descriptor
1004
1005    @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.
1006    @retval EFI_INVALID_PARAMETER  Configuration is NULL.
1007    @retval EFI_INVALID_PARAMETER  Configuration does not point to a valid ACPI 2.0 resource descriptor.
1008    @retval EFI_INVALID_PARAMETER  Configuration does not include a valid ACPI 2.0 bus resource descriptor.
1009    @retval EFI_INVALID_PARAMETER  Configuration includes valid ACPI 2.0 resource descriptors other than
1010                                   bus descriptors.
1011    @retval EFI_INVALID_PARAMETER  Configuration contains one or more invalid ACPI resource descriptors.
1012    @retval EFI_INVALID_PARAMETER  "Address Range Minimum" is invalid for this root bridge.
1013    @retval EFI_INVALID_PARAMETER  "Address Range Length" is invalid for this root bridge.
1014    @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error.
1015    @retval EFI_SUCCESS            The bus range for the PCI root bridge was programmed.
1016
1017 **/
1018 EFI_STATUS
1019 EFIAPI
1020 SetBusNumbers(
1021   IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
1022   IN EFI_HANDLE                                       RootBridgeHandle,
1023   IN VOID                                             *Configuration
1024   )
1025 {
1026   LIST_ENTRY                            *List;
1027   PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
1028   PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
1029   UINT8                                 *Ptr;
1030   UINTN                                 BusStart;
1031   UINTN                                 BusEnd;
1032   UINTN                                 BusLen;
1033
1034   if (Configuration == NULL) {
1035     return EFI_INVALID_PARAMETER;
1036   }
1037
1038   Ptr = Configuration;
1039
1040   //
1041   // Check the Configuration is valid
1042   //
1043   if(*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {
1044     return EFI_INVALID_PARAMETER;
1045   }
1046
1047   if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != 2) {
1048     return EFI_INVALID_PARAMETER;
1049   }
1050
1051   Ptr += sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
1052   if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {
1053     return EFI_INVALID_PARAMETER;
1054   }
1055
1056   HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
1057   List = HostBridgeInstance->Head.ForwardLink;
1058
1059   Ptr = Configuration;
1060
1061   while (List != &HostBridgeInstance->Head) {
1062     RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
1063     if (RootBridgeHandle == RootBridgeInstance->Handle) {
1064       BusStart = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin;
1065       BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen;
1066       BusEnd = BusStart + BusLen - 1;
1067
1068       if (BusStart > BusEnd) {
1069         return EFI_INVALID_PARAMETER;
1070       }
1071
1072       if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) {
1073         return EFI_INVALID_PARAMETER;
1074       }
1075
1076       //
1077       // Update the Bus Range
1078       //
1079       RootBridgeInstance->ResAllocNode[TypeBus].Base   = BusStart;
1080       RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen;
1081       RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated;
1082
1083       //
1084       // Program the Root Bridge Hardware
1085       //
1086
1087       return EFI_SUCCESS;
1088     }
1089
1090     List = List->ForwardLink;
1091   }
1092
1093   return EFI_INVALID_PARAMETER;
1094 }
1095
1096
1097 /**
1098    Submits the I/O and memory resource requirements for the specified PCI root bridge.
1099
1100    This function is used to submit all the I/O and memory resources that are required by the specified
1101    PCI root bridge. The input parameter Configuration is used to specify the following:
1102    - The various types of resources that are required
1103    - The associated lengths in terms of ACPI 2.0 resource descriptor format
1104
1105    @param[in] This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1106    @param[in] RootBridgeHandle  The PCI root bridge whose I/O and memory resource requirements are being submitted.
1107    @param[in] Configuration     The pointer to the PCI I/O and PCI memory resource descriptor.
1108
1109    @retval EFI_SUCCESS            The I/O and memory resource requests for a PCI root bridge were accepted.
1110    @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.
1111    @retval EFI_INVALID_PARAMETER  Configuration is NULL.
1112    @retval EFI_INVALID_PARAMETER  Configuration does not point to a valid ACPI 2.0 resource descriptor.
1113    @retval EFI_INVALID_PARAMETER  Configuration includes requests for one or more resource types that are
1114                                   not supported by this PCI root bridge. This error will happen if the caller
1115                                   did not combine resources according to Attributes that were returned by
1116                                   GetAllocAttributes().
1117    @retval EFI_INVALID_PARAMETER  Address Range Maximum" is invalid.
1118    @retval EFI_INVALID_PARAMETER  "Address Range Length" is invalid for this PCI root bridge.
1119    @retval EFI_INVALID_PARAMETER  "Address Space Granularity" is invalid for this PCI root bridge.
1120
1121 **/
1122 EFI_STATUS
1123 EFIAPI
1124 SubmitResources(
1125   IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
1126   IN EFI_HANDLE                                       RootBridgeHandle,
1127   IN VOID                                             *Configuration
1128   )
1129 {
1130   LIST_ENTRY                            *List;
1131   PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
1132   PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
1133   UINT8                                 *Temp;
1134   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     *Ptr;
1135   UINT64                                AddrLen;
1136   UINT64                                Alignment;
1137
1138   //
1139   // Check the input parameter: Configuration
1140   //
1141   if (Configuration == NULL) {
1142     return EFI_INVALID_PARAMETER;
1143   }
1144
1145   HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
1146   List = HostBridgeInstance->Head.ForwardLink;
1147
1148   Temp = (UINT8 *)Configuration;
1149   while ( *Temp == 0x8A) {
1150     Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;
1151   }
1152   if (*Temp != 0x79) {
1153     return EFI_INVALID_PARAMETER;
1154   }
1155
1156   Temp = (UINT8 *)Configuration;
1157   while (List != &HostBridgeInstance->Head) {
1158     RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
1159     if (RootBridgeHandle == RootBridgeInstance->Handle) {
1160       for (;
1161            *Temp == 0x8A;
1162            Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR)
1163            ) {
1164         Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
1165
1166         //
1167         // Check Address Length
1168         //
1169         if (Ptr->AddrLen == 0) {
1170           HostBridgeInstance->ResourceSubmited = TRUE;
1171           continue;
1172         }
1173         if (Ptr->AddrLen > 0xffffffff) {
1174           return EFI_INVALID_PARAMETER;
1175         }
1176
1177         //
1178         // Check address range alignment
1179         //
1180         if (Ptr->AddrRangeMax >= 0xffffffff || Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {
1181           return EFI_INVALID_PARAMETER;
1182         }
1183
1184         switch (Ptr->ResType) {
1185
1186         case 0:
1187
1188           //
1189           // Check invalid Address Sapce Granularity
1190           //
1191           if (Ptr->AddrSpaceGranularity != 32) {
1192             return EFI_INVALID_PARAMETER;
1193           }
1194
1195           //
1196           // check the memory resource request is supported by PCI root bridge
1197           //
1198           if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&
1199                Ptr->SpecificFlag == 0x06) {
1200             return EFI_INVALID_PARAMETER;
1201           }
1202
1203           AddrLen = Ptr->AddrLen;
1204           Alignment = Ptr->AddrRangeMax;
1205           if (Ptr->AddrSpaceGranularity == 32) {
1206             if (Ptr->SpecificFlag == 0x06) {
1207               //
1208               // Apply from GCD
1209               //
1210               RootBridgeInstance->ResAllocNode[TypePMem32].Status = ResSubmitted;
1211             } else {
1212               RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen;
1213               RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = Alignment;
1214               RootBridgeInstance->ResAllocNode[TypeMem32].Status = ResRequested;
1215               HostBridgeInstance->ResourceSubmited = TRUE;
1216             }
1217           }
1218
1219           if (Ptr->AddrSpaceGranularity == 64) {
1220             if (Ptr->SpecificFlag == 0x06) {
1221               RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;
1222             } else {
1223               RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;
1224             }
1225           }
1226           break;
1227
1228         case 1:
1229           AddrLen = (UINTN) Ptr->AddrLen;
1230           Alignment = (UINTN) Ptr->AddrRangeMax;
1231           RootBridgeInstance->ResAllocNode[TypeIo].Length  = AddrLen;
1232           RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;
1233           RootBridgeInstance->ResAllocNode[TypeIo].Status  = ResRequested;
1234           HostBridgeInstance->ResourceSubmited = TRUE;
1235           break;
1236
1237         default:
1238             break;
1239         };
1240       }
1241
1242       return EFI_SUCCESS;
1243     }
1244
1245     List = List->ForwardLink;
1246   }
1247
1248   return EFI_INVALID_PARAMETER;
1249 }
1250
1251 /**
1252    Returns the proposed resource settings for the specified PCI root bridge.
1253
1254    This member function returns the proposed resource settings for the specified PCI root bridge. The
1255    proposed resource settings are prepared when NotifyPhase() is called with a Phase of
1256    EfiPciHostBridgeAllocateResources. The output parameter Configuration
1257    specifies the following:
1258    - The various types of resources, excluding bus resources, that are allocated
1259    - The associated lengths in terms of ACPI 2.0 resource descriptor format
1260
1261    @param[in]  This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1262    @param[in]  RootBridgeHandle  The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
1263    @param[out] Configuration     The pointer to the pointer to the PCI I/O and memory resource descriptor.
1264
1265    @retval EFI_SUCCESS            The requested parameters were returned.
1266    @retval EFI_INVALID_PARAMETER  RootBridgeHandle is not a valid root bridge handle.
1267    @retval EFI_DEVICE_ERROR       Programming failed due to a hardware error.
1268    @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.
1269
1270 **/
1271 EFI_STATUS
1272 EFIAPI
1273 GetProposedResources(
1274   IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
1275   IN  EFI_HANDLE                                       RootBridgeHandle,
1276   OUT VOID                                             **Configuration
1277   )
1278 {
1279   LIST_ENTRY                            *List;
1280   PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
1281   PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
1282   UINTN                                 Index;
1283   UINTN                                 Number;
1284   VOID                                  *Buffer;
1285   UINT8                                 *Temp;
1286   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     *Ptr;
1287   UINT64                                ResStatus;
1288
1289   Buffer = NULL;
1290   Number = 0;
1291   //
1292   // Get the Host Bridge Instance from the resource allocation protocol
1293   //
1294   HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
1295   List = HostBridgeInstance->Head.ForwardLink;
1296
1297   //
1298   // Enumerate the root bridges in this host bridge
1299   //
1300   while (List != &HostBridgeInstance->Head) {
1301     RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
1302     if (RootBridgeHandle == RootBridgeInstance->Handle) {
1303       for (Index = 0; Index < TypeBus; Index ++) {
1304         if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
1305           Number ++;
1306         }
1307       }
1308
1309       if (Number ==  0) {
1310         EFI_ACPI_END_TAG_DESCRIPTOR *End;
1311
1312         End = AllocateZeroPool (sizeof *End);
1313         if (End == NULL) {
1314           return EFI_OUT_OF_RESOURCES;
1315         }
1316         End->Desc = ACPI_END_TAG_DESCRIPTOR;
1317         *Configuration = End;
1318         return EFI_SUCCESS;
1319       }
1320
1321       Buffer = AllocateZeroPool (Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
1322       if (Buffer == NULL) {
1323         return EFI_OUT_OF_RESOURCES;
1324       }
1325
1326       Temp = Buffer;
1327       for (Index = 0; Index < TypeBus; Index ++) {
1328         if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
1329           Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
1330           ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;
1331
1332           switch (Index) {
1333
1334           case TypeIo:
1335             //
1336             // Io
1337             //
1338             Ptr->Desc = 0x8A;
1339             Ptr->Len  = 0x2B;
1340             Ptr->ResType = 1;
1341             Ptr->GenFlag = 0;
1342             Ptr->SpecificFlag = 0;
1343             Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
1344             Ptr->AddrRangeMax = 0;
1345             Ptr->AddrTranslationOffset = \
1346                  (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
1347             Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
1348             break;
1349
1350           case TypeMem32:
1351             //
1352             // Memory 32
1353             //
1354             Ptr->Desc = 0x8A;
1355             Ptr->Len  = 0x2B;
1356             Ptr->ResType = 0;
1357             Ptr->GenFlag = 0;
1358             Ptr->SpecificFlag = 0;
1359             Ptr->AddrSpaceGranularity = 32;
1360             Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
1361             Ptr->AddrRangeMax = 0;
1362             Ptr->AddrTranslationOffset = \
1363                  (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
1364             Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
1365             break;
1366
1367           case TypePMem32:
1368             //
1369             // Prefetch memory 32
1370             //
1371             Ptr->Desc = 0x8A;
1372             Ptr->Len  = 0x2B;
1373             Ptr->ResType = 0;
1374             Ptr->GenFlag = 0;
1375             Ptr->SpecificFlag = 6;
1376             Ptr->AddrSpaceGranularity = 32;
1377             Ptr->AddrRangeMin = 0;
1378             Ptr->AddrRangeMax = 0;
1379             Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
1380             Ptr->AddrLen = 0;
1381             break;
1382
1383           case TypeMem64:
1384             //
1385             // Memory 64
1386             //
1387             Ptr->Desc = 0x8A;
1388             Ptr->Len  = 0x2B;
1389             Ptr->ResType = 0;
1390             Ptr->GenFlag = 0;
1391             Ptr->SpecificFlag = 0;
1392             Ptr->AddrSpaceGranularity = 64;
1393             Ptr->AddrRangeMin = 0;
1394             Ptr->AddrRangeMax = 0;
1395             Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
1396             Ptr->AddrLen = 0;
1397             break;
1398
1399           case TypePMem64:
1400             //
1401             // Prefetch memory 64
1402             //
1403             Ptr->Desc = 0x8A;
1404             Ptr->Len  = 0x2B;
1405             Ptr->ResType = 0;
1406             Ptr->GenFlag = 0;
1407             Ptr->SpecificFlag = 6;
1408             Ptr->AddrSpaceGranularity = 64;
1409             Ptr->AddrRangeMin = 0;
1410             Ptr->AddrRangeMax = 0;
1411             Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
1412             Ptr->AddrLen = 0;
1413             break;
1414           };
1415
1416           Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
1417         }
1418       }
1419
1420       ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
1421       ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
1422
1423       *Configuration = Buffer;
1424
1425       return EFI_SUCCESS;
1426     }
1427
1428     List = List->ForwardLink;
1429   }
1430
1431   return EFI_INVALID_PARAMETER;
1432 }
1433
1434 /**
1435    Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
1436    stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
1437    PCI controllers before enumeration.
1438
1439    This function is called during the PCI enumeration process. No specific action is expected from this
1440    member function. It allows the host bridge driver to preinitialize individual PCI controllers before
1441    enumeration.
1442
1443    @param This              Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1444    @param RootBridgeHandle  The associated PCI root bridge handle. Type EFI_HANDLE is defined in
1445                             InstallProtocolInterface() in the UEFI 2.0 Specification.
1446    @param PciAddress        The address of the PCI device on the PCI bus. This address can be passed to the
1447                             EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI
1448                             configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for
1449                             the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
1450    @param Phase             The phase of the PCI device enumeration.
1451
1452    @retval EFI_SUCCESS              The requested parameters were returned.
1453    @retval EFI_INVALID_PARAMETER    RootBridgeHandle is not a valid root bridge handle.
1454    @retval EFI_INVALID_PARAMETER    Phase is not a valid phase that is defined in
1455                                     EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
1456    @retval EFI_DEVICE_ERROR         Programming failed due to a hardware error. The PCI enumerator should
1457                                     not enumerate this device, including its child devices if it is a PCI-to-PCI
1458                                     bridge.
1459
1460 **/
1461 EFI_STATUS
1462 EFIAPI
1463 PreprocessController (
1464   IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL          *This,
1465   IN  EFI_HANDLE                                                RootBridgeHandle,
1466   IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS               PciAddress,
1467   IN  EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE              Phase
1468   )
1469 {
1470   PCI_HOST_BRIDGE_INSTANCE              *HostBridgeInstance;
1471   PCI_ROOT_BRIDGE_INSTANCE              *RootBridgeInstance;
1472   LIST_ENTRY                            *List;
1473
1474   HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
1475   List = HostBridgeInstance->Head.ForwardLink;
1476
1477   //
1478   // Enumerate the root bridges in this host bridge
1479   //
1480   while (List != &HostBridgeInstance->Head) {
1481     RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
1482     if (RootBridgeHandle == RootBridgeInstance->Handle) {
1483       break;
1484     }
1485     List = List->ForwardLink;
1486   }
1487   if (List == &HostBridgeInstance->Head) {
1488     return EFI_INVALID_PARAMETER;
1489   }
1490
1491   if ((UINT32)Phase > EfiPciBeforeResourceCollection) {
1492     return EFI_INVALID_PARAMETER;
1493   }
1494
1495   return EFI_SUCCESS;
1496 }