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ArmVirtPkg/FdtPciHostBridgeLib: add MMIO64 support
[mirror_edk2.git] / ArmVirtPkg / PciHostBridgeDxe / PciHostBridge.c
1 /** @file
2 Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation
3
4 Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are
6 licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15 #include "PciHostBridge.h"
16
17 //
18 // Hard code: Root Bridge Number within the host bridge
19 // Root Bridge's attribute
20 // Root Bridge's device path
21 // Root Bridge's resource aperture
22 //
23 UINTN RootBridgeNumber[1] = { 1 };
24
25 UINT64 RootBridgeAttribute[1][1] = { { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM } };
26
27 EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {
28 {
29 {
30 {
31 {
32 ACPI_DEVICE_PATH,
33 ACPI_DP,
34 {
35 (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
36 (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
37 }
38 },
39 EISA_PNP_ID(0x0A03),
40 0
41 },
42
43 {
44 END_DEVICE_PATH_TYPE,
45 END_ENTIRE_DEVICE_PATH_SUBTYPE,
46 {
47 END_DEVICE_PATH_LENGTH,
48 0
49 }
50 }
51 }
52 }
53 };
54
55 STATIC PCI_ROOT_BRIDGE_RESOURCE_APERTURE mResAperture[1][1];
56
57 EFI_HANDLE mDriverImageHandle;
58
59 PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {
60 PCI_HOST_BRIDGE_SIGNATURE, // Signature
61 NULL, // HostBridgeHandle
62 0, // RootBridgeNumber
63 {NULL, NULL}, // Head
64 FALSE, // ResourceSubiteed
65 TRUE, // CanRestarted
66 {
67 NotifyPhase,
68 GetNextRootBridge,
69 GetAttributes,
70 StartBusEnumeration,
71 SetBusNumbers,
72 SubmitResources,
73 GetProposedResources,
74 PreprocessController
75 }
76 };
77
78 //
79 // Implementation
80 //
81
82 //
83 // We expect the "ranges" property of "pci-host-ecam-generic" to consist of
84 // records like this.
85 //
86 #pragma pack (1)
87 typedef struct {
88 UINT32 Type;
89 UINT64 ChildBase;
90 UINT64 CpuBase;
91 UINT64 Size;
92 } DTB_PCI_HOST_RANGE_RECORD;
93 #pragma pack ()
94
95 #define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31
96 #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
97 #define DTB_PCI_HOST_RANGE_ALIASED BIT29
98 #define DTB_PCI_HOST_RANGE_MMIO32 BIT25
99 #define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24)
100 #define DTB_PCI_HOST_RANGE_IO BIT24
101 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
102
103 STATIC
104 EFI_STATUS
105 ProcessPciHost (
106 OUT UINT64 *IoBase,
107 OUT UINT64 *IoSize,
108 OUT UINT64 *IoTranslation,
109 OUT UINT64 *MmioBase,
110 OUT UINT64 *MmioSize,
111 OUT UINT64 *MmioTranslation,
112 OUT UINT32 *BusMin,
113 OUT UINT32 *BusMax
114 )
115 {
116 FDT_CLIENT_PROTOCOL *FdtClient;
117 INT32 Node;
118 UINT64 ConfigBase, ConfigSize;
119 CONST VOID *Prop;
120 UINT32 Len;
121 UINT32 RecordIdx;
122 EFI_STATUS Status;
123
124 //
125 // The following output arguments are initialized only in
126 // order to suppress '-Werror=maybe-uninitialized' warnings
127 // *incorrectly* emitted by some gcc versions.
128 //
129 *IoBase = 0;
130 *IoTranslation = 0;
131 *MmioBase = 0;
132 *MmioTranslation = 0;
133 *BusMin = 0;
134 *BusMax = 0;
135
136 //
137 // *IoSize and *MmioSize are initialized to zero because the logic below
138 // requires it. However, since they are also affected by the issue reported
139 // above, they are initialized early.
140 //
141 *IoSize = 0;
142 *MmioSize = 0;
143
144 Status = gBS->LocateProtocol (&gFdtClientProtocolGuid, NULL,
145 (VOID **)&FdtClient);
146 ASSERT_EFI_ERROR (Status);
147
148 Status = FdtClient->FindCompatibleNode (FdtClient, "pci-host-ecam-generic",
149 &Node);
150 if (EFI_ERROR (Status)) {
151 DEBUG ((EFI_D_INFO,
152 "%a: No 'pci-host-ecam-generic' compatible DT node found\n",
153 __FUNCTION__));
154 return EFI_NOT_FOUND;
155 }
156
157 DEBUG_CODE (
158 INT32 Tmp;
159
160 //
161 // A DT can legally describe multiple PCI host bridges, but we are not
162 // equipped to deal with that. So assert that there is only one.
163 //
164 Status = FdtClient->FindNextCompatibleNode (FdtClient,
165 "pci-host-ecam-generic", Node, &Tmp);
166 ASSERT (Status == EFI_NOT_FOUND);
167 );
168
169 Status = FdtClient->GetNodeProperty (FdtClient, Node, "reg", &Prop, &Len);
170 if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT64)) {
171 DEBUG ((EFI_D_ERROR, "%a: 'reg' property not found or invalid\n",
172 __FUNCTION__));
173 return EFI_PROTOCOL_ERROR;
174 }
175
176 //
177 // Fetch the ECAM window.
178 //
179 ConfigBase = SwapBytes64 (((CONST UINT64 *)Prop)[0]);
180 ConfigSize = SwapBytes64 (((CONST UINT64 *)Prop)[1]);
181
182 //
183 // Fetch the bus range (note: inclusive).
184 //
185 Status = FdtClient->GetNodeProperty (FdtClient, Node, "bus-range", &Prop,
186 &Len);
187 if (EFI_ERROR (Status) || Len != 2 * sizeof (UINT32)) {
188 DEBUG ((EFI_D_ERROR, "%a: 'bus-range' not found or invalid\n",
189 __FUNCTION__));
190 return EFI_PROTOCOL_ERROR;
191 }
192 *BusMin = SwapBytes32 (((CONST UINT32 *)Prop)[0]);
193 *BusMax = SwapBytes32 (((CONST UINT32 *)Prop)[1]);
194
195 //
196 // Sanity check: the config space must accommodate all 4K register bytes of
197 // all 8 functions of all 32 devices of all buses.
198 //
199 if (*BusMax < *BusMin || *BusMax - *BusMin == MAX_UINT32 ||
200 DivU64x32 (ConfigSize, SIZE_4KB * 8 * 32) < *BusMax - *BusMin + 1) {
201 DEBUG ((EFI_D_ERROR, "%a: invalid 'bus-range' and/or 'reg'\n",
202 __FUNCTION__));
203 return EFI_PROTOCOL_ERROR;
204 }
205
206 //
207 // Iterate over "ranges".
208 //
209 Status = FdtClient->GetNodeProperty (FdtClient, Node, "ranges", &Prop, &Len);
210 if (EFI_ERROR (Status) || Len == 0 ||
211 Len % sizeof (DTB_PCI_HOST_RANGE_RECORD) != 0) {
212 DEBUG ((EFI_D_ERROR, "%a: 'ranges' not found or invalid\n", __FUNCTION__));
213 return EFI_PROTOCOL_ERROR;
214 }
215
216 for (RecordIdx = 0; RecordIdx < Len / sizeof (DTB_PCI_HOST_RANGE_RECORD);
217 ++RecordIdx) {
218 CONST DTB_PCI_HOST_RANGE_RECORD *Record;
219
220 Record = (CONST DTB_PCI_HOST_RANGE_RECORD *)Prop + RecordIdx;
221 switch (SwapBytes32 (Record->Type) & DTB_PCI_HOST_RANGE_TYPEMASK) {
222 case DTB_PCI_HOST_RANGE_IO:
223 *IoBase = SwapBytes64 (Record->ChildBase);
224 *IoSize = SwapBytes64 (Record->Size);
225 *IoTranslation = SwapBytes64 (Record->CpuBase) - *IoBase;
226 break;
227
228 case DTB_PCI_HOST_RANGE_MMIO32:
229 *MmioBase = SwapBytes64 (Record->ChildBase);
230 *MmioSize = SwapBytes64 (Record->Size);
231 *MmioTranslation = SwapBytes64 (Record->CpuBase) - *MmioBase;
232
233 if (*MmioBase > MAX_UINT32 || *MmioSize > MAX_UINT32 ||
234 *MmioBase + *MmioSize > SIZE_4GB) {
235 DEBUG ((EFI_D_ERROR, "%a: MMIO32 space invalid\n", __FUNCTION__));
236 return EFI_PROTOCOL_ERROR;
237 }
238
239 if (*MmioTranslation != 0) {
240 DEBUG ((EFI_D_ERROR, "%a: unsupported nonzero MMIO32 translation "
241 "0x%Lx\n", __FUNCTION__, *MmioTranslation));
242 return EFI_UNSUPPORTED;
243 }
244
245 break;
246 }
247 }
248 if (*IoSize == 0 || *MmioSize == 0) {
249 DEBUG ((EFI_D_ERROR, "%a: %a space empty\n", __FUNCTION__,
250 (*IoSize == 0) ? "IO" : "MMIO32"));
251 return EFI_PROTOCOL_ERROR;
252 }
253
254 //
255 // The dynamic PCD PcdPciExpressBaseAddress should have already been set,
256 // and should match the value we found in the DT node.
257 //
258 ASSERT (PcdGet64 (PcdPciExpressBaseAddress) == ConfigBase);
259
260 DEBUG ((EFI_D_INFO, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "
261 "Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x%Lx\n", __FUNCTION__, ConfigBase,
262 ConfigSize, *BusMin, *BusMax, *IoBase, *IoSize, *IoTranslation, *MmioBase,
263 *MmioSize, *MmioTranslation));
264 return EFI_SUCCESS;
265 }
266
267
268 /**
269 Entry point of this driver
270
271 @param ImageHandle Handle of driver image
272 @param SystemTable Point to EFI_SYSTEM_TABLE
273
274 @retval EFI_ABORTED PCI host bridge not present
275 @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource
276 @retval EFI_DEVICE_ERROR Can not install the protocol instance
277 @retval EFI_SUCCESS Success to initialize the Pci host bridge.
278 **/
279 EFI_STATUS
280 EFIAPI
281 InitializePciHostBridge (
282 IN EFI_HANDLE ImageHandle,
283 IN EFI_SYSTEM_TABLE *SystemTable
284 )
285 {
286 UINT64 MmioAttributes;
287 EFI_STATUS Status;
288 UINTN Loop1;
289 UINTN Loop2;
290 PCI_HOST_BRIDGE_INSTANCE *HostBridge;
291 PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
292 UINT64 IoBase, IoSize, IoTranslation;
293 UINT64 MmioBase, MmioSize, MmioTranslation;
294 UINT32 BusMin, BusMax;
295
296 if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {
297 DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));
298 return EFI_ABORTED;
299 }
300
301 Status = ProcessPciHost (&IoBase, &IoSize, &IoTranslation, &MmioBase,
302 &MmioSize, &MmioTranslation, &BusMin, &BusMax);
303 if (EFI_ERROR (Status)) {
304 return Status;
305 }
306
307 mDriverImageHandle = ImageHandle;
308
309 mResAperture[0][0].BusBase = BusMin;
310 mResAperture[0][0].BusLimit = BusMax;
311
312 mResAperture[0][0].MemBase = MmioBase;
313 mResAperture[0][0].MemLimit = MmioBase + MmioSize - 1;
314
315 mResAperture[0][0].IoBase = IoBase;
316 mResAperture[0][0].IoLimit = IoBase + IoSize - 1;
317 mResAperture[0][0].IoTranslation = IoTranslation;
318
319 //
320 // Add IO and MMIO memory space, so that resources can be allocated in the
321 // EfiPciHostBridgeAllocateResources phase.
322 //
323 Status = gDS->AddIoSpace (
324 EfiGcdIoTypeIo,
325 IoBase,
326 IoSize
327 );
328 ASSERT_EFI_ERROR (Status);
329
330 MmioAttributes = EFI_MEMORY_UC;
331
332 Status = gDS->AddMemorySpace (
333 EfiGcdMemoryTypeMemoryMappedIo,
334 MmioBase,
335 MmioSize,
336 MmioAttributes
337 );
338 if (EFI_ERROR (Status)) {
339 DEBUG ((EFI_D_ERROR, "%a: AddMemorySpace: %r\n", __FUNCTION__, Status));
340 return Status;
341 }
342
343 Status = gDS->SetMemorySpaceAttributes (
344 MmioBase,
345 MmioSize,
346 MmioAttributes
347 );
348 if (EFI_ERROR (Status)) {
349 DEBUG ((EFI_D_ERROR, "%a: SetMemorySpaceAttributes: %r\n", __FUNCTION__,
350 Status));
351 return Status;
352 }
353
354 //
355 // Create Host Bridge Device Handle
356 //
357 for (Loop1 = 0; Loop1 < HOST_BRIDGE_NUMBER; Loop1++) {
358 HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE), &mPciHostBridgeInstanceTemplate);
359 if (HostBridge == NULL) {
360 return EFI_OUT_OF_RESOURCES;
361 }
362
363 HostBridge->RootBridgeNumber = RootBridgeNumber[Loop1];
364 InitializeListHead (&HostBridge->Head);
365
366 Status = gBS->InstallMultipleProtocolInterfaces (
367 &HostBridge->HostBridgeHandle,
368 &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,
369 NULL
370 );
371 if (EFI_ERROR (Status)) {
372 FreePool (HostBridge);
373 return EFI_DEVICE_ERROR;
374 }
375
376 //
377 // Create Root Bridge Device Handle in this Host Bridge
378 //
379
380 for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) {
381 PrivateData = AllocateZeroPool (sizeof(PCI_ROOT_BRIDGE_INSTANCE));
382 if (PrivateData == NULL) {
383 return EFI_OUT_OF_RESOURCES;
384 }
385
386 PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
387 PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2];
388
389 RootBridgeConstructor (
390 &PrivateData->Io,
391 HostBridge->HostBridgeHandle,
392 RootBridgeAttribute[Loop1][Loop2],
393 &mResAperture[Loop1][Loop2]
394 );
395
396 Status = gBS->InstallMultipleProtocolInterfaces(
397 &PrivateData->Handle,
398 &gEfiDevicePathProtocolGuid, PrivateData->DevicePath,
399 &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io,
400 NULL
401 );
402 if (EFI_ERROR (Status)) {
403 FreePool(PrivateData);
404 return EFI_DEVICE_ERROR;
405 }
406
407 InsertTailList (&HostBridge->Head, &PrivateData->Link);
408 }
409 }
410
411 return EFI_SUCCESS;
412 }
413
414
415 /**
416 These are the notifications from the PCI bus driver that it is about to enter a certain
417 phase of the PCI enumeration process.
418
419 This member function can be used to notify the host bridge driver to perform specific actions,
420 including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
421 Eight notification points are defined at this time. See belows:
422 EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
423 structures. The PCI enumerator should issue this notification
424 before starting a fresh enumeration process. Enumeration cannot
425 be restarted after sending any other notification such as
426 EfiPciHostBridgeBeginBusAllocation.
427 EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
428 required here. This notification can be used to perform any
429 chipset-specific programming.
430 EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
431 specific action is required here. This notification can be used to
432 perform any chipset-specific programming.
433 EfiPciHostBridgeBeginResourceAllocation
434 The resource allocation phase is about to begin. No specific
435 action is required here. This notification can be used to perform
436 any chipset-specific programming.
437 EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
438 root bridges. These resource settings are returned on the next call to
439 GetProposedResources(). Before calling NotifyPhase() with a Phase of
440 EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
441 for gathering I/O and memory requests for
442 all the PCI root bridges and submitting these requests using
443 SubmitResources(). This function pads the resource amount
444 to suit the root bridge hardware, takes care of dependencies between
445 the PCI root bridges, and calls the Global Coherency Domain (GCD)
446 with the allocation request. In the case of padding, the allocated range
447 could be bigger than what was requested.
448 EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
449 resources (proposed resources) for all the PCI root bridges. After the
450 hardware is programmed, reassigning resources will not be supported.
451 The bus settings are not affected.
452 EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
453 root bridges and resets the I/O and memory apertures to their initial
454 state. The bus settings are not affected. If the request to allocate
455 resources fails, the PCI enumerator can use this notification to
456 deallocate previous resources, adjust the requests, and retry
457 allocation.
458 EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
459 required here. This notification can be used to perform any chipsetspecific
460 programming.
461
462 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
463 @param[in] Phase The phase during enumeration
464
465 @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
466 is valid for a Phase of EfiPciHostBridgeAllocateResources if
467 SubmitResources() has not been called for one or more
468 PCI root bridges before this call
469 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
470 for a Phase of EfiPciHostBridgeSetResources.
471 @retval EFI_INVALID_PARAMETER Invalid phase parameter
472 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
473 This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
474 previously submitted resource requests cannot be fulfilled or
475 were only partially fulfilled.
476 @retval EFI_SUCCESS The notification was accepted without any errors.
477
478 **/
479 EFI_STATUS
480 EFIAPI
481 NotifyPhase(
482 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
483 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
484 )
485 {
486 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
487 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
488 PCI_RESOURCE_TYPE Index;
489 LIST_ENTRY *List;
490 EFI_PHYSICAL_ADDRESS BaseAddress;
491 UINT64 AddrLen;
492 UINTN BitsOfAlignment;
493 EFI_STATUS Status;
494 EFI_STATUS ReturnStatus;
495
496 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
497
498 switch (Phase) {
499
500 case EfiPciHostBridgeBeginEnumeration:
501 if (HostBridgeInstance->CanRestarted) {
502 //
503 // Reset the Each Root Bridge
504 //
505 List = HostBridgeInstance->Head.ForwardLink;
506
507 while (List != &HostBridgeInstance->Head) {
508 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
509 for (Index = TypeIo; Index < TypeMax; Index++) {
510 RootBridgeInstance->ResAllocNode[Index].Type = Index;
511 RootBridgeInstance->ResAllocNode[Index].Base = 0;
512 RootBridgeInstance->ResAllocNode[Index].Length = 0;
513 RootBridgeInstance->ResAllocNode[Index].Status = ResNone;
514 }
515
516 List = List->ForwardLink;
517 }
518
519 HostBridgeInstance->ResourceSubmited = FALSE;
520 HostBridgeInstance->CanRestarted = TRUE;
521 } else {
522 //
523 // Can not restart
524 //
525 return EFI_NOT_READY;
526 }
527 break;
528
529 case EfiPciHostBridgeEndEnumeration:
530 break;
531
532 case EfiPciHostBridgeBeginBusAllocation:
533 //
534 // No specific action is required here, can perform any chipset specific programing
535 //
536 HostBridgeInstance->CanRestarted = FALSE;
537 break;
538
539 case EfiPciHostBridgeEndBusAllocation:
540 //
541 // No specific action is required here, can perform any chipset specific programing
542 //
543 //HostBridgeInstance->CanRestarted = FALSE;
544 break;
545
546 case EfiPciHostBridgeBeginResourceAllocation:
547 //
548 // No specific action is required here, can perform any chipset specific programing
549 //
550 //HostBridgeInstance->CanRestarted = FALSE;
551 break;
552
553 case EfiPciHostBridgeAllocateResources:
554 ReturnStatus = EFI_SUCCESS;
555 if (HostBridgeInstance->ResourceSubmited) {
556 //
557 // Take care of the resource dependencies between the root bridges
558 //
559 List = HostBridgeInstance->Head.ForwardLink;
560
561 while (List != &HostBridgeInstance->Head) {
562 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
563 for (Index = TypeIo; Index < TypeBus; Index++) {
564 if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
565
566 AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
567
568 //
569 // Get the number of '1' in Alignment.
570 //
571 BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);
572
573 switch (Index) {
574
575 case TypeIo:
576 //
577 // It is impossible for this chipset to align 0xFFFF for IO16
578 // So clear it
579 //
580 if (BitsOfAlignment >= 16) {
581 BitsOfAlignment = 0;
582 }
583
584 BaseAddress = mResAperture[0][0].IoLimit;
585 Status = gDS->AllocateIoSpace (
586 EfiGcdAllocateMaxAddressSearchTopDown,
587 EfiGcdIoTypeIo,
588 BitsOfAlignment,
589 AddrLen,
590 &BaseAddress,
591 mDriverImageHandle,
592 NULL
593 );
594
595 if (!EFI_ERROR (Status)) {
596 RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;
597 RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;
598 } else {
599 ReturnStatus = Status;
600 if (Status != EFI_OUT_OF_RESOURCES) {
601 RootBridgeInstance->ResAllocNode[Index].Length = 0;
602 }
603 }
604
605 break;
606
607
608 case TypeMem32:
609 //
610 // It is impossible for this chipset to align 0xFFFFFFFF for Mem32
611 // So clear it
612 //
613
614 if (BitsOfAlignment >= 32) {
615 BitsOfAlignment = 0;
616 }
617
618 BaseAddress = mResAperture[0][0].MemLimit;
619 Status = gDS->AllocateMemorySpace (
620 EfiGcdAllocateMaxAddressSearchTopDown,
621 EfiGcdMemoryTypeMemoryMappedIo,
622 BitsOfAlignment,
623 AddrLen,
624 &BaseAddress,
625 mDriverImageHandle,
626 NULL
627 );
628
629 if (!EFI_ERROR (Status)) {
630 // We were able to allocate the PCI memory
631 RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;
632 RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;
633
634 } else {
635 // Not able to allocate enough PCI memory
636 ReturnStatus = Status;
637
638 if (Status != EFI_OUT_OF_RESOURCES) {
639 RootBridgeInstance->ResAllocNode[Index].Length = 0;
640 }
641 ASSERT (FALSE);
642 }
643 break;
644
645 case TypePMem32:
646 case TypeMem64:
647 case TypePMem64:
648 ReturnStatus = EFI_ABORTED;
649 break;
650 default:
651 ASSERT (FALSE);
652 break;
653 }; //end switch
654 }
655 }
656
657 List = List->ForwardLink;
658 }
659
660 return ReturnStatus;
661 } else {
662 return EFI_NOT_READY;
663 }
664
665 case EfiPciHostBridgeSetResources:
666 break;
667
668 case EfiPciHostBridgeFreeResources:
669 ReturnStatus = EFI_SUCCESS;
670 List = HostBridgeInstance->Head.ForwardLink;
671 while (List != &HostBridgeInstance->Head) {
672 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
673 for (Index = TypeIo; Index < TypeBus; Index++) {
674 if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {
675 AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
676 BaseAddress = RootBridgeInstance->ResAllocNode[Index].Base;
677 switch (Index) {
678
679 case TypeIo:
680 Status = gDS->FreeIoSpace (BaseAddress, AddrLen);
681 if (EFI_ERROR (Status)) {
682 ReturnStatus = Status;
683 }
684 break;
685
686 case TypeMem32:
687 Status = gDS->FreeMemorySpace (BaseAddress, AddrLen);
688 if (EFI_ERROR (Status)) {
689 ReturnStatus = Status;
690 }
691 break;
692
693 case TypePMem32:
694 break;
695
696 case TypeMem64:
697 break;
698
699 case TypePMem64:
700 break;
701
702 default:
703 ASSERT (FALSE);
704 break;
705
706 }; //end switch
707 RootBridgeInstance->ResAllocNode[Index].Type = Index;
708 RootBridgeInstance->ResAllocNode[Index].Base = 0;
709 RootBridgeInstance->ResAllocNode[Index].Length = 0;
710 RootBridgeInstance->ResAllocNode[Index].Status = ResNone;
711 }
712 }
713
714 List = List->ForwardLink;
715 }
716
717 HostBridgeInstance->ResourceSubmited = FALSE;
718 HostBridgeInstance->CanRestarted = TRUE;
719 return ReturnStatus;
720
721 case EfiPciHostBridgeEndResourceAllocation:
722 HostBridgeInstance->CanRestarted = FALSE;
723 break;
724
725 default:
726 return EFI_INVALID_PARAMETER;
727 }
728
729 return EFI_SUCCESS;
730 }
731
732 /**
733 Return the device handle of the next PCI root bridge that is associated with this Host Bridge.
734
735 This function is called multiple times to retrieve the device handles of all the PCI root bridges that
736 are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI
737 root bridges. On each call, the handle that was returned by the previous call is passed into the
738 interface, and on output the interface returns the device handle of the next PCI root bridge. The
739 caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
740 for that root bridge. When there are no more PCI root bridges to report, the interface returns
741 EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they
742 are returned by this function.
743 For D945 implementation, there is only one root bridge in PCI host bridge.
744
745 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
746 @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.
747
748 @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the
749 specific Host bridge and return EFI_SUCCESS.
750 @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.
751 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was
752 returned on a previous call to GetNextRootBridge().
753 **/
754 EFI_STATUS
755 EFIAPI
756 GetNextRootBridge(
757 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
758 IN OUT EFI_HANDLE *RootBridgeHandle
759 )
760 {
761 BOOLEAN NoRootBridge;
762 LIST_ENTRY *List;
763 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
764 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
765
766 NoRootBridge = TRUE;
767 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
768 List = HostBridgeInstance->Head.ForwardLink;
769
770
771 while (List != &HostBridgeInstance->Head) {
772 NoRootBridge = FALSE;
773 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
774 if (*RootBridgeHandle == NULL) {
775 //
776 // Return the first Root Bridge Handle of the Host Bridge
777 //
778 *RootBridgeHandle = RootBridgeInstance->Handle;
779 return EFI_SUCCESS;
780 } else {
781 if (*RootBridgeHandle == RootBridgeInstance->Handle) {
782 //
783 // Get next if have
784 //
785 List = List->ForwardLink;
786 if (List!=&HostBridgeInstance->Head) {
787 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
788 *RootBridgeHandle = RootBridgeInstance->Handle;
789 return EFI_SUCCESS;
790 } else {
791 return EFI_NOT_FOUND;
792 }
793 }
794 }
795
796 List = List->ForwardLink;
797 } //end while
798
799 if (NoRootBridge) {
800 return EFI_NOT_FOUND;
801 } else {
802 return EFI_INVALID_PARAMETER;
803 }
804 }
805
806 /**
807 Returns the allocation attributes of a PCI root bridge.
808
809 The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary
810 from one PCI root bridge to another. These attributes are different from the decode-related
811 attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
812 RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device
813 handles of all the root bridges that are associated with this host bridge must be obtained by calling
814 GetNextRootBridge(). The attributes are static in the sense that they do not change during or
815 after the enumeration process. The hardware may provide mechanisms to change the attributes on
816 the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is
817 installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
818 "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.
819 For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to
820 include requests for the prefetchable memory in the nonprefetchable memory pool and not request any
821 prefetchable memory.
822 Attribute Description
823 ------------------------------------ ----------------------------------------------------------------------
824 EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate
825 windows for nonprefetchable and prefetchable memory. A PCI bus
826 driver needs to include requests for prefetchable memory in the
827 nonprefetchable memory pool.
828
829 EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory
830 windows. If this bit is not set, the PCI bus driver needs to include
831 requests for a 64-bit memory address in the corresponding 32-bit
832 memory pool.
833
834 @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
835 @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type
836 EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
837 @param[out] Attributes The pointer to attribte of root bridge, it is output parameter
838
839 @retval EFI_INVALID_PARAMETER Attribute pointer is NULL
840 @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.
841 @retval EFI_SUCCESS Success to get attribute of interested root bridge.
842
843 **/
844 EFI_STATUS
845 EFIAPI
846 GetAttributes(
847 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
848 IN EFI_HANDLE RootBridgeHandle,
849 OUT UINT64 *Attributes
850 )
851 {
852 LIST_ENTRY *List;
853 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
854 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
855
856 if (Attributes == NULL) {
857 return EFI_INVALID_PARAMETER;
858 }
859
860 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
861 List = HostBridgeInstance->Head.ForwardLink;
862
863 while (List != &HostBridgeInstance->Head) {
864 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
865 if (RootBridgeHandle == RootBridgeInstance->Handle) {
866 *Attributes = RootBridgeInstance->RootBridgeAttrib;
867 return EFI_SUCCESS;
868 }
869 List = List->ForwardLink;
870 }
871
872 //
873 // RootBridgeHandle is not an EFI_HANDLE
874 // that was returned on a previous call to GetNextRootBridge()
875 //
876 return EFI_INVALID_PARAMETER;
877 }
878
879 /**
880 Sets up the specified PCI root bridge for the bus enumeration process.
881
882 This member function sets up the root bridge for bus enumeration and returns the PCI bus range
883 over which the search should be performed in ACPI 2.0 resource descriptor format.
884
885 @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
886 @param[in] RootBridgeHandle The PCI Root Bridge to be set up.
887 @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.
888
889 @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
890 @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.
891 @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.
892
893 **/
894 EFI_STATUS
895 EFIAPI
896 StartBusEnumeration(
897 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
898 IN EFI_HANDLE RootBridgeHandle,
899 OUT VOID **Configuration
900 )
901 {
902 LIST_ENTRY *List;
903 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
904 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
905 VOID *Buffer;
906 UINT8 *Temp;
907 UINT64 BusStart;
908 UINT64 BusEnd;
909
910 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
911 List = HostBridgeInstance->Head.ForwardLink;
912
913 while (List != &HostBridgeInstance->Head) {
914 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
915 if (RootBridgeHandle == RootBridgeInstance->Handle) {
916 //
917 // Set up the Root Bridge for Bus Enumeration
918 //
919 BusStart = RootBridgeInstance->BusBase;
920 BusEnd = RootBridgeInstance->BusLimit;
921 //
922 // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR
923 //
924
925 Buffer = AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
926 if (Buffer == NULL) {
927 return EFI_OUT_OF_RESOURCES;
928 }
929
930 Temp = (UINT8 *)Buffer;
931
932 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = 0x8A;
933 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len = 0x2B;
934 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = 2;
935 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0;
936 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = 0;
937 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = 0;
938 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;
939 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;
940 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;
941 ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = BusEnd - BusStart + 1;
942
943 Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
944 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
945 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
946
947 *Configuration = Buffer;
948 return EFI_SUCCESS;
949 }
950 List = List->ForwardLink;
951 }
952
953 return EFI_INVALID_PARAMETER;
954 }
955
956 /**
957 Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
958
959 This member function programs the specified PCI root bridge to decode the bus range that is
960 specified by the input parameter Configuration.
961 The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.
962
963 @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
964 @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed
965 @param[in] Configuration The pointer to the PCI bus resource descriptor
966
967 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
968 @retval EFI_INVALID_PARAMETER Configuration is NULL.
969 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
970 @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.
971 @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than
972 bus descriptors.
973 @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.
974 @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.
975 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.
976 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
977 @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.
978
979 **/
980 EFI_STATUS
981 EFIAPI
982 SetBusNumbers(
983 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
984 IN EFI_HANDLE RootBridgeHandle,
985 IN VOID *Configuration
986 )
987 {
988 LIST_ENTRY *List;
989 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
990 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
991 UINT8 *Ptr;
992 UINTN BusStart;
993 UINTN BusEnd;
994 UINTN BusLen;
995
996 if (Configuration == NULL) {
997 return EFI_INVALID_PARAMETER;
998 }
999
1000 Ptr = Configuration;
1001
1002 //
1003 // Check the Configuration is valid
1004 //
1005 if(*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {
1006 return EFI_INVALID_PARAMETER;
1007 }
1008
1009 if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != 2) {
1010 return EFI_INVALID_PARAMETER;
1011 }
1012
1013 Ptr += sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
1014 if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {
1015 return EFI_INVALID_PARAMETER;
1016 }
1017
1018 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
1019 List = HostBridgeInstance->Head.ForwardLink;
1020
1021 Ptr = Configuration;
1022
1023 while (List != &HostBridgeInstance->Head) {
1024 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
1025 if (RootBridgeHandle == RootBridgeInstance->Handle) {
1026 BusStart = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin;
1027 BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen;
1028 BusEnd = BusStart + BusLen - 1;
1029
1030 if (BusStart > BusEnd) {
1031 return EFI_INVALID_PARAMETER;
1032 }
1033
1034 if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) {
1035 return EFI_INVALID_PARAMETER;
1036 }
1037
1038 //
1039 // Update the Bus Range
1040 //
1041 RootBridgeInstance->ResAllocNode[TypeBus].Base = BusStart;
1042 RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen;
1043 RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated;
1044
1045 //
1046 // Program the Root Bridge Hardware
1047 //
1048
1049 return EFI_SUCCESS;
1050 }
1051
1052 List = List->ForwardLink;
1053 }
1054
1055 return EFI_INVALID_PARAMETER;
1056 }
1057
1058
1059 /**
1060 Submits the I/O and memory resource requirements for the specified PCI root bridge.
1061
1062 This function is used to submit all the I/O and memory resources that are required by the specified
1063 PCI root bridge. The input parameter Configuration is used to specify the following:
1064 - The various types of resources that are required
1065 - The associated lengths in terms of ACPI 2.0 resource descriptor format
1066
1067 @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1068 @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.
1069 @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.
1070
1071 @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.
1072 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
1073 @retval EFI_INVALID_PARAMETER Configuration is NULL.
1074 @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
1075 @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are
1076 not supported by this PCI root bridge. This error will happen if the caller
1077 did not combine resources according to Attributes that were returned by
1078 GetAllocAttributes().
1079 @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.
1080 @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.
1081 @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.
1082
1083 **/
1084 EFI_STATUS
1085 EFIAPI
1086 SubmitResources(
1087 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
1088 IN EFI_HANDLE RootBridgeHandle,
1089 IN VOID *Configuration
1090 )
1091 {
1092 LIST_ENTRY *List;
1093 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
1094 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
1095 UINT8 *Temp;
1096 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
1097 UINT64 AddrLen;
1098 UINT64 Alignment;
1099
1100 //
1101 // Check the input parameter: Configuration
1102 //
1103 if (Configuration == NULL) {
1104 return EFI_INVALID_PARAMETER;
1105 }
1106
1107 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
1108 List = HostBridgeInstance->Head.ForwardLink;
1109
1110 Temp = (UINT8 *)Configuration;
1111 while ( *Temp == 0x8A) {
1112 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;
1113 }
1114 if (*Temp != 0x79) {
1115 return EFI_INVALID_PARAMETER;
1116 }
1117
1118 Temp = (UINT8 *)Configuration;
1119 while (List != &HostBridgeInstance->Head) {
1120 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
1121 if (RootBridgeHandle == RootBridgeInstance->Handle) {
1122 for (;
1123 *Temp == 0x8A;
1124 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR)
1125 ) {
1126 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
1127
1128 //
1129 // Check Address Length
1130 //
1131 if (Ptr->AddrLen == 0) {
1132 HostBridgeInstance->ResourceSubmited = TRUE;
1133 continue;
1134 }
1135 if (Ptr->AddrLen > 0xffffffff) {
1136 return EFI_INVALID_PARAMETER;
1137 }
1138
1139 //
1140 // Check address range alignment
1141 //
1142 if (Ptr->AddrRangeMax >= 0xffffffff || Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {
1143 return EFI_INVALID_PARAMETER;
1144 }
1145
1146 switch (Ptr->ResType) {
1147
1148 case 0:
1149
1150 //
1151 // Check invalid Address Sapce Granularity
1152 //
1153 if (Ptr->AddrSpaceGranularity != 32) {
1154 return EFI_INVALID_PARAMETER;
1155 }
1156
1157 //
1158 // check the memory resource request is supported by PCI root bridge
1159 //
1160 if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&
1161 Ptr->SpecificFlag == 0x06) {
1162 return EFI_INVALID_PARAMETER;
1163 }
1164
1165 AddrLen = Ptr->AddrLen;
1166 Alignment = Ptr->AddrRangeMax;
1167 if (Ptr->AddrSpaceGranularity == 32) {
1168 if (Ptr->SpecificFlag == 0x06) {
1169 //
1170 // Apply from GCD
1171 //
1172 RootBridgeInstance->ResAllocNode[TypePMem32].Status = ResSubmitted;
1173 } else {
1174 RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen;
1175 RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = Alignment;
1176 RootBridgeInstance->ResAllocNode[TypeMem32].Status = ResRequested;
1177 HostBridgeInstance->ResourceSubmited = TRUE;
1178 }
1179 }
1180
1181 if (Ptr->AddrSpaceGranularity == 64) {
1182 if (Ptr->SpecificFlag == 0x06) {
1183 RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;
1184 } else {
1185 RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;
1186 }
1187 }
1188 break;
1189
1190 case 1:
1191 AddrLen = (UINTN) Ptr->AddrLen;
1192 Alignment = (UINTN) Ptr->AddrRangeMax;
1193 RootBridgeInstance->ResAllocNode[TypeIo].Length = AddrLen;
1194 RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;
1195 RootBridgeInstance->ResAllocNode[TypeIo].Status = ResRequested;
1196 HostBridgeInstance->ResourceSubmited = TRUE;
1197 break;
1198
1199 default:
1200 break;
1201 };
1202 }
1203
1204 return EFI_SUCCESS;
1205 }
1206
1207 List = List->ForwardLink;
1208 }
1209
1210 return EFI_INVALID_PARAMETER;
1211 }
1212
1213 /**
1214 Returns the proposed resource settings for the specified PCI root bridge.
1215
1216 This member function returns the proposed resource settings for the specified PCI root bridge. The
1217 proposed resource settings are prepared when NotifyPhase() is called with a Phase of
1218 EfiPciHostBridgeAllocateResources. The output parameter Configuration
1219 specifies the following:
1220 - The various types of resources, excluding bus resources, that are allocated
1221 - The associated lengths in terms of ACPI 2.0 resource descriptor format
1222
1223 @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1224 @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
1225 @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.
1226
1227 @retval EFI_SUCCESS The requested parameters were returned.
1228 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
1229 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
1230 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
1231
1232 **/
1233 EFI_STATUS
1234 EFIAPI
1235 GetProposedResources(
1236 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
1237 IN EFI_HANDLE RootBridgeHandle,
1238 OUT VOID **Configuration
1239 )
1240 {
1241 LIST_ENTRY *List;
1242 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
1243 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
1244 UINTN Index;
1245 UINTN Number;
1246 VOID *Buffer;
1247 UINT8 *Temp;
1248 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
1249 UINT64 ResStatus;
1250
1251 Buffer = NULL;
1252 Number = 0;
1253 //
1254 // Get the Host Bridge Instance from the resource allocation protocol
1255 //
1256 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
1257 List = HostBridgeInstance->Head.ForwardLink;
1258
1259 //
1260 // Enumerate the root bridges in this host bridge
1261 //
1262 while (List != &HostBridgeInstance->Head) {
1263 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
1264 if (RootBridgeHandle == RootBridgeInstance->Handle) {
1265 for (Index = 0; Index < TypeBus; Index ++) {
1266 if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
1267 Number ++;
1268 }
1269 }
1270
1271 if (Number == 0) {
1272 EFI_ACPI_END_TAG_DESCRIPTOR *End;
1273
1274 End = AllocateZeroPool (sizeof *End);
1275 if (End == NULL) {
1276 return EFI_OUT_OF_RESOURCES;
1277 }
1278 End->Desc = ACPI_END_TAG_DESCRIPTOR;
1279 *Configuration = End;
1280 return EFI_SUCCESS;
1281 }
1282
1283 Buffer = AllocateZeroPool (Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
1284 if (Buffer == NULL) {
1285 return EFI_OUT_OF_RESOURCES;
1286 }
1287
1288 Temp = Buffer;
1289 for (Index = 0; Index < TypeBus; Index ++) {
1290 if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
1291 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
1292 ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;
1293
1294 switch (Index) {
1295
1296 case TypeIo:
1297 //
1298 // Io
1299 //
1300 Ptr->Desc = 0x8A;
1301 Ptr->Len = 0x2B;
1302 Ptr->ResType = 1;
1303 Ptr->GenFlag = 0;
1304 Ptr->SpecificFlag = 0;
1305 Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
1306 Ptr->AddrRangeMax = 0;
1307 Ptr->AddrTranslationOffset = \
1308 (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
1309 Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
1310 break;
1311
1312 case TypeMem32:
1313 //
1314 // Memory 32
1315 //
1316 Ptr->Desc = 0x8A;
1317 Ptr->Len = 0x2B;
1318 Ptr->ResType = 0;
1319 Ptr->GenFlag = 0;
1320 Ptr->SpecificFlag = 0;
1321 Ptr->AddrSpaceGranularity = 32;
1322 Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;
1323 Ptr->AddrRangeMax = 0;
1324 Ptr->AddrTranslationOffset = \
1325 (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
1326 Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
1327 break;
1328
1329 case TypePMem32:
1330 //
1331 // Prefetch memory 32
1332 //
1333 Ptr->Desc = 0x8A;
1334 Ptr->Len = 0x2B;
1335 Ptr->ResType = 0;
1336 Ptr->GenFlag = 0;
1337 Ptr->SpecificFlag = 6;
1338 Ptr->AddrSpaceGranularity = 32;
1339 Ptr->AddrRangeMin = 0;
1340 Ptr->AddrRangeMax = 0;
1341 Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
1342 Ptr->AddrLen = 0;
1343 break;
1344
1345 case TypeMem64:
1346 //
1347 // Memory 64
1348 //
1349 Ptr->Desc = 0x8A;
1350 Ptr->Len = 0x2B;
1351 Ptr->ResType = 0;
1352 Ptr->GenFlag = 0;
1353 Ptr->SpecificFlag = 0;
1354 Ptr->AddrSpaceGranularity = 64;
1355 Ptr->AddrRangeMin = 0;
1356 Ptr->AddrRangeMax = 0;
1357 Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
1358 Ptr->AddrLen = 0;
1359 break;
1360
1361 case TypePMem64:
1362 //
1363 // Prefetch memory 64
1364 //
1365 Ptr->Desc = 0x8A;
1366 Ptr->Len = 0x2B;
1367 Ptr->ResType = 0;
1368 Ptr->GenFlag = 0;
1369 Ptr->SpecificFlag = 6;
1370 Ptr->AddrSpaceGranularity = 64;
1371 Ptr->AddrRangeMin = 0;
1372 Ptr->AddrRangeMax = 0;
1373 Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;
1374 Ptr->AddrLen = 0;
1375 break;
1376 };
1377
1378 Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
1379 }
1380 }
1381
1382 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
1383 ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
1384
1385 *Configuration = Buffer;
1386
1387 return EFI_SUCCESS;
1388 }
1389
1390 List = List->ForwardLink;
1391 }
1392
1393 return EFI_INVALID_PARAMETER;
1394 }
1395
1396 /**
1397 Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
1398 stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
1399 PCI controllers before enumeration.
1400
1401 This function is called during the PCI enumeration process. No specific action is expected from this
1402 member function. It allows the host bridge driver to preinitialize individual PCI controllers before
1403 enumeration.
1404
1405 @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
1406 @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in
1407 InstallProtocolInterface() in the UEFI 2.0 Specification.
1408 @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the
1409 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI
1410 configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for
1411 the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
1412 @param Phase The phase of the PCI device enumeration.
1413
1414 @retval EFI_SUCCESS The requested parameters were returned.
1415 @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
1416 @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
1417 EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
1418 @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
1419 not enumerate this device, including its child devices if it is a PCI-to-PCI
1420 bridge.
1421
1422 **/
1423 EFI_STATUS
1424 EFIAPI
1425 PreprocessController (
1426 IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
1427 IN EFI_HANDLE RootBridgeHandle,
1428 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
1429 IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
1430 )
1431 {
1432 PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
1433 PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
1434 LIST_ENTRY *List;
1435
1436 HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
1437 List = HostBridgeInstance->Head.ForwardLink;
1438
1439 //
1440 // Enumerate the root bridges in this host bridge
1441 //
1442 while (List != &HostBridgeInstance->Head) {
1443 RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
1444 if (RootBridgeHandle == RootBridgeInstance->Handle) {
1445 break;
1446 }
1447 List = List->ForwardLink;
1448 }
1449 if (List == &HostBridgeInstance->Head) {
1450 return EFI_INVALID_PARAMETER;
1451 }
1452
1453 if ((UINT32)Phase > EfiPciBeforeResourceCollection) {
1454 return EFI_INVALID_PARAMETER;
1455 }
1456
1457 return EFI_SUCCESS;
1458 }
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