BaseTools/Source/C/Include/IndustryStandard/pci22.h

   1 /** @file
   2   Support for PCI 2.2 standard.
   3
   4   Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   5
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #ifndef _PCI22_H
  11 #define _PCI22_H
  12
  13 #define PCI_MAX_SEGMENT 0
  14
  15 #define PCI_MAX_BUS     255
  16
  17 #define PCI_MAX_DEVICE  31
  18 #define PCI_MAX_FUNC    7
  19
  20 //
  21 // Command
  22 //
  23 #define PCI_VGA_PALETTE_SNOOP_DISABLED  0x20
  24
  25 #pragma pack(push, 1)
  26 typedef struct {
  27   UINT16  VendorId;
  28   UINT16  DeviceId;
  29   UINT16  Command;
  30   UINT16  Status;
  31   UINT8   RevisionID;
  32   UINT8   ClassCode[3];
  33   UINT8   CacheLineSize;
  34   UINT8   LatencyTimer;
  35   UINT8   HeaderType;
  36   UINT8   BIST;
  37 } PCI_DEVICE_INDEPENDENT_REGION;
  38
  39 typedef struct {
  40   UINT32  Bar[6];
  41   UINT32  CISPtr;
  42   UINT16  SubsystemVendorID;
  43   UINT16  SubsystemID;
  44   UINT32  ExpansionRomBar;
  45   UINT8   CapabilityPtr;
  46   UINT8   Reserved1[3];
  47   UINT32  Reserved2;
  48   UINT8   InterruptLine;
  49   UINT8   InterruptPin;
  50   UINT8   MinGnt;
  51   UINT8   MaxLat;
  52 } PCI_DEVICE_HEADER_TYPE_REGION;
  53
  54 typedef struct {
  55   PCI_DEVICE_INDEPENDENT_REGION Hdr;
  56   PCI_DEVICE_HEADER_TYPE_REGION Device;
  57 } PCI_TYPE00;
  58
  59 typedef struct {
  60   UINT32  Bar[2];
  61   UINT8   PrimaryBus;
  62   UINT8   SecondaryBus;
  63   UINT8   SubordinateBus;
  64   UINT8   SecondaryLatencyTimer;
  65   UINT8   IoBase;
  66   UINT8   IoLimit;
  67   UINT16  SecondaryStatus;
  68   UINT16  MemoryBase;
  69   UINT16  MemoryLimit;
  70   UINT16  PrefetchableMemoryBase;
  71   UINT16  PrefetchableMemoryLimit;
  72   UINT32  PrefetchableBaseUpper32;
  73   UINT32  PrefetchableLimitUpper32;
  74   UINT16  IoBaseUpper16;
  75   UINT16  IoLimitUpper16;
  76   UINT8   CapabilityPtr;
  77   UINT8   Reserved[3];
  78   UINT32  ExpansionRomBAR;
  79   UINT8   InterruptLine;
  80   UINT8   InterruptPin;
  81   UINT16  BridgeControl;
  82 } PCI_BRIDGE_CONTROL_REGISTER;
  83
  84 typedef struct {
  85   PCI_DEVICE_INDEPENDENT_REGION Hdr;
  86   PCI_BRIDGE_CONTROL_REGISTER   Bridge;
  87 } PCI_TYPE01;
  88
  89 typedef union {
  90   PCI_TYPE00  Device;
  91   PCI_TYPE01  Bridge;
  92 } PCI_TYPE_GENERIC;
  93
  94 typedef struct {
  95   UINT32  CardBusSocketReg; // Cardbus Socket/ExCA Base
  96   // Address Register
  97   //
  98   UINT16  Reserved;
  99   UINT16  SecondaryStatus;      // Secondary Status
 100   UINT8   PciBusNumber;         // PCI Bus Number
 101   UINT8   CardBusBusNumber;     // CardBus Bus Number
 102   UINT8   SubordinateBusNumber; // Subordinate Bus Number
 103   UINT8   CardBusLatencyTimer;  // CardBus Latency Timer
 104   UINT32  MemoryBase0;          // Memory Base Register 0
 105   UINT32  MemoryLimit0;         // Memory Limit Register 0
 106   UINT32  MemoryBase1;
 107   UINT32  MemoryLimit1;
 108   UINT32  IoBase0;
 109   UINT32  IoLimit0;             // I/O Base Register 0
 110   UINT32  IoBase1;              // I/O Limit Register 0
 111   UINT32  IoLimit1;
 112   UINT8   InterruptLine;        // Interrupt Line
 113   UINT8   InterruptPin;         // Interrupt Pin
 114   UINT16  BridgeControl;        // Bridge Control
 115 } PCI_CARDBUS_CONTROL_REGISTER;
 116
 117 //
 118 // Definitions of PCI class bytes and manipulation macros.
 119 //
 120 #define PCI_CLASS_OLD                 0x00
 121 #define PCI_CLASS_OLD_OTHER           0x00
 122 #define PCI_CLASS_OLD_VGA             0x01
 123
 124 #define PCI_CLASS_MASS_STORAGE        0x01
 125 #define PCI_CLASS_MASS_STORAGE_SCSI   0x00
 126 #define PCI_CLASS_MASS_STORAGE_IDE    0x01  // obsolete
 127 #define PCI_CLASS_IDE                 0x01
 128 #define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02
 129 #define PCI_CLASS_MASS_STORAGE_IPI    0x03
 130 #define PCI_CLASS_MASS_STORAGE_RAID   0x04
 131 #define PCI_CLASS_MASS_STORAGE_OTHER  0x80
 132
 133 #define PCI_CLASS_NETWORK             0x02
 134 #define PCI_CLASS_NETWORK_ETHERNET    0x00
 135 #define PCI_CLASS_ETHERNET            0x00  // obsolete
 136 #define PCI_CLASS_NETWORK_TOKENRING   0x01
 137 #define PCI_CLASS_NETWORK_FDDI        0x02
 138 #define PCI_CLASS_NETWORK_ATM         0x03
 139 #define PCI_CLASS_NETWORK_ISDN        0x04
 140 #define PCI_CLASS_NETWORK_OTHER       0x80
 141
 142 #define PCI_CLASS_DISPLAY             0x03
 143 #define PCI_CLASS_DISPLAY_CTRL        0x03  // obsolete
 144 #define PCI_CLASS_DISPLAY_VGA         0x00
 145 #define PCI_CLASS_VGA                 0x00  // obsolete
 146 #define PCI_CLASS_DISPLAY_XGA         0x01
 147 #define PCI_CLASS_DISPLAY_3D          0x02
 148 #define PCI_CLASS_DISPLAY_OTHER       0x80
 149 #define PCI_CLASS_DISPLAY_GFX         0x80
 150 #define PCI_CLASS_GFX                 0x80  // obsolete
 151 #define PCI_CLASS_BRIDGE              0x06
 152 #define PCI_CLASS_BRIDGE_HOST         0x00
 153 #define PCI_CLASS_BRIDGE_ISA          0x01
 154 #define PCI_CLASS_ISA                 0x01  // obsolete
 155 #define PCI_CLASS_BRIDGE_EISA         0x02
 156 #define PCI_CLASS_BRIDGE_MCA          0x03
 157 #define PCI_CLASS_BRIDGE_P2P          0x04
 158 #define PCI_CLASS_BRIDGE_PCMCIA       0x05
 159 #define PCI_CLASS_BRIDGE_NUBUS        0x06
 160 #define PCI_CLASS_BRIDGE_CARDBUS      0x07
 161 #define PCI_CLASS_BRIDGE_RACEWAY      0x08
 162 #define PCI_CLASS_BRIDGE_ISA_PDECODE  0x80
 163 #define PCI_CLASS_ISA_POSITIVE_DECODE 0x80  // obsolete
 164
 165 #define PCI_CLASS_SCC                 0x07  // Simple communications controllers
 166 #define PCI_SUBCLASS_SERIAL           0x00
 167 #define PCI_IF_GENERIC_XT             0x00
 168 #define PCI_IF_16450                  0x01
 169 #define PCI_IF_16550                  0x02
 170 #define PCI_IF_16650                  0x03
 171 #define PCI_IF_16750                  0x04
 172 #define PCI_IF_16850                  0x05
 173 #define PCI_IF_16950                  0x06
 174 #define PCI_SUBCLASS_PARALLEL         0x01
 175 #define PCI_IF_PARALLEL_PORT          0x00
 176 #define PCI_IF_BI_DIR_PARALLEL_PORT   0x01
 177 #define PCI_IF_ECP_PARALLEL_PORT      0x02
 178 #define PCI_IF_1284_CONTROLLER        0x03
 179 #define PCI_IF_1284_DEVICE            0xFE
 180 #define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02
 181 #define PCI_SUBCLASS_MODEM            0x03
 182 #define PCI_IF_GENERIC_MODEM          0x00
 183 #define PCI_IF_16450_MODEM            0x01
 184 #define PCI_IF_16550_MODEM            0x02
 185 #define PCI_IF_16650_MODEM            0x03
 186 #define PCI_IF_16750_MODEM            0x04
 187 #define PCI_SUBCLASS_OTHER            0x80
 188
 189 #define PCI_CLASS_SYSTEM_PERIPHERAL   0x08
 190 #define PCI_SUBCLASS_PIC              0x00
 191 #define PCI_IF_8259_PIC               0x00
 192 #define PCI_IF_ISA_PIC                0x01
 193 #define PCI_IF_EISA_PIC               0x02
 194 #define PCI_IF_APIC_CONTROLLER        0x10 // I/O APIC interrupt controller , 32 byte none-prefetchable memory.
 195 #define PCI_IF_APIC_CONTROLLER2       0x20
 196 #define PCI_SUBCLASS_TIMER            0x02
 197 #define PCI_IF_8254_TIMER             0x00
 198 #define PCI_IF_ISA_TIMER              0x01
 199 #define PCI_EISA_TIMER                0x02
 200 #define PCI_SUBCLASS_RTC              0x03
 201 #define PCI_IF_GENERIC_RTC            0x00
 202 #define PCI_IF_ISA_RTC                0x00
 203 #define PCI_SUBCLASS_PNP_CONTROLLER   0x04 // HotPlug Controller
 204
 205 #define PCI_CLASS_INPUT_DEVICE        0x09
 206 #define PCI_SUBCLASS_KEYBOARD         0x00
 207 #define PCI_SUBCLASS_PEN              0x01
 208 #define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02
 209 #define PCI_SUBCLASS_SCAN_CONTROLLER  0x03
 210 #define PCI_SUBCLASS_GAMEPORT         0x04
 211
 212 #define PCI_CLASS_DOCKING_STATION     0x0A
 213
 214 #define PCI_CLASS_PROCESSOR           0x0B
 215 #define PCI_SUBCLASS_PROC_386         0x00
 216 #define PCI_SUBCLASS_PROC_486         0x01
 217 #define PCI_SUBCLASS_PROC_PENTIUM     0x02
 218 #define PCI_SUBCLASS_PROC_ALPHA       0x10
 219 #define PCI_SUBCLASS_PROC_POWERPC     0x20
 220 #define PCI_SUBCLASS_PROC_MIPS        0x30
 221 #define PCI_SUBCLASS_PROC_CO_PORC     0x40 // Co-Processor
 222
 223 #define PCI_CLASS_SERIAL              0x0C
 224 #define PCI_CLASS_SERIAL_FIREWIRE     0x00
 225 #define PCI_CLASS_SERIAL_ACCESS_BUS   0x01
 226 #define PCI_CLASS_SERIAL_SSA          0x02
 227 #define PCI_CLASS_SERIAL_USB          0x03
 228 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04
 229 #define PCI_CLASS_SERIAL_SMB          0x05
 230
 231 #define PCI_CLASS_WIRELESS            0x0D
 232 #define PCI_SUBCLASS_IRDA             0x00
 233 #define PCI_SUBCLASS_IR               0x01
 234 #define PCI_SUBCLASS_RF               0x02
 235
 236 #define PCI_CLASS_INTELLIGENT_IO      0x0E
 237
 238 #define PCI_CLASS_SATELLITE           0x0F
 239 #define PCI_SUBCLASS_TV               0x01
 240 #define PCI_SUBCLASS_AUDIO            0x02
 241 #define PCI_SUBCLASS_VOICE            0x03
 242 #define PCI_SUBCLASS_DATA             0x04
 243
 244 #define PCI_SECURITY_CONTROLLER       0x10 // Encryption and decryption controller
 245 #define PCI_SUBCLASS_NET_COMPUT       0x00
 246 #define PCI_SUBCLASS_ENTERTAINMENT    0x10
 247
 248 #define PCI_CLASS_DPIO                0x11
 249
 250 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))
 251 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
 252 #define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
 253
 254 #define IS_PCI_DISPLAY(_p)            IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
 255 #define IS_PCI_VGA(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 0)
 256 #define IS_PCI_8514(_p)               IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, 1)
 257 #define IS_PCI_GFX(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_GFX, 0)
 258 #define IS_PCI_OLD(_p)                IS_CLASS1 (_p, PCI_CLASS_OLD)
 259 #define IS_PCI_OLD_VGA(_p)            IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
 260 #define IS_PCI_IDE(_p)                IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
 261 #define IS_PCI_SCSI(_p)               IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI, 0)
 262 #define IS_PCI_RAID(_p)               IS_CLASS3 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID, 0)
 263 #define IS_PCI_LPC(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA, 0)
 264 #define IS_PCI_P2P(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 0)
 265 #define IS_PCI_P2P_SUB(_p)            IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, 1)
 266 #define IS_PCI_USB(_p)                IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
 267
 268 #define HEADER_TYPE_DEVICE            0x00
 269 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
 270 #define HEADER_TYPE_CARDBUS_BRIDGE    0x02
 271
 272 #define HEADER_TYPE_MULTI_FUNCTION    0x80
 273 #define HEADER_LAYOUT_CODE            0x7f
 274
 275 #define IS_PCI_BRIDGE(_p)             (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
 276 #define IS_CARDBUS_BRIDGE(_p)         (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
 277 #define IS_PCI_MULTI_FUNC(_p)         ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)
 278
 279 #define PCI_DEVICE_ROMBAR             0x30
 280 #define PCI_BRIDGE_ROMBAR             0x38
 281
 282 #define PCI_MAX_BAR                   0x0006
 283 #define PCI_MAX_CONFIG_OFFSET         0x0100
 284
 285 #define PCI_VENDOR_ID_OFFSET                        0x00
 286 #define PCI_DEVICE_ID_OFFSET                        0x02
 287 #define PCI_COMMAND_OFFSET                          0x04
 288 #define PCI_PRIMARY_STATUS_OFFSET                   0x06
 289 #define PCI_REVISION_ID_OFFSET                      0x08
 290 #define PCI_CLASSCODE_OFFSET                        0x09
 291 #define PCI_CACHELINE_SIZE_OFFSET                   0x0C
 292 #define PCI_LATENCY_TIMER_OFFSET                    0x0D
 293 #define PCI_HEADER_TYPE_OFFSET                      0x0E
 294 #define PCI_BIST_OFFSET                             0x0F
 295 #define PCI_BASE_ADDRESSREG_OFFSET                  0x10
 296 #define PCI_CARDBUS_CIS_OFFSET                      0x28
 297 #define PCI_SVID_OFFSET                             0x2C // SubSystem Vendor id
 298 #define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C
 299 #define PCI_SID_OFFSET                              0x2E // SubSystem ID
 300 #define PCI_SUBSYSTEM_ID_OFFSET                     0x2E
 301 #define PCI_EXPANSION_ROM_BASE                      0x30
 302 #define PCI_CAPBILITY_POINTER_OFFSET                0x34
 303 #define PCI_INT_LINE_OFFSET                         0x3C // Interrupt Line Register
 304 #define PCI_INT_PIN_OFFSET                          0x3D // Interrupt Pin Register
 305 #define PCI_MAXGNT_OFFSET                           0x3E // Max Grant Register
 306 #define PCI_MAXLAT_OFFSET                           0x3F // Max Latency Register
 307
 308 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E
 309 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E
 310
 311 #define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18
 312 #define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19
 313 #define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a
 314
 315 typedef union {
 316   struct {
 317     UINT32  Reg : 8;
 318     UINT32  Func : 3;
 319     UINT32  Dev : 5;
 320     UINT32  Bus : 8;
 321     UINT32  Reserved : 7;
 322     UINT32  Enable : 1;
 323   } Bits;
 324   UINT32  Uint32;
 325 } PCI_CONFIG_ACCESS_CF8;
 326
 327 #pragma pack()
 328
 329 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55
 330 #define PCI_DATA_STRUCTURE_SIGNATURE                    SIGNATURE_32 ('P', 'C', 'I', 'R')
 331 #define PCI_CODE_TYPE_PCAT_IMAGE                        0x00
 332 #define PCI_CODE_TYPE_EFI_IMAGE                         0x03
 333 #define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED         0x0001
 334
 335 #define EFI_PCI_COMMAND_IO_SPACE                        0x0001
 336 #define EFI_PCI_COMMAND_MEMORY_SPACE                    0x0002
 337 #define EFI_PCI_COMMAND_BUS_MASTER                      0x0004
 338 #define EFI_PCI_COMMAND_SPECIAL_CYCLE                   0x0008
 339 #define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE     0x0010
 340 #define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP               0x0020
 341 #define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND            0x0040
 342 #define EFI_PCI_COMMAND_STEPPING_CONTROL                0x0080
 343 #define EFI_PCI_COMMAND_SERR                            0x0100
 344 #define EFI_PCI_COMMAND_FAST_BACK_TO_BACK               0x0200
 345
 346 #define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE    0x0001
 347 #define EFI_PCI_BRIDGE_CONTROL_SERR                     0x0002
 348 #define EFI_PCI_BRIDGE_CONTROL_ISA                      0x0004
 349 #define EFI_PCI_BRIDGE_CONTROL_VGA                      0x0008
 350 #define EFI_PCI_BRIDGE_CONTROL_VGA_16                   0x0010
 351 #define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT             0x0020
 352 #define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS      0x0040
 353 #define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK        0x0080
 354 #define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER    0x0100
 355 #define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER  0x0200
 356 #define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS             0x0400
 357 #define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR       0x0800
 358
 359 //
 360 // Following are the PCI-CARDBUS bridge control bit
 361 //
 362 #define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE       0x0080
 363 #define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE   0x0100
 364 #define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE   0x0200
 365 #define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE 0x0400
 366
 367 //
 368 // Following are the PCI status control bit
 369 //
 370 #define EFI_PCI_STATUS_CAPABILITY             0x0010
 371 #define EFI_PCI_STATUS_66MZ_CAPABLE           0x0020
 372 #define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE     0x0080
 373 #define EFI_PCI_MASTER_DATA_PARITY_ERROR      0x0100
 374
 375 #define EFI_PCI_CAPABILITY_PTR                0x34
 376 #define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14
 377
 378 #pragma pack(1)
 379 typedef struct {
 380   UINT16  Signature;    // 0xaa55
 381   UINT8   Reserved[0x16];
 382   UINT16  PcirOffset;
 383 } PCI_EXPANSION_ROM_HEADER;
 384
 385 typedef struct {
 386   UINT16  Signature;    // 0xaa55
 387   UINT8   Size512;
 388   UINT8   InitEntryPoint[3];
 389   UINT8   Reserved[0x12];
 390   UINT16  PcirOffset;
 391 } EFI_LEGACY_EXPANSION_ROM_HEADER;
 392
 393 typedef struct {
 394   UINT32  Signature;    // "PCIR"
 395   UINT16  VendorId;
 396   UINT16  DeviceId;
 397   UINT16  Reserved0;
 398   UINT16  Length;
 399   UINT8   Revision;
 400   UINT8   ClassCode[3];
 401   UINT16  ImageLength;
 402   UINT16  CodeRevision;
 403   UINT8   CodeType;
 404   UINT8   Indicator;
 405   UINT16  Reserved1;
 406 } PCI_DATA_STRUCTURE;
 407
 408 //
 409 // PCI Capability List IDs and records
 410 //
 411 #define EFI_PCI_CAPABILITY_ID_PMI     0x01
 412 #define EFI_PCI_CAPABILITY_ID_AGP     0x02
 413 #define EFI_PCI_CAPABILITY_ID_VPD     0x03
 414 #define EFI_PCI_CAPABILITY_ID_SLOTID  0x04
 415 #define EFI_PCI_CAPABILITY_ID_MSI     0x05
 416 #define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06
 417 #define EFI_PCI_CAPABILITY_ID_PCIX    0x07
 418
 419 typedef struct {
 420   UINT8 CapabilityID;
 421   UINT8 NextItemPtr;
 422 } EFI_PCI_CAPABILITY_HDR;
 423
 424 //
 425 // Capability EFI_PCI_CAPABILITY_ID_PMI
 426 //
 427 typedef struct {
 428   EFI_PCI_CAPABILITY_HDR  Hdr;
 429   UINT16                  PMC;
 430   UINT16                  PMCSR;
 431   UINT8                   BridgeExtention;
 432   UINT8                   Data;
 433 } EFI_PCI_CAPABILITY_PMI;
 434
 435 //
 436 // Capability EFI_PCI_CAPABILITY_ID_AGP
 437 //
 438 typedef struct {
 439   EFI_PCI_CAPABILITY_HDR  Hdr;
 440   UINT8                   Rev;
 441   UINT8                   Reserved;
 442   UINT32                  Status;
 443   UINT32                  Command;
 444 } EFI_PCI_CAPABILITY_AGP;
 445
 446 //
 447 // Capability EFI_PCI_CAPABILITY_ID_VPD
 448 //
 449 typedef struct {
 450   EFI_PCI_CAPABILITY_HDR  Hdr;
 451   UINT16                  AddrReg;
 452   UINT32                  DataReg;
 453 } EFI_PCI_CAPABILITY_VPD;
 454
 455 //
 456 // Capability EFI_PCI_CAPABILITY_ID_SLOTID
 457 //
 458 typedef struct {
 459   EFI_PCI_CAPABILITY_HDR  Hdr;
 460   UINT8                   ExpnsSlotReg;
 461   UINT8                   ChassisNo;
 462 } EFI_PCI_CAPABILITY_SLOTID;
 463
 464 //
 465 // Capability EFI_PCI_CAPABILITY_ID_MSI
 466 //
 467 typedef struct {
 468   EFI_PCI_CAPABILITY_HDR  Hdr;
 469   UINT16                  MsgCtrlReg;
 470   UINT32                  MsgAddrReg;
 471   UINT16                  MsgDataReg;
 472 } EFI_PCI_CAPABILITY_MSI32;
 473
 474 typedef struct {
 475   EFI_PCI_CAPABILITY_HDR  Hdr;
 476   UINT16                  MsgCtrlReg;
 477   UINT32                  MsgAddrRegLsdw;
 478   UINT32                  MsgAddrRegMsdw;
 479   UINT16                  MsgDataReg;
 480 } EFI_PCI_CAPABILITY_MSI64;
 481
 482 //
 483 // Capability EFI_PCI_CAPABILITY_ID_HOTPLUG
 484 //
 485 typedef struct {
 486   EFI_PCI_CAPABILITY_HDR  Hdr;
 487   //
 488   // not finished - fields need to go here
 489   //
 490 } EFI_PCI_CAPABILITY_HOTPLUG;
 491
 492 //
 493 // Capability EFI_PCI_CAPABILITY_ID_PCIX
 494 //
 495 typedef struct {
 496   EFI_PCI_CAPABILITY_HDR  Hdr;
 497   UINT16                  CommandReg;
 498   UINT32                  StatusReg;
 499 } EFI_PCI_CAPABILITY_PCIX;
 500
 501 typedef struct {
 502   EFI_PCI_CAPABILITY_HDR  Hdr;
 503   UINT16                  SecStatusReg;
 504   UINT32                  StatusReg;
 505   UINT32                  SplitTransCtrlRegUp;
 506   UINT32                  SplitTransCtrlRegDn;
 507 } EFI_PCI_CAPABILITY_PCIX_BRDG;
 508
 509 #define DEVICE_ID_NOCARE    0xFFFF
 510
 511 #define PCI_ACPI_UNUSED     0
 512 #define PCI_BAR_NOCHANGE    0
 513 #define PCI_BAR_OLD_ALIGN   0xFFFFFFFFFFFFFFFFULL
 514 #define PCI_BAR_EVEN_ALIGN  0xFFFFFFFFFFFFFFFEULL
 515 #define PCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL
 516 #define PCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL
 517
 518 #define PCI_BAR_IDX0        0x00
 519 #define PCI_BAR_IDX1        0x01
 520 #define PCI_BAR_IDX2        0x02
 521 #define PCI_BAR_IDX3        0x03
 522 #define PCI_BAR_IDX4        0x04
 523 #define PCI_BAR_IDX5        0x05
 524 #define PCI_BAR_ALL         0xFF
 525
 526 #pragma pack(pop)
 527
 528 //
 529 // NOTE: The following header files are included here for
 530 // compatibility consideration.
 531 //
 532 #include "pci23.h"
 533 #include "pci30.h"
 534 #include "EfiPci.h"
 535
 536 #endif