BeagleBoardPkg: drop unused EmbeddedPkg Pcds
[mirror_edk2.git] / BeagleBoardPkg / Library / BeagleBoardLib / BeagleBoardMem.c
1 /** @file
2 *
3 * Copyright (c) 2011, ARM Limited. All rights reserved.
4 *
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
9 *
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14
15 #include <Library/ArmPlatformLib.h>
16 #include <Library/DebugLib.h>
17 #include <Library/PcdLib.h>
18 #include <Library/MemoryAllocationLib.h>
19 #include <Library/IoLib.h>
20
21 #include <BeagleBoard.h>
22
23 #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 4
24
25 /**
26 Return the Virtual Memory Map of your platform
27
28 This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
29
30 @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
31 Virtual Memory mapping. This array must be ended by a zero-filled
32 entry
33
34 **/
35 VOID
36 ArmPlatformGetVirtualMemoryMap (
37 IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
38 )
39 {
40 ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
41 UINTN Index = 0;
42 ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
43
44 ASSERT(VirtualMemoryMap != NULL);
45
46 VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
47 if (VirtualMemoryTable == NULL) {
48 return;
49 }
50
51 CacheAttributes = DDR_ATTRIBUTES_CACHED;
52
53 // ReMap (Either NOR Flash or DRAM)
54 VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);
55 VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);
56 VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);
57 VirtualMemoryTable[Index].Attributes = CacheAttributes;
58
59 // SOC Registers. L3 interconnects
60 VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
61 VirtualMemoryTable[Index].VirtualBase = SOC_REGISTERS_L3_PHYSICAL_BASE;
62 VirtualMemoryTable[Index].Length = SOC_REGISTERS_L3_PHYSICAL_LENGTH;
63 VirtualMemoryTable[Index].Attributes = SOC_REGISTERS_L3_ATTRIBUTES;
64
65 // SOC Registers. L4 interconnects
66 VirtualMemoryTable[++Index].PhysicalBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
67 VirtualMemoryTable[Index].VirtualBase = SOC_REGISTERS_L4_PHYSICAL_BASE;
68 VirtualMemoryTable[Index].Length = SOC_REGISTERS_L4_PHYSICAL_LENGTH;
69 VirtualMemoryTable[Index].Attributes = SOC_REGISTERS_L4_ATTRIBUTES;
70
71 // End of Table
72 VirtualMemoryTable[++Index].PhysicalBase = 0;
73 VirtualMemoryTable[Index].VirtualBase = 0;
74 VirtualMemoryTable[Index].Length = 0;
75 VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
76
77 ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
78
79 *VirtualMemoryMap = VirtualMemoryTable;
80 }