3 Copyright (c) 2005 - 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 The driver for the host to pci bridge (root bridge).
21 #ifndef _PCAT_PCI_ROOT_BRIDGE_H_
22 #define _PCAT_PCI_ROOT_BRIDGE_H_
25 #include <Protocol/PciRootBridgeIo.h>
26 #include <Protocol/DeviceIo.h>
27 #include <Protocol/CpuIo.h>
29 #include <Library/UefiLib.h>
30 #include <Library/BaseLib.h>
31 #include <Library/MemoryAllocationLib.h>
32 #include <Library/UefiBootServicesTableLib.h>
33 #include <Library/DebugLib.h>
34 #include <Library/BaseMemoryLib.h>
35 #include <Library/DevicePathLib.h>
36 #include <Library/HobLib.h>
38 #include <Guid/PciOptionRomTable.h>
39 #include <Guid/HobList.h>
40 #include <Guid/PciExpressBaseAddress.h>
42 #include <IndustryStandard/Acpi.h>
43 #include <IndustryStandard/Pci.h>
45 // Driver Instance Data Prototypes
47 #define PCAT_PCI_ROOT_BRIDGE_SIGNATURE EFI_SIGNATURE_32('p', 'c', 'r', 'b')
53 EFI_DEVICE_PATH_PROTOCOL
*DevicePath
;
54 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io
;
55 EFI_CPU_IO_PROTOCOL
*CpuIo
;
57 UINT32 RootBridgeNumber
;
59 UINT32 SubordinateBus
;
61 UINT64 MemBase
; // Offsets host to bus memory addr.
62 UINT64 MemLimit
; // Max allowable memory access
64 UINT64 IoBase
; // Offsets host to bus io addr.
65 UINT64 IoLimit
; // Max allowable io access
70 UINT64 PhysicalMemoryBase
;
71 UINT64 PhysicalIoBase
;
86 UINT64 PciExpressBaseAddress
;
88 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Configuration
;
91 } PCAT_PCI_ROOT_BRIDGE_INSTANCE
;
94 // Driver Instance Data Macros
96 #define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \
97 CR(a, PCAT_PCI_ROOT_BRIDGE_INSTANCE, Io, PCAT_PCI_ROOT_BRIDGE_SIGNATURE)
99 #define VOLATILE volatile
101 // Private data types
106 UINT16 VOLATILE
*ui16
;
107 UINT32 VOLATILE
*ui32
;
108 UINT64 VOLATILE
*ui64
;
113 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation
;
116 EFI_PHYSICAL_ADDRESS HostAddress
;
117 EFI_PHYSICAL_ADDRESS MappedHostAddress
;
127 (*EFI_PCI_BUS_SCAN_CALLBACK
) (
128 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
142 UINT16
*CommandRegisterBuffer
;
143 UINT32 PpbMemoryWindow
;
144 } PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT
;
155 // Driver Protocol Constructor Prototypes
158 ConstructConfiguration(
159 IN OUT PCAT_PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
163 PcatPciRootBridgeParseBars (
164 IN PCAT_PCI_ROOT_BRIDGE_INSTANCE
*PrivateData
,
172 ScanPciRootBridgeForRoms(
173 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
177 PcatRootBridgeDevicePathConstructor (
178 IN EFI_DEVICE_PATH_PROTOCOL
**Protocol
,
179 IN UINTN RootBridgeNumber
,
180 IN BOOLEAN IsPciExpress
184 PcatRootBridgeIoConstructor (
185 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*Protocol
,
186 IN UINTN SegmentNumber
190 PcatRootBridgeIoGetIoPortMapping (
191 OUT EFI_PHYSICAL_ADDRESS
*IoPortMapping
,
192 OUT EFI_PHYSICAL_ADDRESS
*MemoryPortMapping
196 PcatRootBridgeIoPciRW (
197 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*This
,
199 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
200 IN UINT64 UserAddress
,
202 IN OUT VOID
*UserBuffer
206 GetPciExpressBaseAddressForRootBridge (
207 IN UINTN HostBridgeNumber
,
208 IN UINTN RootBridgeNumber
212 // Driver entry point prototype
216 InitializePcatPciRootBridge (
217 IN EFI_HANDLE ImageHandle
,
218 IN EFI_SYSTEM_TABLE
*SystemTable
221 extern EFI_CPU_IO_PROTOCOL
*gCpuIo
;