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1 /*++
2
3 Copyright (c) 2005 - 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 Module Name:
13 PcatPciRootBridgeIo.c
14
15 Abstract:
16
17 EFI PC AT PCI Root Bridge Io Protocol
18
19 Revision History
20
21 --*/
22
23 #include "PcatPciRootBridge.h"
24
25 static BOOLEAN mPciOptionRomTableInstalled = FALSE;
26 static EFI_PCI_OPTION_ROM_TABLE mPciOptionRomTable = {0, NULL};
27
28 EFI_STATUS
29 PcatRootBridgeIoIoRead (
30 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
31 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
32 IN UINT64 UserAddress,
33 IN UINTN Count,
34 IN OUT VOID *UserBuffer
35 )
36 {
37 return gCpuIo->Io.Read (
38 gCpuIo,
39 (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
40 UserAddress,
41 Count,
42 UserBuffer
43 );
44 }
45
46 EFI_STATUS
47 PcatRootBridgeIoIoWrite (
48 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
49 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
50 IN UINT64 UserAddress,
51 IN UINTN Count,
52 IN OUT VOID *UserBuffer
53 )
54 {
55 return gCpuIo->Io.Write (
56 gCpuIo,
57 (EFI_CPU_IO_PROTOCOL_WIDTH) Width,
58 UserAddress,
59 Count,
60 UserBuffer
61 );
62
63 }
64
65 EFI_STATUS
66 PcatRootBridgeIoGetIoPortMapping (
67 OUT EFI_PHYSICAL_ADDRESS *IoPortMapping,
68 OUT EFI_PHYSICAL_ADDRESS *MemoryPortMapping
69 )
70 /*++
71
72 Get the IO Port Mapping. For IA-32 it is always 0.
73
74 --*/
75 {
76 *IoPortMapping = 0;
77 *MemoryPortMapping = 0;
78
79 return EFI_SUCCESS;
80 }
81
82 EFI_STATUS
83 PcatRootBridgeIoPciRW (
84 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
85 IN BOOLEAN Write,
86 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
87 IN UINT64 UserAddress,
88 IN UINTN Count,
89 IN OUT VOID *UserBuffer
90 )
91 {
92 PCI_CONFIG_ACCESS_CF8 Pci;
93 PCI_CONFIG_ACCESS_CF8 PciAligned;
94 UINT32 InStride;
95 UINT32 OutStride;
96 UINTN PciData;
97 UINTN PciDataStride;
98 PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
99 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress;
100 UINT64 PciExpressRegAddr;
101 BOOLEAN UsePciExpressAccess;
102
103 if (Width < 0 || Width >= EfiPciWidthMaximum) {
104 return EFI_INVALID_PARAMETER;
105 }
106
107 if ((Width & 0x03) >= EfiPciWidthUint64) {
108 return EFI_INVALID_PARAMETER;
109 }
110
111 PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
112
113 InStride = 1 << (Width & 0x03);
114 OutStride = InStride;
115 if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
116 InStride = 0;
117 }
118
119 if (Width >= EfiCpuIoWidthFillUint8 && Width <= EfiCpuIoWidthFillUint64) {
120 OutStride = 0;
121 }
122
123 UsePciExpressAccess = FALSE;
124
125 CopyMem (&PciAddress, &UserAddress, sizeof(UINT64));
126
127 if (PciAddress.ExtendedRegister > 0xFF) {
128 //
129 // Check PciExpressBaseAddress
130 //
131 if ((PrivateData->PciExpressBaseAddress == 0) ||
132 (PrivateData->PciExpressBaseAddress >= EFI_MAX_ADDRESS)) {
133 return EFI_UNSUPPORTED;
134 } else {
135 UsePciExpressAccess = TRUE;
136 }
137 } else {
138 if (PciAddress.ExtendedRegister != 0) {
139 Pci.Bits.Reg = PciAddress.ExtendedRegister & 0xFF;
140 } else {
141 Pci.Bits.Reg = PciAddress.Register;
142 }
143 //
144 // Note: We can also use PciExpress access here, if wanted.
145 //
146 }
147
148 if (!UsePciExpressAccess) {
149 Pci.Bits.Func = PciAddress.Function;
150 Pci.Bits.Dev = PciAddress.Device;
151 Pci.Bits.Bus = PciAddress.Bus;
152 Pci.Bits.Reserved = 0;
153 Pci.Bits.Enable = 1;
154
155 //
156 // PCI Config access are all 32-bit alligned, but by accessing the
157 // CONFIG_DATA_REGISTER (0xcfc) with different widths more cycle types
158 // are possible on PCI.
159 //
160 // To read a byte of PCI config space you load 0xcf8 and
161 // read 0xcfc, 0xcfd, 0xcfe, 0xcff
162 //
163 PciDataStride = Pci.Bits.Reg & 0x03;
164
165 while (Count) {
166 PciAligned = Pci;
167 PciAligned.Bits.Reg &= 0xfc;
168 PciData = (UINTN)PrivateData->PciData + PciDataStride;
169 EfiAcquireLock(&PrivateData->PciLock);
170 This->Io.Write (This, EfiPciWidthUint32, PrivateData->PciAddress, 1, &PciAligned);
171 if (Write) {
172 This->Io.Write (This, Width, PciData, 1, UserBuffer);
173 } else {
174 This->Io.Read (This, Width, PciData, 1, UserBuffer);
175 }
176 EfiReleaseLock(&PrivateData->PciLock);
177 UserBuffer = ((UINT8 *)UserBuffer) + OutStride;
178 PciDataStride = (PciDataStride + InStride) % 4;
179 Pci.Bits.Reg += InStride;
180 Count -= 1;
181 }
182 } else {
183 //
184 // Access PCI-Express space by using memory mapped method.
185 //
186 PciExpressRegAddr = (PrivateData->PciExpressBaseAddress) |
187 (PciAddress.Bus << 20) |
188 (PciAddress.Device << 15) |
189 (PciAddress.Function << 12);
190 if (PciAddress.ExtendedRegister != 0) {
191 PciExpressRegAddr += PciAddress.ExtendedRegister;
192 } else {
193 PciExpressRegAddr += PciAddress.Register;
194 }
195 while (Count) {
196 if (Write) {
197 This->Mem.Write (This, Width, (UINTN) PciExpressRegAddr, 1, UserBuffer);
198 } else {
199 This->Mem.Read (This, Width, (UINTN) PciExpressRegAddr, 1, UserBuffer);
200 }
201
202 UserBuffer = ((UINT8 *) UserBuffer) + OutStride;
203 PciExpressRegAddr += InStride;
204 Count -= 1;
205 }
206 }
207
208 return EFI_SUCCESS;
209 }
210
211 static
212 VOID
213 ScanPciBus(
214 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,
215 UINT16 MinBus,
216 UINT16 MaxBus,
217 UINT16 MinDevice,
218 UINT16 MaxDevice,
219 UINT16 MinFunc,
220 UINT16 MaxFunc,
221 EFI_PCI_BUS_SCAN_CALLBACK Callback,
222 VOID *Context
223 )
224
225 {
226 UINT16 Bus;
227 UINT16 Device;
228 UINT16 Func;
229 UINT64 Address;
230 PCI_TYPE00 PciHeader;
231
232 //
233 // Loop through all busses
234 //
235 for (Bus = MinBus; Bus <= MaxBus; Bus++) {
236 //
237 // Loop 32 devices per bus
238 //
239 for (Device = MinDevice; Device <= MaxDevice; Device++) {
240 //
241 // Loop through 8 functions per device
242 //
243 for (Func = MinFunc; Func <= MaxFunc; Func++) {
244
245 //
246 // Compute the EFI Address required to access the PCI Configuration Header of this PCI Device
247 //
248 Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);
249
250 //
251 // Read the VendorID from this PCI Device's Confioguration Header
252 //
253 IoDev->Pci.Read (IoDev, EfiPciWidthUint16, Address, 1, &PciHeader.Hdr.VendorId);
254
255 //
256 // If VendorId = 0xffff, there does not exist a device at this
257 // location. For each device, if there is any function on it,
258 // there must be 1 function at Function 0. So if Func = 0, there
259 // will be no more functions in the same device, so we can break
260 // loop to deal with the next device.
261 //
262 if (PciHeader.Hdr.VendorId == 0xffff && Func == 0) {
263 break;
264 }
265
266 if (PciHeader.Hdr.VendorId != 0xffff) {
267
268 //
269 // Read the HeaderType to determine if this is a multi-function device
270 //
271 IoDev->Pci.Read (IoDev, EfiPciWidthUint8, Address + 0x0e, 1, &PciHeader.Hdr.HeaderType);
272
273 //
274 // Call the callback function for the device that was found
275 //
276 Callback(
277 IoDev,
278 MinBus, MaxBus,
279 MinDevice, MaxDevice,
280 MinFunc, MaxFunc,
281 Bus,
282 Device,
283 Func,
284 Context
285 );
286
287 //
288 // If this is not a multi-function device, we can leave the loop
289 // to deal with the next device.
290 //
291 if ((PciHeader.Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION) == 0x00 && Func == 0) {
292 break;
293 }
294 }
295 }
296 }
297 }
298 }
299
300 static
301 VOID
302 CheckForRom (
303 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,
304 UINT16 MinBus,
305 UINT16 MaxBus,
306 UINT16 MinDevice,
307 UINT16 MaxDevice,
308 UINT16 MinFunc,
309 UINT16 MaxFunc,
310 UINT16 Bus,
311 UINT16 Device,
312 UINT16 Func,
313 IN VOID *VoidContext
314 )
315 {
316 EFI_STATUS Status;
317 PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT *Context;
318 UINT64 Address;
319 PCI_TYPE00 PciHeader;
320 PCI_TYPE01 *PciBridgeHeader;
321 UINT32 Register;
322 UINT32 RomBar;
323 UINT32 RomBarSize;
324 EFI_PHYSICAL_ADDRESS RomBuffer;
325 UINT32 MaxRomSize;
326 EFI_PCI_EXPANSION_ROM_HEADER EfiRomHeader;
327 PCI_DATA_STRUCTURE Pcir;
328 EFI_PCI_OPTION_ROM_DESCRIPTOR *TempPciOptionRomDescriptors;
329 BOOLEAN LastImage;
330
331 Context = (PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT *)VoidContext;
332
333 Address = EFI_PCI_ADDRESS (Bus, Device, Func, 0);
334
335 //
336 // Save the contents of the PCI Configuration Header
337 //
338 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, Address, sizeof(PciHeader)/sizeof(UINT32), &PciHeader);
339
340 if (IS_PCI_BRIDGE(&PciHeader)) {
341
342 PciBridgeHeader = (PCI_TYPE01 *)(&PciHeader);
343
344 //
345 // See if the PCI-PCI Bridge has its secondary interface enabled.
346 //
347 if (PciBridgeHeader->Bridge.SubordinateBus >= PciBridgeHeader->Bridge.SecondaryBus) {
348
349 //
350 // Disable the Prefetchable Memory Window
351 //
352 Register = 0x00000000;
353 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 0x26, 1, &Register);
354 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, Address + 0x2c, 1, &Register);
355 Register = 0xffffffff;
356 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 0x24, 1, &Register);
357 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 0x28, 1, &Register);
358
359 //
360 // Program Memory Window to the PCI Root Bridge Memory Window
361 //
362 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 0x20, 4, &Context->PpbMemoryWindow);
363
364 //
365 // Enable the Memory decode for the PCI-PCI Bridge
366 //
367 IoDev->Pci.Read (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
368 Register |= 0x02;
369 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
370
371 //
372 // Recurse on the Secondary Bus Number
373 //
374 ScanPciBus(
375 IoDev,
376 PciBridgeHeader->Bridge.SecondaryBus, PciBridgeHeader->Bridge.SecondaryBus,
377 0, PCI_MAX_DEVICE,
378 0, PCI_MAX_FUNC,
379 CheckForRom, Context
380 );
381 }
382 } else {
383
384 //
385 // Check if an Option ROM Register is present and save the Option ROM Window Register
386 //
387 RomBar = 0xffffffff;
388 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, Address + 0x30, 1, &RomBar);
389 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, Address + 0x30, 1, &RomBar);
390
391 RomBarSize = (~(RomBar & 0xfffff800)) + 1;
392
393 //
394 // Make sure the size of the ROM is between 0 and 16 MB
395 //
396 if (RomBarSize > 0 && RomBarSize <= 0x01000000) {
397
398 //
399 // Program Option ROM Window Register to the PCI Root Bridge Window and Enable the Option ROM Window
400 //
401 RomBar = (Context->PpbMemoryWindow & 0xffff) << 16;
402 RomBar = ((RomBar - 1) & (~(RomBarSize - 1))) + RomBarSize;
403 if (RomBar < (Context->PpbMemoryWindow & 0xffff0000)) {
404 MaxRomSize = (Context->PpbMemoryWindow & 0xffff0000) - RomBar;
405 RomBar = RomBar + 1;
406 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, Address + 0x30, 1, &RomBar);
407 IoDev->Pci.Read (IoDev, EfiPciWidthUint32, Address + 0x30, 1, &RomBar);
408 RomBar = RomBar - 1;
409
410 //
411 // Enable the Memory decode for the PCI Device
412 //
413 IoDev->Pci.Read (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
414 Register |= 0x02;
415 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
416
417 //
418 // Follow the chain of images to determine the size of the Option ROM present
419 // Keep going until the last image is found by looking at the Indicator field
420 // or the size of an image is 0, or the size of all the images is bigger than the
421 // size of the window programmed into the PPB.
422 //
423 RomBarSize = 0;
424 do {
425
426 LastImage = TRUE;
427
428 ZeroMem (&EfiRomHeader, sizeof(EfiRomHeader));
429 IoDev->Mem.Read (
430 IoDev,
431 EfiPciWidthUint8,
432 RomBar + RomBarSize,
433 sizeof(EfiRomHeader),
434 &EfiRomHeader
435 );
436
437 Pcir.ImageLength = 0;
438
439 if (EfiRomHeader.Signature == 0xaa55) {
440
441 ZeroMem (&Pcir, sizeof(Pcir));
442 IoDev->Mem.Read (
443 IoDev,
444 EfiPciWidthUint8,
445 RomBar + RomBarSize + EfiRomHeader.PcirOffset,
446 sizeof(Pcir),
447 &Pcir
448 );
449
450 if ((Pcir.Indicator & 0x80) == 0x00) {
451 LastImage = FALSE;
452 }
453
454 RomBarSize += Pcir.ImageLength * 512;
455 }
456 } while (!LastImage && RomBarSize < MaxRomSize && Pcir.ImageLength !=0);
457
458 if (RomBarSize > 0) {
459
460 //
461 // Allocate a memory buffer for the Option ROM contents.
462 //
463 Status = gBS->AllocatePages(
464 AllocateAnyPages,
465 EfiBootServicesData,
466 EFI_SIZE_TO_PAGES(RomBarSize),
467 &RomBuffer
468 );
469
470 if (!EFI_ERROR (Status)) {
471
472 //
473 // Copy the contents of the Option ROM to the memory buffer
474 //
475 IoDev->Mem.Read (IoDev, EfiPciWidthUint32, RomBar, RomBarSize / sizeof(UINT32), (VOID *)(UINTN)RomBuffer);
476
477 Status = gBS->AllocatePool(
478 EfiBootServicesData,
479 ((UINT32)mPciOptionRomTable.PciOptionRomCount + 1) * sizeof(EFI_PCI_OPTION_ROM_DESCRIPTOR),
480 &TempPciOptionRomDescriptors
481 );
482 if (mPciOptionRomTable.PciOptionRomCount > 0) {
483 CopyMem(
484 TempPciOptionRomDescriptors,
485 mPciOptionRomTable.PciOptionRomDescriptors,
486 (UINT32)mPciOptionRomTable.PciOptionRomCount * sizeof(EFI_PCI_OPTION_ROM_DESCRIPTOR)
487 );
488
489 gBS->FreePool(mPciOptionRomTable.PciOptionRomDescriptors);
490 }
491
492 mPciOptionRomTable.PciOptionRomDescriptors = TempPciOptionRomDescriptors;
493
494 TempPciOptionRomDescriptors = &(mPciOptionRomTable.PciOptionRomDescriptors[(UINT32)mPciOptionRomTable.PciOptionRomCount]);
495
496 TempPciOptionRomDescriptors->RomAddress = RomBuffer;
497 TempPciOptionRomDescriptors->MemoryType = EfiBootServicesData;
498 TempPciOptionRomDescriptors->RomLength = RomBarSize;
499 TempPciOptionRomDescriptors->Seg = (UINT32)IoDev->SegmentNumber;
500 TempPciOptionRomDescriptors->Bus = (UINT8)Bus;
501 TempPciOptionRomDescriptors->Dev = (UINT8)Device;
502 TempPciOptionRomDescriptors->Func = (UINT8)Func;
503 TempPciOptionRomDescriptors->ExecutedLegacyBiosImage = TRUE;
504 TempPciOptionRomDescriptors->DontLoadEfiRom = FALSE;
505
506 mPciOptionRomTable.PciOptionRomCount++;
507 }
508 }
509
510 //
511 // Disable the Memory decode for the PCI-PCI Bridge
512 //
513 IoDev->Pci.Read (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
514 Register &= (~0x02);
515 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 4, 1, &Register);
516 }
517 }
518 }
519
520 //
521 // Restore the PCI Configuration Header
522 //
523 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, Address, sizeof(PciHeader)/sizeof(UINT32), &PciHeader);
524 }
525
526 static
527 VOID
528 SaveCommandRegister (
529 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,
530 UINT16 MinBus,
531 UINT16 MaxBus,
532 UINT16 MinDevice,
533 UINT16 MaxDevice,
534 UINT16 MinFunc,
535 UINT16 MaxFunc,
536 UINT16 Bus,
537 UINT16 Device,
538 UINT16 Func,
539 IN VOID *VoidContext
540 )
541
542 {
543 PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT *Context;
544 UINT64 Address;
545 UINTN Index;
546 UINT16 Command;
547
548 Context = (PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT *)VoidContext;
549
550 Address = EFI_PCI_ADDRESS (Bus, Device, Func, 4);
551
552 Index = (Bus - MinBus) * (PCI_MAX_DEVICE+1) * (PCI_MAX_FUNC+1) + Device * (PCI_MAX_FUNC+1) + Func;
553
554 IoDev->Pci.Read (IoDev, EfiPciWidthUint16, Address, 1, &Context->CommandRegisterBuffer[Index]);
555
556 //
557 // Clear the memory enable bit
558 //
559 Command = Context->CommandRegisterBuffer[Index] & (~0x02);
560
561 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address, 1, &Command);
562 }
563
564 static
565 VOID
566 RestoreCommandRegister (
567 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,
568 UINT16 MinBus,
569 UINT16 MaxBus,
570 UINT16 MinDevice,
571 UINT16 MaxDevice,
572 UINT16 MinFunc,
573 UINT16 MaxFunc,
574 UINT16 Bus,
575 UINT16 Device,
576 UINT16 Func,
577 IN VOID *VoidContext
578 )
579
580 {
581 PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT *Context;
582 UINT64 Address;
583 UINTN Index;
584
585 Context = (PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT *)VoidContext;
586
587 Address = EFI_PCI_ADDRESS (Bus, Device, Func, 4);
588
589 Index = (Bus - MinBus) * (PCI_MAX_DEVICE+1) * (PCI_MAX_FUNC+1) + Device * (PCI_MAX_FUNC+1) + Func;
590
591 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address, 1, &Context->CommandRegisterBuffer[Index]);
592 }
593
594 EFI_STATUS
595 ScanPciRootBridgeForRoms(
596 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev
597 )
598
599 {
600 EFI_STATUS Status;
601 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;
602 UINT16 MinBus;
603 UINT16 MaxBus;
604 UINT64 RootWindowBase;
605 UINT64 RootWindowLimit;
606 PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT Context;
607
608 if (mPciOptionRomTableInstalled == FALSE) {
609 gBS->InstallConfigurationTable(&gEfiPciOptionRomTableGuid, &mPciOptionRomTable);
610 mPciOptionRomTableInstalled = TRUE;
611 }
612
613 Status = IoDev->Configuration(IoDev, &Descriptors);
614 if (EFI_ERROR (Status) || Descriptors == NULL) {
615 return EFI_NOT_FOUND;
616 }
617
618 MinBus = 0xffff;
619 MaxBus = 0xffff;
620 RootWindowBase = 0;
621 RootWindowLimit = 0;
622 while (Descriptors->Desc != ACPI_END_TAG_DESCRIPTOR) {
623 //
624 // Find bus range
625 //
626 if (Descriptors->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {
627 MinBus = (UINT16)Descriptors->AddrRangeMin;
628 MaxBus = (UINT16)Descriptors->AddrRangeMax;
629 }
630 //
631 // Find memory descriptors that are not prefetchable
632 //
633 if (Descriptors->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM && Descriptors->SpecificFlag == 0) {
634 //
635 // Find Memory Descriptors that are less than 4GB, so the PPB Memory Window can be used for downstream devices
636 //
637 if (Descriptors->AddrRangeMax < 0x100000000) {
638 //
639 // Find the largest Non-Prefetchable Memory Descriptor that is less than 4GB
640 //
641 if ((Descriptors->AddrRangeMax - Descriptors->AddrRangeMin) > (RootWindowLimit - RootWindowBase)) {
642 RootWindowBase = Descriptors->AddrRangeMin;
643 RootWindowLimit = Descriptors->AddrRangeMax;
644 }
645 }
646 }
647 Descriptors ++;
648 }
649
650 //
651 // Make sure a bus range was found
652 //
653 if (MinBus == 0xffff || MaxBus == 0xffff) {
654 return EFI_NOT_FOUND;
655 }
656
657 //
658 // Make sure a non-prefetchable memory region was found
659 //
660 if (RootWindowBase == 0 && RootWindowLimit == 0) {
661 return EFI_NOT_FOUND;
662 }
663
664 //
665 // Round the Base and Limit values to 1 MB boudaries
666 //
667 RootWindowBase = ((RootWindowBase - 1) & 0xfff00000) + 0x00100000;
668 RootWindowLimit = ((RootWindowLimit + 1) & 0xfff00000) - 1;
669
670 //
671 // Make sure that the size of the rounded window is greater than zero
672 //
673 if (RootWindowLimit <= RootWindowBase) {
674 return EFI_NOT_FOUND;
675 }
676
677 //
678 // Allocate buffer to save the Command register from all the PCI devices
679 //
680 Context.CommandRegisterBuffer = NULL;
681 Status = gBS->AllocatePool(
682 EfiBootServicesData,
683 sizeof(UINT16) * (MaxBus - MinBus + 1) * (PCI_MAX_DEVICE+1) * (PCI_MAX_FUNC+1),
684 &Context.CommandRegisterBuffer
685 );
686
687 if (EFI_ERROR (Status)) {
688 return Status;
689 }
690
691 Context.PpbMemoryWindow = (((UINT32)RootWindowBase) >> 16) | ((UINT32)RootWindowLimit & 0xffff0000);
692
693 //
694 // Save the Command register from all the PCI devices, and disable the I/O, Mem, and BusMaster bits
695 //
696 ScanPciBus(
697 IoDev,
698 MinBus, MaxBus,
699 0, PCI_MAX_DEVICE,
700 0, PCI_MAX_FUNC,
701 SaveCommandRegister, &Context
702 );
703
704 //
705 // Recursively scan all the busses for PCI Option ROMs
706 //
707 ScanPciBus(
708 IoDev,
709 MinBus, MinBus,
710 0, PCI_MAX_DEVICE,
711 0, PCI_MAX_FUNC,
712 CheckForRom, &Context
713 );
714
715 //
716 // Restore the Command register in all the PCI devices
717 //
718 ScanPciBus(
719 IoDev,
720 MinBus, MaxBus,
721 0, PCI_MAX_DEVICE,
722 0, PCI_MAX_FUNC,
723 RestoreCommandRegister, &Context
724 );
725
726 //
727 // Free the buffer used to save all the Command register values
728 //
729 gBS->FreePool(Context.CommandRegisterBuffer);
730
731 return EFI_SUCCESS;
732 }
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