2 Header file for IDE Bus Driver's Data Structures
4 Copyright (c) 2006 - 2007 Intel Corporation. <BR>
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
31 #define bit10 (1 << 10)
32 #define bit11 (1 << 11)
33 #define bit12 (1 << 12)
34 #define bit13 (1 << 13)
35 #define bit14 (1 << 14)
36 #define bit15 (1 << 15)
37 #define bit16 (1 << 16)
38 #define bit17 (1 << 17)
39 #define bit18 (1 << 18)
40 #define bit19 (1 << 19)
41 #define bit20 (1 << 20)
42 #define bit21 (1 << 21)
43 #define bit22 (1 << 22)
44 #define bit23 (1 << 23)
45 #define bit24 (1 << 24)
46 #define bit25 (1 << 25)
47 #define bit26 (1 << 26)
48 #define bit27 (1 << 27)
49 #define bit28 (1 << 28)
50 #define bit29 (1 << 29)
51 #define bit30 (1 << 30)
52 #define bit31 (1 << 31)
57 #define STALL_1_MILLI_SECOND 1000 // stall 1 ms
58 #define STALL_1_SECOND 1000000 // stall 1 second
72 IdeMagnetic
, /* ZIP Drive or LS120 Floppy Drive */
73 IdeCdRom
, /* ATAPI CDROM */
74 IdeHardDisk
, /* Hard Disk */
75 Ide48bitAddressingHardDisk
, /* Hard Disk larger than 120GB */
81 SenseDeviceNotReadyNoRetry
,
82 SenseDeviceNotReadyNeedRetry
,
100 UINT16 Command
; /* when write */
101 UINT16 Status
; /* when read */
105 UINT16 Error
; /* when read */
106 UINT16 Feature
; /* when write */
107 } IDE_ERROR_OR_FEATURE
;
110 UINT16 AltStatus
; /* when read */
111 UINT16 DeviceControl
; /* when write */
112 } IDE_AltStatus_OR_DeviceControl
;
119 IDE_ERROR_OR_FEATURE Reg1
;
125 IDE_CMD_OR_STATUS Reg
;
127 IDE_AltStatus_OR_DeviceControl Alt
;
131 UINT16 BusMasterBaseAddr
;
132 } IDE_BASE_REGISTERS
;
135 // IDE registers' base addresses
138 UINT16 CommandBlockBaseAddr
;
139 UINT16 ControlBlockBaseAddr
;
140 UINT16 BusMasterBaseAddr
;
141 } IDE_REGISTERS_BASE_ADDR
;
144 // Bit definitions in Programming Interface byte of the Class Code field
145 // in PCI IDE controller's Configuration Space
147 #define IDE_PRIMARY_OPERATING_MODE bit0
148 #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR bit1
149 #define IDE_SECONDARY_OPERATING_MODE bit2
150 #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR bit3
153 // IDE registers bit definitions
159 #define BBK_ERR bit7 /* Bad block detected */
160 #define UNC_ERR bit6 /* Uncorrectable Data */
161 #define MC_ERR bit5 /* Media Change */
162 #define IDNF_ERR bit4 /* ID Not Found */
163 #define MCR_ERR bit3 /* Media Change Requested */
164 #define ABRT_ERR bit2 /* Aborted Command */
165 #define TK0NF_ERR bit1 /* Track 0 Not Found */
166 #define AMNF_ERR bit0 /* Address Mark Not Found */
171 #define LBA_MODE bit6
186 #define BSY bit7 /* Controller Busy */
187 #define DRDY bit6 /* Drive Ready */
188 #define DWF bit5 /* Drive Write Fault */
189 #define DSC bit4 /* Disk Seek Complete */
190 #define DRQ bit3 /* Data Request */
191 #define CORR bit2 /* Corrected Data */
192 #define IDX bit1 /* Index */
193 #define ERR bit0 /* Error */
196 // Device Control Reg
198 #define SRST bit2 /* Software Reset */
199 #define IEN_L bit1 /* Interrupt Enable #*/
204 #define BMIC_nREAD bit3
205 #define BMIC_START bit0
206 #define BMIS_INTERRUPT bit2
207 #define BMIS_ERROR bit1
209 #define BMICP_OFFSET 0x00
210 #define BMISP_OFFSET 0x02
211 #define BMIDP_OFFSET 0x04
212 #define BMICS_OFFSET 0x08
213 #define BMISS_OFFSET 0x0A
214 #define BMIDS_OFFSET 0x0C
217 // Time Out Value For IDE Device Polling
221 // ATATIMEOUT is used for waiting time out for ATA device
227 #define ATATIMEOUT 1000
230 // ATAPITIMEOUT is used for waiting operation
231 // except read and write time out for ATAPI device
237 #define ATAPITIMEOUT 1000
240 // ATAPILONGTIMEOUT is used for waiting read and
241 // write operation timeout for ATAPI device
247 #define CDROMLONGTIMEOUT 2000
252 #define ATAPILONGTIMEOUT 5000
257 #define ATASMARTTIMEOUT 10000
262 #define ATA_INITIALIZE_DEVICE 0x91
267 #define IDENTIFY_DRIVE_CMD 0xec
268 #define READ_BUFFER_CMD 0xe4
269 #define READ_SECTORS_CMD 0x20
270 #define READ_SECTORS_WITH_RETRY_CMD 0x21
271 #define READ_LONG_CMD 0x22
272 #define READ_LONG_WITH_RETRY_CMD 0x23
274 // Class 1 - Atapi6 enhanced commands
276 #define READ_SECTORS_EXT_CMD 0x24
281 #define FORMAT_TRACK_CMD 0x50
282 #define WRITE_BUFFER_CMD 0xe8
283 #define WRITE_SECTORS_CMD 0x30
284 #define WRITE_SECTORS_WITH_RETRY_CMD 0x31
285 #define WRITE_LONG_CMD 0x32
286 #define WRITE_LONG_WITH_RETRY_CMD 0x33
287 #define WRITE_VERIFY_CMD 0x3c
289 // Class 2 - Atapi6 enhanced commands
291 #define WRITE_SECTORS_EXT_CMD 0x34
296 #define ACK_MEDIA_CHANGE_CMD 0xdb
297 #define BOOT_POST_BOOT_CMD 0xdc
298 #define BOOT_PRE_BOOT_CMD 0xdd
299 #define CHECK_POWER_MODE_CMD 0x98
300 #define CHECK_POWER_MODE_CMD_ALIAS 0xe5
301 #define DOOR_LOCK_CMD 0xde
302 #define DOOR_UNLOCK_CMD 0xdf
303 #define EXEC_DRIVE_DIAG_CMD 0x90
304 #define IDLE_CMD_ALIAS 0x97
305 #define IDLE_CMD 0xe3
306 #define IDLE_IMMEDIATE_CMD 0x95
307 #define IDLE_IMMEDIATE_CMD_ALIAS 0xe1
308 #define INIT_DRIVE_PARAM_CMD 0x91
309 #define RECALIBRATE_CMD 0x10 /* aliased to 1x */
310 #define READ_DRIVE_STATE_CMD 0xe9
311 #define SET_MULTIPLE_MODE_CMD 0xC6
312 #define READ_DRIVE_STATE_CMD 0xe9
313 #define READ_VERIFY_CMD 0x40
314 #define READ_VERIFY_WITH_RETRY_CMD 0x41
315 #define SEEK_CMD 0x70 /* aliased to 7x */
316 #define SET_FEATURES_CMD 0xef
317 #define STANDBY_CMD 0x96
318 #define STANDBY_CMD_ALIAS 0xe2
319 #define STANDBY_IMMEDIATE_CMD 0x94
320 #define STANDBY_IMMEDIATE_CMD_ALIAS 0xe0
325 #define READ_DMA_CMD 0xc8
326 #define READ_DMA_WITH_RETRY_CMD 0xc9
327 #define READ_DMA_EXT_CMD 0x25
328 #define WRITE_DMA_CMD 0xca
329 #define WRITE_DMA_WITH_RETRY_CMD 0xcb
330 #define WRITE_DMA_EXT_CMD 0x35
335 #define READ_MULTIPLE_CMD 0xc4
336 #define REST_CMD 0xe7
337 #define RESTORE_DRIVE_STATE_CMD 0xea
338 #define SET_SLEEP_MODE_CMD 0x99
339 #define SET_SLEEP_MODE_CMD_ALIAS 0xe6
340 #define WRITE_MULTIPLE_CMD 0xc5
341 #define WRITE_SAME_CMD 0xe9
344 // Class 6 - Host protected area access feature set
346 #define READ_NATIVE_MAX_ADDRESS_CMD 0xf8
347 #define SET_MAX_ADDRESS_CMD 0xf9
350 // Class 6 - ATA/ATAPI-6 enhanced commands
352 #define READ_NATIVE_MAX_ADDRESS_EXT_CMD 0x27
353 #define SET_MAX_ADDRESS_CMD_EXT 0x37
356 // Class 6 - SET_MAX related sub command (in feature register)
358 #define PARTIES_SET_MAX_ADDRESS_SUB_CMD 0x00
359 #define PARTIES_SET_PASSWORD_SUB_CMD 0x01
360 #define PARTIES_LOCK_SUB_CMD 0x02
361 #define PARTIES_UNLOCK_SUB_CMD 0x03
362 #define PARTIES_FREEZE_SUB_CMD 0x04
367 #define ATA_SMART_CMD 0xb0
368 #define ATA_CONSTANT_C2 0xc2
369 #define ATA_CONSTANT_4F 0x4f
370 #define ATA_SMART_ENABLE_OPERATION 0xd8
371 #define ATA_SMART_RETURN_STATUS 0xda
374 // Error codes for Exec Drive Diag
376 #define DRIV_DIAG_NO_ERROR (0x01)
377 #define DRIV_DIAG_FORMATTER_ERROR (0x02)
378 #define DRIV_DIAG_DATA_BUFFER_ERROR (0x03)
379 #define DRIV_DIAG_ECC_CKT_ERRROR (0x04)
380 #define DRIV_DIAG_UP_ERROR (0x05)
381 #define DRIV_DIAG_SLAVE_DRV_ERROR (0x80) /* aliased to 0x8x */
384 // Codes for Format Track
386 #define FORMAT_GOOD_SECTOR (0x00)
387 #define FORMAT_SUSPEND_ALLOC (0x01)
388 #define FORMAT_REALLOC_SECTOR (0x02)
389 #define FORMAT_MARK_SECTOR_DEFECTIVE (0x03)
395 #define ID_CONFIG_RESERVED0 bit0
396 #define ID_CONFIG_HARD_SECTORED_DRIVE bit1
397 #define ID_CONFIG_SOFT_SECTORED_DRIVE bit2
398 #define ID_CONFIG_NON_MFM bit3
399 #define ID_CONFIG_15uS_HEAD_SWITCHING bit4
400 #define ID_CONFIG_SPINDLE_MOTOR_CONTROL bit5
401 #define ID_CONFIG_HARD_DRIVE bit6
402 #define ID_CONFIG_CHANGEABLE_MEDIUM bit7
403 #define ID_CONFIG_DATA_RATE_TO_5MHZ bit8
404 #define ID_CONFIG_DATA_RATE_5_TO_10MHZ bit9
405 #define ID_CONFIG_DATA_RATE_ABOVE_10MHZ bit10
406 #define ID_CONFIG_MOTOR_SPEED_TOLERANCE_ABOVE_0_5_PERC bit11
407 #define ID_CONFIG_DATA_CLK_OFFSET_AVAIL bit12
408 #define ID_CONFIG_TRACK_OFFSET_AVAIL bit13
409 #define ID_CONFIG_SPEED_TOLERANCE_GAP_NECESSARY bit14
410 #define ID_CONFIG_RESERVED1 bit15
412 #define ID_DOUBLE_WORD_IO_POSSIBLE bit01
413 #define ID_LBA_SUPPORTED bit9
414 #define ID_DMA_SUPPORTED bit8
416 #define SET_FEATURE_ENABLE_8BIT_TRANSFER (0x01)
417 #define SET_FEATURE_ENABLE_WRITE_CACHE (0x02)
418 #define SET_FEATURE_TRANSFER_MODE (0x03)
419 #define SET_FEATURE_WRITE_SAME_WRITE_SPECIFIC_AREA (0x22)
420 #define SET_FEATURE_DISABLE_RETRIES (0x33)
422 // for Read & Write Longs
424 #define SET_FEATURE_VENDOR_SPEC_ECC_LENGTH (0x44)
425 #define SET_FEATURE_PLACE_NO_OF_CACHE_SEGMENTS_IN_SECTOR_NO_REG (0x54)
426 #define SET_FEATURE_DISABLE_READ_AHEAD (0x55)
427 #define SET_FEATURE_MAINTAIN_PARAM_AFTER_RESET (0x66)
428 #define SET_FEATURE_DISABLE_ECC (0x77)
429 #define SET_FEATURE_DISABLE_8BIT_TRANSFER (0x81)
430 #define SET_FEATURE_DISABLE_WRITE_CACHE (0x82)
431 #define SET_FEATURE_ENABLE_ECC (0x88)
432 #define SET_FEATURE_ENABLE_RETRIES (0x99)
433 #define SET_FEATURE_ENABLE_READ_AHEAD (0xaa)
434 #define SET_FEATURE_SET_SECTOR_CNT_REG_AS_NO_OF_READ_AHEAD_SECTORS (0xab)
435 #define SET_FEATURE_ALLOW_REST_MODE (0xac)
437 // for Read & Write Longs
439 #define SET_FEATURE_4BYTE_ECC (0xbb)
440 #define SET_FEATURE_DEFALUT_FEATURES_ON_SOFTWARE_RESET (0xcc)
441 #define SET_FEATURE_WRITE_SAME_TO_WRITE_ENTIRE_MEDIUM (0xdd)
443 #define BLOCK_TRANSFER_MODE (0x00)
444 #define SINGLE_WORD_DMA_TRANSFER_MODE (0x10)
445 #define MULTI_WORD_DMA_TRANSFER_MODE (0x20)
446 #define TRANSFER_MODE_MASK (0x07) // 3 LSBs
451 #define DEFAULT_DRIVE (0x00)
452 #define DEFAULT_CMD (0xa0)
454 // default content of device control register, disable INT
456 #define DEFAULT_CTL (0x0a)
457 #define DEFAULT_IDE_BM_IO_BASE_ADR (0xffa0)
460 // ATAPI6 related data structure definition
464 // The maximum sectors count in 28 bit addressing mode
466 #define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff
469 // Move the IDENTIFY section to DXE\Protocol\IdeControllerInit
475 #define ATAPI_SOFT_RESET_CMD 0x08
476 #define ATAPI_PACKET_CMD 0xA0
477 #define PACKET_CMD 0xA0
478 #define ATAPI_IDENTIFY_DEVICE_CMD 0xA1
479 #define ATAPI_SERVICE_CMD 0xA2
482 // ATAPI Packet Command
499 } TEST_UNIT_READY_CMD
;
503 UINT8 reserved_1
: 4;
507 UINT8 allocation_length
;
519 UINT8 reserved_1
: 4;
523 UINT8 allocation_length
;
535 UINT8 reserved_1
: 4;
538 UINT8 page_control
: 4;
543 UINT8 parameter_list_length_hi
;
544 UINT8 parameter_list_length_lo
;
552 UINT8 reserved_1
: 5;
574 UINT8 allocation_length_hi
;
575 UINT8 allocation_length_lo
;
579 } READ_FORMAT_CAP_CMD
;
583 TEST_UNIT_READY_CMD TestUnitReady
;
585 REQUEST_SENSE_CMD RequestSence
;
587 MODE_SENSE_CMD ModeSense
;
588 READ_FORMAT_CAP_CMD ReadFormatCapacity
;
589 } ATAPI_PACKET_COMMAND
;
592 UINT32 RegionBaseAddr
;
597 #define MAX_DMA_EXT_COMMAND_SECTORS 0x10000
598 #define MAX_DMA_COMMAND_SECTORS 0x100
603 // Packet Command Code
605 #define TEST_UNIT_READY 0x00
607 #define REQUEST_SENSE 0x03
608 #define FORMAT_UNIT 0x04
609 #define REASSIGN_BLOCKS 0x07
611 #define START_STOP_UNIT 0x1B
612 #define PREVENT_ALLOW_MEDIA_REMOVAL 0x1E
613 #define READ_FORMAT_CAPACITY 0x23
614 #define OLD_FORMAT_UNIT 0x24
615 #define READ_CAPACITY 0x25
617 #define WRITE_10 0x2A
619 #define SEND_DIAGNOSTICS 0x3D
620 #define WRITE_VERIFY 0x2E
622 #define READ_DEFECT_DATA 0x37
623 #define WRITE_BUFFER 0x38
624 #define READ_BUFFER 0x3C
625 #define READ_LONG 0x3E
626 #define WRITE_LONG 0x3F
627 #define MODE_SELECT 0x55
628 #define MODE_SENSE 0x5A
630 #define WRITE_12 0xAA
631 #define MAX_ATAPI_BYTE_COUNT (0xfffe)
636 #define REQUEST_SENSE_ERROR (0x70)
637 #define SK_NO_SENSE (0x0)
638 #define SK_RECOVERY_ERROR (0x1)
639 #define SK_NOT_READY (0x2)
640 #define SK_MEDIUM_ERROR (0x3)
641 #define SK_HARDWARE_ERROR (0x4)
642 #define SK_ILLEGAL_REQUEST (0x5)
643 #define SK_UNIT_ATTENTION (0x6)
644 #define SK_DATA_PROTECT (0x7)
645 #define SK_BLANK_CHECK (0x8)
646 #define SK_VENDOR_SPECIFIC (0x9)
647 #define SK_RESERVED_A (0xA)
648 #define SK_ABORT (0xB)
649 #define SK_RESERVED_C (0xC)
650 #define SK_OVERFLOW (0xD)
651 #define SK_MISCOMPARE (0xE)
652 #define SK_RESERVED_F (0xF)
655 // Additional Sense Codes
657 #define ASC_NOT_READY (0x04)
658 #define ASC_MEDIA_ERR1 (0x10)
659 #define ASC_MEDIA_ERR2 (0x11)
660 #define ASC_MEDIA_ERR3 (0x14)
661 #define ASC_MEDIA_ERR4 (0x30)
662 #define ASC_MEDIA_UPSIDE_DOWN (0x06)
663 #define ASC_INVALID_CMD (0x20)
664 #define ASC_LBA_OUT_OF_RANGE (0x21)
665 #define ASC_INVALID_FIELD (0x24)
666 #define ASC_WRITE_PROTECTED (0x27)
667 #define ASC_MEDIA_CHANGE (0x28)
668 #define ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */
669 #define ASC_ILLEGAL_FIELD (0x26)
670 #define ASC_NO_MEDIA (0x3A)
671 #define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
674 // Additional Sense Code Qualifier
676 #define ASCQ_IN_PROGRESS (0x01)
678 #define SETFEATURE TRUE
679 #define CLEARFEATURE FALSE
682 // ATAPI Data structure
687 UINT8 peripheral_type
;
690 UINT8 response_data_format
;
695 UINT8 vendor_info
[8];
696 UINT8 product_id
[12];
697 UINT8 eeprom_product_code
[4];
698 UINT8 firmware_rev_level
[4];
699 UINT8 firmware_sub_rev_level
[1];
703 UINT8 max_capacity_hi
;
704 UINT8 max_capacity_mid
;
705 UINT8 max_capacity_lo
;
706 UINT8 reserved_43_95
[95 - 43 + 1];
710 UINT8 peripheral_type
;
713 UINT8 response_data_format
;
718 UINT8 vendor_info
[8];
719 UINT8 product_id
[16];
720 UINT8 product_revision_level
[4];
721 UINT8 vendor_specific
[20];
722 UINT8 reserved_56_95
[40];
723 } CDROM_INQUIRY_DATA
;
726 UINT8 error_code
: 7;
730 UINT8 reserved_21
: 1;
732 UINT8 reserved_22
: 2;
733 UINT8 vendor_specific_3
;
734 UINT8 vendor_specific_4
;
735 UINT8 vendor_specific_5
;
736 UINT8 vendor_specific_6
;
737 UINT8 addnl_sense_length
; // n - 7
738 UINT8 vendor_specific_8
;
739 UINT8 vendor_specific_9
;
740 UINT8 vendor_specific_10
;
741 UINT8 vendor_specific_11
;
742 UINT8 addnl_sense_code
; // mandatory
743 UINT8 addnl_sense_code_qualifier
; // mandatory
744 UINT8 field_replaceable_unit_code
; // optional
749 // Followed by additional sense bytes : FIXME
751 } REQUEST_SENSE_DATA
;
762 } READ_CAPACITY_DATA
;
768 UINT8 Capacity_Length
;
774 UINT8 reserved_9
: 6;
778 } READ_FORMAT_CAPACITY_DATA
;
783 // PIO mode definition
786 ATA_PIO_MODE_BELOW_2
,
793 // Multi word DMA definition
802 // UDMA mode definition
813 #define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00
814 #define ATA_MODE_CATEGORY_FLOW_PIO 0x01
815 #define ATA_MODE_CATEGORY_MDMA 0x04
816 #define ATA_MODE_CATEGORY_UDMA 0x08
821 UINT8 ModeNumber
: 3;
822 UINT8 ModeCategory
: 5;
828 UINT8 MultipleSector
;
833 // IORDY Sample Point field value
841 // Recovery Time field value
843 #define RECVY_4_CLK 0
844 #define RECVY_3_CLK 1
845 #define RECVY_2_CLK 2
846 #define RECVY_1_CLK 3
849 // Slave IDE Timing Register Enable
854 // DMA Timing Enable Only Select 1
859 // Pre-fetch and Posting Enable Select 1
864 // IORDY Sample Point Enable Select 1
869 // Fast Timing Bank Drive Select 1
874 // DMA Timing Enable Only Select 0
879 // Pre-fetch and Posting Enable Select 0
884 // IOREY Sample Point Enable Select 0
889 // Fast Timing Bank Drive Select 0