3 Copyright (c) 2017 - 2019, ARM Limited. All rights reserved.
5 SPDX-License-Identifier: BSD-2-Clause-Patent
8 - Cm or CM - Configuration Manager
10 - Std or STD - Standard
13 #ifndef ARM_NAMESPACE_OBJECTS_H_
14 #define ARM_NAMESPACE_OBJECTS_H_
16 #include <StandardNameSpaceObjects.h>
20 /** The EARM_OBJECT_ID enum describes the Object IDs
23 typedef enum ArmObjectID
{
24 EArmObjReserved
, ///< 0 - Reserved
25 EArmObjBootArchInfo
, ///< 1 - Boot Architecture Info
26 EArmObjCpuInfo
, ///< 2 - CPU Info
27 EArmObjPowerManagementProfileInfo
, ///< 3 - Power Management Profile Info
28 EArmObjGicCInfo
, ///< 4 - GIC CPU Interface Info
29 EArmObjGicDInfo
, ///< 5 - GIC Distributor Info
30 EArmObjGicMsiFrameInfo
, ///< 6 - GIC MSI Frame Info
31 EArmObjGicRedistributorInfo
, ///< 7 - GIC Redistributor Info
32 EArmObjGicItsInfo
, ///< 8 - GIC ITS Info
33 EArmObjSerialConsolePortInfo
, ///< 9 - Serial Console Port Info
34 EArmObjSerialDebugPortInfo
, ///< 10 - Serial Debug Port Info
35 EArmObjGenericTimerInfo
, ///< 11 - Generic Timer Info
36 EArmObjPlatformGTBlockInfo
, ///< 12 - Platform GT Block Info
37 EArmObjGTBlockTimerFrameInfo
, ///< 13 - Generic Timer Block Frame Info
38 EArmObjPlatformGenericWatchdogInfo
, ///< 14 - Platform Generic Watchdog
39 EArmObjPciConfigSpaceInfo
, ///< 15 - PCI Configuration Space Info
40 EArmObjHypervisorVendorIdentity
, ///< 16 - Hypervisor Vendor Id
41 EArmObjFixedFeatureFlags
, ///< 17 - Fixed feature flags for FADT
42 EArmObjItsGroup
, ///< 18 - ITS Group
43 EArmObjNamedComponent
, ///< 19 - Named Component
44 EArmObjRootComplex
, ///< 20 - Root Complex
45 EArmObjSmmuV1SmmuV2
, ///< 21 - SMMUv1 or SMMUv2
46 EArmObjSmmuV3
, ///< 22 - SMMUv3
47 EArmObjPmcg
, ///< 23 - PMCG
48 EArmObjGicItsIdentifierArray
, ///< 24 - GIC ITS Identifier Array
49 EArmObjIdMappingArray
, ///< 25 - ID Mapping Array
50 EArmObjSmmuInterruptArray
, ///< 26 - SMMU Interrupt Array
51 EArmObjProcHierarchyInfo
, ///< 27 - Processor Hierarchy Info
52 EArmObjCacheInfo
, ///< 28 - Cache Info
53 EArmObjProcNodeIdInfo
, ///< 29 - Processor Hierarchy Node ID Info
54 EArmObjCmRef
, ///< 30 - CM Object Reference
58 /** A structure that describes the
59 ARM Boot Architecture flags.
61 ID: EArmObjBootArchInfo
63 typedef struct CmArmBootArchInfo
{
64 /** This is the ARM_BOOT_ARCH flags field of the FADT Table
65 described in the ACPI Table Specification.
68 } CM_ARM_BOOT_ARCH_INFO
;
70 typedef struct CmArmCpuInfo
{
71 // Reserved for use when SMBIOS tables are implemented
74 /** A structure that describes the
75 Power Management Profile Information for the Platform.
77 ID: EArmObjPowerManagementProfileInfo
79 typedef struct CmArmPowerManagementProfileInfo
{
80 /** This is the Preferred_PM_Profile field of the FADT Table
81 described in the ACPI Specification
83 UINT8 PowerManagementProfile
;
84 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO
;
86 /** A structure that describes the
87 GIC CPU Interface for the Platform.
91 typedef struct CmArmGicCInfo
{
92 /// The GIC CPU Interface number.
93 UINT32 CPUInterfaceNumber
;
95 /** The ACPI Processor UID. This must match the
96 _UID of the CPU Device object information described
97 in the DSDT/SSDT for the CPU.
99 UINT32 AcpiProcessorUid
;
101 /** The flags field as described by the GICC structure
102 in the ACPI Specification.
106 /** The parking protocol version field as described by
107 the GICC structure in the ACPI Specification.
109 UINT32 ParkingProtocolVersion
;
111 /** The Performance Interrupt field as described by
112 the GICC structure in the ACPI Specification.
114 UINT32 PerformanceInterruptGsiv
;
116 /** The CPU Parked address field as described by
117 the GICC structure in the ACPI Specification.
119 UINT64 ParkedAddress
;
121 /** The base address for the GIC CPU Interface
122 as described by the GICC structure in the
125 UINT64 PhysicalBaseAddress
;
127 /** The base address for GICV interface
128 as described by the GICC structure in the
133 /** The base address for GICH interface
134 as described by the GICC structure in the
139 /** The GICV maintenance interrupt
140 as described by the GICC structure in the
143 UINT32 VGICMaintenanceInterrupt
;
145 /** The base address for GICR interface
146 as described by the GICC structure in the
149 UINT64 GICRBaseAddress
;
151 /** The MPIDR for the CPU
152 as described by the GICC structure in the
157 /** The Processor Power Efficiency class
158 as described by the GICC structure in the
161 UINT8 ProcessorPowerEfficiencyClass
;
163 /** Statistical Profiling Extension buffer overflow GSIV. Zero if
164 unsupported by this processor. This field was introduced in
165 ACPI 6.3 (MADT revision 5) and is therefore ignored when
166 generating MADT revision 4 or lower.
168 UINT16 SpeOverflowInterrupt
;
171 /** A structure that describes the
172 GIC Distributor information for the Platform.
176 typedef struct CmArmGicDInfo
{
177 /// The Physical Base address for the GIC Distributor.
178 UINT64 PhysicalBaseAddress
;
180 /** The global system interrupt
181 number where this GIC Distributor's
182 interrupt inputs start.
184 UINT32 SystemVectorBase
;
186 /** The GIC version as described
187 by the GICD structure in the
193 /** A structure that describes the
194 GIC MSI Frame information for the Platform.
196 ID: EArmObjGicMsiFrameInfo
198 typedef struct CmArmGicMsiFrameInfo
{
199 /// The GIC MSI Frame ID
200 UINT32 GicMsiFrameId
;
202 /// The Physical base address for the MSI Frame
203 UINT64 PhysicalBaseAddress
;
205 /** The GIC MSI Frame flags
206 as described by the GIC MSI frame
207 structure in the ACPI Specification.
211 /// SPI Count used by this frame
214 /// SPI Base used by this frame
216 } CM_ARM_GIC_MSI_FRAME_INFO
;
218 /** A structure that describes the
219 GIC Redistributor information for the Platform.
221 ID: EArmObjGicRedistributorInfo
223 typedef struct CmArmGicRedistInfo
{
224 /** The physical address of a page range
225 containing all GIC Redistributors.
227 UINT64 DiscoveryRangeBaseAddress
;
229 /// Length of the GIC Redistributor Discovery page range
230 UINT32 DiscoveryRangeLength
;
231 } CM_ARM_GIC_REDIST_INFO
;
233 /** A structure that describes the
234 GIC Interrupt Translation Service information for the Platform.
236 ID: EArmObjGicItsInfo
238 typedef struct CmArmGicItsInfo
{
242 /// The physical address for the Interrupt Translation Service
243 UINT64 PhysicalBaseAddress
;
244 } CM_ARM_GIC_ITS_INFO
;
246 /** A structure that describes the
247 Serial Port information for the Platform.
249 ID: EArmObjSerialConsolePortInfo or
250 EArmObjSerialDebugPortInfo
252 typedef struct CmArmSerialPortInfo
{
253 /// The physical base address for the serial port
256 /// The serial port interrupt
259 /// The serial port baud rate
262 /// The serial port clock
265 /// Serial Port subtype
267 } CM_ARM_SERIAL_PORT_INFO
;
269 /** A structure that describes the
270 Generic Timer information for the Platform.
272 ID: EArmObjGenericTimerInfo
274 typedef struct CmArmGenericTimerInfo
{
275 /// The physical base address for the counter control frame
276 UINT64 CounterControlBaseAddress
;
278 /// The physical base address for the counter read frame
279 UINT64 CounterReadBaseAddress
;
281 /// The secure PL1 timer interrupt
282 UINT32 SecurePL1TimerGSIV
;
284 /// The secure PL1 timer flags
285 UINT32 SecurePL1TimerFlags
;
287 /// The non-secure PL1 timer interrupt
288 UINT32 NonSecurePL1TimerGSIV
;
290 /// The non-secure PL1 timer flags
291 UINT32 NonSecurePL1TimerFlags
;
293 /// The virtual timer interrupt
294 UINT32 VirtualTimerGSIV
;
296 /// The virtual timer flags
297 UINT32 VirtualTimerFlags
;
299 /// The non-secure PL2 timer interrupt
300 UINT32 NonSecurePL2TimerGSIV
;
302 /// The non-secure PL2 timer flags
303 UINT32 NonSecurePL2TimerFlags
;
305 /// GSIV for the virtual EL2 timer
306 UINT32 VirtualPL2TimerGSIV
;
308 /// Flags for the virtual EL2 timer
309 UINT32 VirtualPL2TimerFlags
;
310 } CM_ARM_GENERIC_TIMER_INFO
;
312 /** A structure that describes the
313 Platform Generic Block Timer Frame information for the Platform.
315 ID: EArmObjGTBlockTimerFrameInfo
317 typedef struct CmArmGTBlockTimerFrameInfo
{
318 /// The Generic Timer frame number
321 /// The physical base address for the CntBase block
322 UINT64 PhysicalAddressCntBase
;
324 /// The physical base address for the CntEL0Base block
325 UINT64 PhysicalAddressCntEL0Base
;
327 /// The physical timer interrupt
328 UINT32 PhysicalTimerGSIV
;
330 /** The physical timer flags as described by the GT Block
331 Timer frame Structure in the ACPI Specification.
333 UINT32 PhysicalTimerFlags
;
335 /// The virtual timer interrupt
336 UINT32 VirtualTimerGSIV
;
338 /** The virtual timer flags as described by the GT Block
339 Timer frame Structure in the ACPI Specification.
341 UINT32 VirtualTimerFlags
;
343 /** The common timer flags as described by the GT Block
344 Timer frame Structure in the ACPI Specification.
347 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO
;
349 /** A structure that describes the
350 Platform Generic Block Timer information for the Platform.
352 ID: EArmObjPlatformGTBlockInfo
354 typedef struct CmArmGTBlockInfo
{
355 /// The physical base address for the GT Block Timer structure
356 UINT64 GTBlockPhysicalAddress
;
358 /// The number of timer frames implemented in the GT Block
359 UINT32 GTBlockTimerFrameCount
;
361 /// Reference token for the GT Block timer frame list
362 CM_OBJECT_TOKEN GTBlockTimerFrameToken
;
363 } CM_ARM_GTBLOCK_INFO
;
365 /** A structure that describes the
366 SBSA Generic Watchdog information for the Platform.
368 ID: EArmObjPlatformGenericWatchdogInfo
370 typedef struct CmArmGenericWatchdogInfo
{
371 /// The physical base address of the SBSA Watchdog control frame
372 UINT64 ControlFrameAddress
;
374 /// The physical base address of the SBSA Watchdog refresh frame
375 UINT64 RefreshFrameAddress
;
377 /// The watchdog interrupt
380 /** The flags for the watchdog as described by the SBSA watchdog
381 structure in the ACPI specification.
384 } CM_ARM_GENERIC_WATCHDOG_INFO
;
386 /** A structure that describes the
387 PCI Configuration Space information for the Platform.
389 ID: EArmObjPciConfigSpaceInfo
391 typedef struct CmArmPciConfigSpaceInfo
{
392 /// The physical base address for the PCI segment
395 /// The PCI segment group number
396 UINT16 PciSegmentGroupNumber
;
398 /// The start bus number
399 UINT8 StartBusNumber
;
401 /// The end bus number
403 } CM_ARM_PCI_CONFIG_SPACE_INFO
;
405 /** A structure that describes the
406 Hypervisor Vendor ID information for the Platform.
408 ID: EArmObjHypervisorVendorIdentity
410 typedef struct CmArmHypervisorVendorId
{
411 /// The hypervisor Vendor ID
412 UINT64 HypervisorVendorId
;
413 } CM_ARM_HYPERVISOR_VENDOR_ID
;
415 /** A structure that describes the
416 Fixed feature flags for the Platform.
418 ID: EArmObjFixedFeatureFlags
420 typedef struct CmArmFixedFeatureFlags
{
421 /// The Fixed feature flags
423 } CM_ARM_FIXED_FEATURE_FLAGS
;
425 /** A structure that describes the
426 ITS Group node for the Platform.
430 typedef struct CmArmItsGroupNode
{
431 /// An unique token used to identify this object
432 CM_OBJECT_TOKEN Token
;
433 /// The number of ITS identifiers in the ITS node
435 /// Reference token for the ITS identifier array
436 CM_OBJECT_TOKEN ItsIdToken
;
437 } CM_ARM_ITS_GROUP_NODE
;
439 /** A structure that describes the
440 GIC ITS Identifiers for an ITS Group node.
442 ID: EArmObjGicItsIdentifierArray
444 typedef struct CmArmGicItsIdentifier
{
445 /// The ITS Identifier
447 } CM_ARM_ITS_IDENTIFIER
;
449 /** A structure that describes the
450 Named component node for the Platform.
452 ID: EArmObjNamedComponent
454 typedef struct CmArmNamedComponentNode
{
455 /// An unique token used to identify this object
456 CM_OBJECT_TOKEN Token
;
457 /// Number of ID mappings
458 UINT32 IdMappingCount
;
459 /// Reference token for the ID mapping array
460 CM_OBJECT_TOKEN IdMappingToken
;
462 /// Flags for the named component
465 /// Memory access properties : Cache coherent attributes
466 UINT32 CacheCoherent
;
467 /// Memory access properties : Allocation hints
468 UINT8 AllocationHints
;
469 /// Memory access properties : Memory access flags
470 UINT8 MemoryAccessFlags
;
472 /// Memory access properties : Address size limit
473 UINT8 AddressSizeLimit
;
474 /** ASCII Null terminated string with the full path to
475 the entry in the namespace for this object.
478 } CM_ARM_NAMED_COMPONENT_NODE
;
480 /** A structure that describes the
481 Root complex node for the Platform.
483 ID: EArmObjRootComplex
485 typedef struct CmArmRootComplexNode
{
486 /// An unique token used to identify this object
487 CM_OBJECT_TOKEN Token
;
488 /// Number of ID mappings
489 UINT32 IdMappingCount
;
490 /// Reference token for the ID mapping array
491 CM_OBJECT_TOKEN IdMappingToken
;
493 /// Memory access properties : Cache coherent attributes
494 UINT32 CacheCoherent
;
495 /// Memory access properties : Allocation hints
496 UINT8 AllocationHints
;
497 /// Memory access properties : Memory access flags
498 UINT8 MemoryAccessFlags
;
502 /// PCI segment number
503 UINT32 PciSegmentNumber
;
504 /// Memory address size limit
505 UINT8 MemoryAddressSize
;
506 } CM_ARM_ROOT_COMPLEX_NODE
;
508 /** A structure that describes the
509 SMMUv1 or SMMUv2 node for the Platform.
511 ID: EArmObjSmmuV1SmmuV2
513 typedef struct CmArmSmmuV1SmmuV2Node
{
514 /// An unique token used to identify this object
515 CM_OBJECT_TOKEN Token
;
516 /// Number of ID mappings
517 UINT32 IdMappingCount
;
518 /// Reference token for the ID mapping array
519 CM_OBJECT_TOKEN IdMappingToken
;
521 /// SMMU Base Address
523 /// Length of the memory range covered by the SMMU
530 /// Number of context interrupts
531 UINT32 ContextInterruptCount
;
532 /// Reference token for the context interrupt array
533 CM_OBJECT_TOKEN ContextInterruptToken
;
535 /// Number of PMU interrupts
536 UINT32 PmuInterruptCount
;
537 /// Reference token for the PMU interrupt array
538 CM_OBJECT_TOKEN PmuInterruptToken
;
540 /// GSIV of the SMMU_NSgIrpt interrupt
542 /// SMMU_NSgIrpt interrupt flags
543 UINT32 SMMU_NSgIrptFlags
;
544 /// GSIV of the SMMU_NSgCfgIrpt interrupt
545 UINT32 SMMU_NSgCfgIrpt
;
546 /// SMMU_NSgCfgIrpt interrupt flags
547 UINT32 SMMU_NSgCfgIrptFlags
;
548 } CM_ARM_SMMUV1_SMMUV2_NODE
;
550 /** A structure that describes the
551 SMMUv3 node for the Platform.
555 typedef struct CmArmSmmuV3Node
{
556 /// An unique token used to identify this object
557 CM_OBJECT_TOKEN Token
;
558 /// Number of ID mappings
559 UINT32 IdMappingCount
;
560 /// Reference token for the ID mapping array
561 CM_OBJECT_TOKEN IdMappingToken
;
563 /// SMMU Base Address
571 /// GSIV of the Event interrupt if SPI based
572 UINT32 EventInterrupt
;
573 /// PRI Interrupt if SPI based
575 /// GERR interrupt if GSIV based
576 UINT32 GerrInterrupt
;
577 /// Sync interrupt if GSIV based
578 UINT32 SyncInterrupt
;
580 /// Proximity domain flag
581 UINT32 ProximityDomain
;
582 /// Index into the array of ID mapping
583 UINT32 DeviceIdMappingIndex
;
584 } CM_ARM_SMMUV3_NODE
;
586 /** A structure that describes the
587 PMCG node for the Platform.
591 typedef struct CmArmPmcgNode
{
592 /// An unique token used to identify this object
593 CM_OBJECT_TOKEN Token
;
594 /// Number of ID mappings
595 UINT32 IdMappingCount
;
596 /// Reference token for the ID mapping array
597 CM_OBJECT_TOKEN IdMappingToken
;
599 /// Base Address for performance monitor counter group
601 /// GSIV for the Overflow interrupt
602 UINT32 OverflowInterrupt
;
603 /// Page 1 Base address
604 UINT64 Page1BaseAddress
;
606 /// Reference token for the IORT node associated with this node
607 CM_OBJECT_TOKEN ReferenceToken
;
610 /** A structure that describes the
611 ID Mappings for the Platform.
613 ID: EArmObjIdMappingArray
615 typedef struct CmArmIdMapping
{
618 /// Number of input IDs
622 /// Reference token for the output node
623 CM_OBJECT_TOKEN OutputReferenceToken
;
628 /** A structure that describes the
629 SMMU interrupts for the Platform.
631 ID: EArmObjSmmuInterruptArray
633 typedef struct CmArmSmmuInterrupt
{
639 } CM_ARM_SMMU_INTERRUPT
;
641 /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT
643 ID: EArmObjProcHierarchyInfo
645 typedef struct CmArmProcHierarchyInfo
{
646 /// A unique token used to identify this object
647 CM_OBJECT_TOKEN Token
;
648 /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)
650 /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor
651 /// topology. A value of CM_NULL_TOKEN means this node has no parent.
652 CM_OBJECT_TOKEN ParentToken
;
653 /// Token of the associated CM_ARM_GICC_INFO object which has the
654 /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this
655 /// node represents a group of associated processors and it does not have an
656 /// associated GIC CPU interface.
657 CM_OBJECT_TOKEN GicCToken
;
658 /// Number of resources private to this Node
659 UINT32 NoOfPrivateResources
;
660 /// Token of the array which contains references to the resources private to
661 /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if
662 /// the NoOfPrivateResources is 0, in which case it is recomended to set
663 /// this field to CM_NULL_TOKEN.
664 CM_OBJECT_TOKEN PrivateResourcesArrayToken
;
665 } CM_ARM_PROC_HIERARCHY_INFO
;
667 /** A structure that describes the Cache Type Structure (Type 1) in PPTT
671 typedef struct CmArmCacheInfo
{
672 /// A unique token used to identify this object
673 CM_OBJECT_TOKEN Token
;
674 /// Reference token for the next level of cache that is private to the same
675 /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this
676 /// entry represents the last cache level appropriate to the processor
677 /// hierarchy node structures using this entry.
678 CM_OBJECT_TOKEN NextLevelOfCacheToken
;
679 /// Size of the cache in bytes
681 /// Number of sets in the cache
683 /// Integer number of ways. The maximum associativity supported by
684 /// ACPI Cache type structure is limited to MAX_UINT8. However,
685 /// the maximum number of ways supported by the architecture is
686 /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field
688 UINT32 Associativity
;
689 /// Cache attributes (ACPI 6.3 - January 2019, PPTT, Table 5-156)
691 /// Line size in bytes
695 /** A structure that describes the ID Structure (Type 2) in PPTT
697 ID: EArmObjProcNodeIdInfo
699 typedef struct CmArmProcNodeIdInfo
{
700 /// A unique token used to identify this object
701 CM_OBJECT_TOKEN Token
;
702 // Vendor ID (as described in ACPI ID registry)
704 /// First level unique node ID
706 /// Second level unique node ID
708 /// Major revision of the node
710 /// Minor revision of the node
712 /// Spin revision of the node
714 } CM_ARM_PROC_NODE_ID_INFO
;
716 /** A structure that describes a reference to another Configuration Manager
719 This is useful for creating an array of reference tokens. The framework
720 can then query the configuration manager for these arrays using the
721 object ID EArmObjCmRef.
723 This can be used is to represent one-to-many relationships between objects.
727 typedef struct CmArmObjRef
{
728 /// Token of the CM object being referenced
729 CM_OBJECT_TOKEN ReferenceToken
;
734 #endif // ARM_NAMESPACE_OBJECTS_H_