DynamicTablesPkg/Include/ArmNameSpaceObjects.h

   1 /** @file
   2
   3   Copyright (c) 2017 - 2019, ARM Limited. All rights reserved.
   4
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13   @par Glossary:
  14     - Cm or CM   - Configuration Manager
  15     - Obj or OBJ - Object
  16     - Std or STD - Standard
  17 **/
  18
  19 #ifndef ARM_NAMESPACE_OBJECTS_H_
  20 #define ARM_NAMESPACE_OBJECTS_H_
  21
  22 #include <StandardNameSpaceObjects.h>
  23
  24 #pragma pack(1)
  25
  26 /** The EARM_OBJECT_ID enum describes the Object IDs
  27     in the ARM Namespace
  28 */
  29 typedef enum ArmObjectID {
  30   EArmObjReserved,                    ///<  0 - Reserved
  31   EArmObjBootArchInfo,                ///<  1 - Boot Architecture Info
  32   EArmObjCpuInfo,                     ///<  2 - CPU Info
  33   EArmObjPowerManagementProfileInfo,  ///<  3 - Power Management Profile Info
  34   EArmObjGicCInfo,                    ///<  4 - GIC CPU Interface Info
  35   EArmObjGicDInfo,                    ///<  5 - GIC Distributor Info
  36   EArmObjGicMsiFrameInfo,             ///<  6 - GIC MSI Frame Info
  37   EArmObjGicRedistributorInfo,        ///<  7 - GIC Redistributor Info
  38   EArmObjGicItsInfo,                  ///<  8 - GIC ITS Info
  39   EArmObjSerialConsolePortInfo,       ///<  9 - Serial Console Port Info
  40   EArmObjSerialDebugPortInfo,         ///< 10 - Serial Debug Port Info
  41   EArmObjGenericTimerInfo,            ///< 11 - Generic Timer Info
  42   EArmObjPlatformGTBlockInfo,         ///< 12 - Platform GT Block Info
  43   EArmObjGTBlockTimerFrameInfo,       ///< 13 - Generic Timer Block Frame Info
  44   EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog
  45   EArmObjPciConfigSpaceInfo,          ///< 15 - PCI Configuration Space Info
  46   EArmObjHypervisorVendorIdentity,    ///< 16 - Hypervisor Vendor Id
  47   EArmObjFixedFeatureFlags,           ///< 17 - Fixed feature flags for FADT
  48   EArmObjItsGroup,                    ///< 18 - ITS Group
  49   EArmObjNamedComponent,              ///< 19 - Named Component
  50   EArmObjRootComplex,                 ///< 20 - Root Complex
  51   EArmObjSmmuV1SmmuV2,                ///< 21 - SMMUv1 or SMMUv2
  52   EArmObjSmmuV3,                      ///< 22 - SMMUv3
  53   EArmObjPmcg,                        ///< 23 - PMCG
  54   EArmObjGicItsIdentifierArray,       ///< 24 - GIC ITS Identifier Array
  55   EArmObjIdMappingArray,              ///< 25 - ID Mapping Array
  56   EArmObjSmmuInterruptArray,          ///< 26 - SMMU Interrupt Array
  57   EArmObjMax
  58 } EARM_OBJECT_ID;
  59
  60 /** A structure that describes the
  61     ARM Boot Architecture flags.
  62
  63     ID: EArmObjBootArchInfo
  64 */
  65 typedef struct CmArmBootArchInfo {
  66   /** This is the ARM_BOOT_ARCH flags field of the FADT Table
  67       described in the ACPI Table Specification.
  68   */
  69   UINT32  BootArchFlags;
  70 } CM_ARM_BOOT_ARCH_INFO;
  71
  72 typedef struct CmArmCpuInfo {
  73   // Reserved for use when SMBIOS tables are implemented
  74 } CM_ARM_CPU_INFO;
  75
  76 /** A structure that describes the
  77     Power Management Profile Information for the Platform.
  78
  79     ID: EArmObjPowerManagementProfileInfo
  80 */
  81 typedef struct CmArmPowerManagementProfileInfo {
  82   /** This is the Preferred_PM_Profile field of the FADT Table
  83       described in the ACPI Specification
  84   */
  85   UINT8  PowerManagementProfile;
  86 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;
  87
  88 /** A structure that describes the
  89     GIC CPU Interface for the Platform.
  90
  91     ID: EArmObjGicCInfo
  92 */
  93 typedef struct CmArmGicCInfo {
  94   /// The GIC CPU Interface number.
  95   UINT32  CPUInterfaceNumber;
  96
  97   /** The ACPI Processor UID. This must match the
  98       _UID of the CPU Device object information described
  99       in the DSDT/SSDT for the CPU.
 100   */
 101   UINT32  AcpiProcessorUid;
 102
 103   /** The flags field as described by the GICC structure
 104       in the ACPI Specification.
 105   */
 106   UINT32  Flags;
 107
 108   /** The parking protocol version field as described by
 109     the GICC structure in the ACPI Specification.
 110   */
 111   UINT32  ParkingProtocolVersion;
 112
 113   /** The Performance Interrupt field as described by
 114       the GICC structure in the ACPI Specification.
 115   */
 116   UINT32  PerformanceInterruptGsiv;
 117
 118   /** The CPU Parked address field as described by
 119       the GICC structure in the ACPI Specification.
 120   */
 121   UINT64  ParkedAddress;
 122
 123   /** The base address for the GIC CPU Interface
 124       as described by the GICC structure in the
 125       ACPI Specification.
 126   */
 127   UINT64  PhysicalBaseAddress;
 128
 129   /** The base address for GICV interface
 130       as described by the GICC structure in the
 131       ACPI Specification.
 132   */
 133   UINT64  GICV;
 134
 135   /** The base address for GICH interface
 136       as described by the GICC structure in the
 137       ACPI Specification.
 138   */
 139   UINT64  GICH;
 140
 141   /** The GICV maintenance interrupt
 142       as described by the GICC structure in the
 143       ACPI Specification.
 144   */
 145   UINT32  VGICMaintenanceInterrupt;
 146
 147   /** The base address for GICR interface
 148       as described by the GICC structure in the
 149       ACPI Specification.
 150   */
 151   UINT64  GICRBaseAddress;
 152
 153   /** The MPIDR for the CPU
 154       as described by the GICC structure in the
 155       ACPI Specification.
 156   */
 157   UINT64  MPIDR;
 158
 159   /** The Processor Power Efficiency class
 160       as described by the GICC structure in the
 161       ACPI Specification.
 162   */
 163   UINT8   ProcessorPowerEfficiencyClass;
 164 } CM_ARM_GICC_INFO;
 165
 166 /** A structure that describes the
 167     GIC Distributor information for the Platform.
 168
 169     ID: EArmObjGicDInfo
 170 */
 171 typedef struct CmArmGicDInfo {
 172   /// The Physical Base address for the GIC Distributor.
 173   UINT64  PhysicalBaseAddress;
 174
 175   /** The global system interrupt
 176       number where this GIC Distributor's
 177       interrupt inputs start.
 178   */
 179   UINT32  SystemVectorBase;
 180
 181   /** The GIC version as described
 182       by the GICD structure in the
 183       ACPI Specification.
 184   */
 185   UINT8   GicVersion;
 186 } CM_ARM_GICD_INFO;
 187
 188 /** A structure that describes the
 189     GIC MSI Frame information for the Platform.
 190
 191     ID: EArmObjGicMsiFrameInfo
 192 */
 193 typedef struct CmArmGicMsiFrameInfo {
 194   /// The GIC MSI Frame ID
 195   UINT32  GicMsiFrameId;
 196
 197   /// The Physical base address for the MSI Frame
 198   UINT64  PhysicalBaseAddress;
 199
 200   /** The GIC MSI Frame flags
 201       as described by the GIC MSI frame
 202       structure in the ACPI Specification.
 203   */
 204   UINT32  Flags;
 205
 206   /// SPI Count used by this frame
 207   UINT16  SPICount;
 208
 209   /// SPI Base used by this frame
 210   UINT16  SPIBase;
 211 } CM_ARM_GIC_MSI_FRAME_INFO;
 212
 213 /** A structure that describes the
 214     GIC Redistributor information for the Platform.
 215
 216     ID: EArmObjGicRedistributorInfo
 217 */
 218 typedef struct CmArmGicRedistInfo {
 219   /** The physical address of a page range
 220       containing all GIC Redistributors.
 221   */
 222   UINT64  DiscoveryRangeBaseAddress;
 223
 224   /// Length of the GIC Redistributor Discovery page range
 225   UINT32  DiscoveryRangeLength;
 226 } CM_ARM_GIC_REDIST_INFO;
 227
 228 /** A structure that describes the
 229     GIC Interrupt Translation Service information for the Platform.
 230
 231     ID: EArmObjGicItsInfo
 232 */
 233 typedef struct CmArmGicItsInfo {
 234   /// The GIC ITS ID
 235   UINT32  GicItsId;
 236
 237   /// The physical address for the Interrupt Translation Service
 238   UINT64  PhysicalBaseAddress;
 239 } CM_ARM_GIC_ITS_INFO;
 240
 241 /** A structure that describes the
 242     Serial Port information for the Platform.
 243
 244     ID: EArmObjSerialConsolePortInfo or
 245         EArmObjSerialDebugPortInfo
 246 */
 247 typedef struct CmArmSerialPortInfo {
 248   /// The physical base address for the serial port
 249   UINT64  BaseAddress;
 250
 251   /// The serial port interrupt
 252   UINT32  Interrupt;
 253
 254   /// The serial port baud rate
 255   UINT64  BaudRate;
 256
 257   /// The serial port clock
 258   UINT32  Clock;
 259
 260   /// Serial Port subtype
 261   UINT16  PortSubtype;
 262 } CM_ARM_SERIAL_PORT_INFO;
 263
 264 /** A structure that describes the
 265     Generic Timer information for the Platform.
 266
 267     ID: EArmObjGenericTimerInfo
 268 */
 269 typedef struct CmArmGenericTimerInfo {
 270   /// The physical base address for the counter control frame
 271   UINT64  CounterControlBaseAddress;
 272
 273   /// The physical base address for the counter read frame
 274   UINT64  CounterReadBaseAddress;
 275
 276   /// The secure PL1 timer interrupt
 277   UINT32  SecurePL1TimerGSIV;
 278
 279   /// The secure PL1 timer flags
 280   UINT32  SecurePL1TimerFlags;
 281
 282   /// The non-secure PL1 timer interrupt
 283   UINT32  NonSecurePL1TimerGSIV;
 284
 285   /// The non-secure PL1 timer flags
 286   UINT32  NonSecurePL1TimerFlags;
 287
 288   /// The virtual timer interrupt
 289   UINT32  VirtualTimerGSIV;
 290
 291   /// The virtual timer flags
 292   UINT32  VirtualTimerFlags;
 293
 294   /// The non-secure PL2 timer interrupt
 295   UINT32  NonSecurePL2TimerGSIV;
 296
 297   /// The non-secure PL2 timer flags
 298   UINT32  NonSecurePL2TimerFlags;
 299 } CM_ARM_GENERIC_TIMER_INFO;
 300
 301 /** A structure that describes the
 302     Platform Generic Block Timer Frame information for the Platform.
 303
 304     ID: EArmObjGTBlockTimerFrameInfo
 305 */
 306 typedef struct CmArmGTBlockTimerFrameInfo {
 307   /// The Generic Timer frame number
 308   UINT8   FrameNumber;
 309
 310   /// The physical base address for the CntBase block
 311   UINT64  PhysicalAddressCntBase;
 312
 313   /// The physical base address for the CntEL0Base block
 314   UINT64  PhysicalAddressCntEL0Base;
 315
 316   /// The physical timer interrupt
 317   UINT32  PhysicalTimerGSIV;
 318
 319   /** The physical timer flags as described by the GT Block
 320       Timer frame Structure in the ACPI Specification.
 321   */
 322   UINT32  PhysicalTimerFlags;
 323
 324   /// The virtual timer interrupt
 325   UINT32  VirtualTimerGSIV;
 326
 327   /** The virtual timer flags as described by the GT Block
 328       Timer frame Structure in the ACPI Specification.
 329   */
 330   UINT32  VirtualTimerFlags;
 331
 332   /** The common timer flags as described by the GT Block
 333       Timer frame Structure in the ACPI Specification.
 334   */
 335   UINT32  CommonFlags;
 336 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;
 337
 338 /** A structure that describes the
 339     Platform Generic Block Timer information for the Platform.
 340
 341     ID: EArmObjPlatformGTBlockInfo
 342 */
 343 typedef struct CmArmGTBlockInfo {
 344   /// The physical base address for the GT Block Timer structure
 345   UINT64            GTBlockPhysicalAddress;
 346
 347   /// The number of timer frames implemented in the GT Block
 348   UINT32            GTBlockTimerFrameCount;
 349
 350   /// Reference token for the GT Block timer frame list
 351   CM_OBJECT_TOKEN   GTBlockTimerFrameToken;
 352 } CM_ARM_GTBLOCK_INFO;
 353
 354 /** A structure that describes the
 355     SBSA Generic Watchdog information for the Platform.
 356
 357     ID: EArmObjPlatformGenericWatchdogInfo
 358 */
 359 typedef struct CmArmGenericWatchdogInfo {
 360   /// The physical base address of the SBSA Watchdog control frame
 361   UINT64  ControlFrameAddress;
 362
 363   /// The physical base address of the SBSA Watchdog refresh frame
 364   UINT64  RefreshFrameAddress;
 365
 366   /// The watchdog interrupt
 367   UINT32  TimerGSIV;
 368
 369   /** The flags for the watchdog as described by the SBSA watchdog
 370       structure in the ACPI specification.
 371   */
 372   UINT32  Flags;
 373 } CM_ARM_GENERIC_WATCHDOG_INFO;
 374
 375 /** A structure that describes the
 376     PCI Configuration Space information for the Platform.
 377
 378     ID: EArmObjPciConfigSpaceInfo
 379 */
 380 typedef struct CmArmPciConfigSpaceInfo {
 381   /// The physical base address for the PCI segment
 382   UINT64  BaseAddress;
 383
 384   /// The PCI segment group number
 385   UINT16  PciSegmentGroupNumber;
 386
 387   /// The start bus number
 388   UINT8   StartBusNumber;
 389
 390   /// The end bus number
 391   UINT8   EndBusNumber;
 392 } CM_ARM_PCI_CONFIG_SPACE_INFO;
 393
 394 /** A structure that describes the
 395     Hypervisor Vendor ID information for the Platform.
 396
 397     ID: EArmObjHypervisorVendorIdentity
 398 */
 399 typedef struct CmArmHypervisorVendorId {
 400   /// The hypervisor Vendor ID
 401   UINT64  HypervisorVendorId;
 402 } CM_ARM_HYPERVISOR_VENDOR_ID;
 403
 404 /** A structure that describes the
 405     Fixed feature flags for the Platform.
 406
 407     ID: EArmObjFixedFeatureFlags
 408 */
 409 typedef struct CmArmFixedFeatureFlags {
 410   /// The Fixed feature flags
 411   UINT32  Flags;
 412 } CM_ARM_FIXED_FEATURE_FLAGS;
 413
 414 /** A structure that describes the
 415     ITS Group node for the Platform.
 416
 417     ID: EArmObjItsGroup
 418 */
 419 typedef struct CmArmItsGroupNode {
 420   /// An unique token used to identify this object
 421   CM_OBJECT_TOKEN   Token;
 422   /// The number of ITS identifiers in the ITS node
 423   UINT32            ItsIdCount;
 424   /// Reference token for the ITS identifier array
 425   CM_OBJECT_TOKEN   ItsIdToken;
 426 } CM_ARM_ITS_GROUP_NODE;
 427
 428 /** A structure that describes the
 429     GIC ITS Identifiers for an ITS Group node.
 430
 431     ID: EArmObjGicItsIdentifierArray
 432 */
 433 typedef struct CmArmGicItsIdentifier {
 434   /// The ITS Identifier
 435   UINT32  ItsId;
 436 } CM_ARM_ITS_IDENTIFIER;
 437
 438 /** A structure that describes the
 439     Named component node for the Platform.
 440
 441     ID: EArmObjNamedComponent
 442 */
 443 typedef struct CmArmNamedComponentNode {
 444   /// An unique token used to identify this object
 445   CM_OBJECT_TOKEN   Token;
 446   /// Number of ID mappings
 447   UINT32            IdMappingCount;
 448   /// Reference token for the ID mapping array
 449   CM_OBJECT_TOKEN   IdMappingToken;
 450
 451   /// Flags for the named component
 452   UINT32            Flags;
 453
 454   /// Memory access properties : Cache coherent attributes
 455   UINT32            CacheCoherent;
 456   /// Memory access properties : Allocation hints
 457   UINT8             AllocationHints;
 458   /// Memory access properties : Memory access flags
 459   UINT8             MemoryAccessFlags;
 460
 461   /// Memory access properties : Address size limit
 462   UINT8             AddressSizeLimit;
 463   /** ASCII Null terminated string with the full path to
 464       the entry in the namespace for this object.
 465   */
 466   CHAR8*            ObjectName;
 467 } CM_ARM_NAMED_COMPONENT_NODE;
 468
 469 /** A structure that describes the
 470     Root complex node for the Platform.
 471
 472     ID: EArmObjRootComplex
 473 */
 474 typedef struct CmArmRootComplexNode {
 475   /// An unique token used to identify this object
 476   CM_OBJECT_TOKEN   Token;
 477   /// Number of ID mappings
 478   UINT32            IdMappingCount;
 479   /// Reference token for the ID mapping array
 480   CM_OBJECT_TOKEN   IdMappingToken;
 481
 482   /// Memory access properties : Cache coherent attributes
 483   UINT32            CacheCoherent;
 484   /// Memory access properties : Allocation hints
 485   UINT8             AllocationHints;
 486   /// Memory access properties : Memory access flags
 487   UINT8             MemoryAccessFlags;
 488
 489   /// ATS attributes
 490   UINT32            AtsAttribute;
 491   /// PCI segment number
 492   UINT32            PciSegmentNumber;
 493   /// Memory address size limit
 494   UINT8             MemoryAddressSize;
 495 } CM_ARM_ROOT_COMPLEX_NODE;
 496
 497 /** A structure that describes the
 498     SMMUv1 or SMMUv2 node for the Platform.
 499
 500     ID: EArmObjSmmuV1SmmuV2
 501 */
 502 typedef struct CmArmSmmuV1SmmuV2Node {
 503   /// An unique token used to identify this object
 504   CM_OBJECT_TOKEN   Token;
 505   /// Number of ID mappings
 506   UINT32            IdMappingCount;
 507   /// Reference token for the ID mapping array
 508   CM_OBJECT_TOKEN   IdMappingToken;
 509
 510   /// SMMU Base Address
 511   UINT64            BaseAddress;
 512   /// Length of the memory range covered by the SMMU
 513   UINT64            Span;
 514   /// SMMU Model
 515   UINT32            Model;
 516   /// SMMU flags
 517   UINT32            Flags;
 518
 519   /// Number of context interrupts
 520   UINT32            ContextInterruptCount;
 521   /// Reference token for the context interrupt array
 522   CM_OBJECT_TOKEN   ContextInterruptToken;
 523
 524   /// Number of PMU interrupts
 525   UINT32            PmuInterruptCount;
 526   /// Reference token for the PMU interrupt array
 527   CM_OBJECT_TOKEN   PmuInterruptToken;
 528
 529   /// GSIV of the SMMU_NSgIrpt interrupt
 530   UINT32            SMMU_NSgIrpt;
 531   /// SMMU_NSgIrpt interrupt flags
 532   UINT32            SMMU_NSgIrptFlags;
 533   /// GSIV of the SMMU_NSgCfgIrpt interrupt
 534   UINT32            SMMU_NSgCfgIrpt;
 535   /// SMMU_NSgCfgIrpt interrupt flags
 536   UINT32            SMMU_NSgCfgIrptFlags;
 537 } CM_ARM_SMMUV1_SMMUV2_NODE;
 538
 539 /** A structure that describes the
 540     SMMUv3 node for the Platform.
 541
 542     ID: EArmObjSmmuV3
 543 */
 544 typedef struct CmArmSmmuV3Node {
 545   /// An unique token used to identify this object
 546   CM_OBJECT_TOKEN   Token;
 547   /// Number of ID mappings
 548   UINT32            IdMappingCount;
 549   /// Reference token for the ID mapping array
 550   CM_OBJECT_TOKEN   IdMappingToken;
 551
 552   /// SMMU Base Address
 553   UINT64    BaseAddress;
 554   /// SMMU flags
 555   UINT32            Flags;
 556   /// VATOS address
 557   UINT64            VatosAddress;
 558   /// Model
 559   UINT32            Model;
 560   /// GSIV of the Event interrupt if SPI based
 561   UINT32            EventInterrupt;
 562   /// PRI Interrupt if SPI based
 563   UINT32            PriInterrupt;
 564   /// GERR interrupt if GSIV based
 565   UINT32            GerrInterrupt;
 566   /// Sync interrupt if GSIV based
 567   UINT32            SyncInterrupt;
 568
 569   /// Proximity domain flag
 570   UINT32            ProximityDomain;
 571   /// Index into the array of ID mapping
 572   UINT32            DeviceIdMappingIndex;
 573 } CM_ARM_SMMUV3_NODE;
 574
 575 /** A structure that describes the
 576     PMCG node for the Platform.
 577
 578     ID: EArmObjPmcg
 579 */
 580 typedef struct CmArmPmcgNode {
 581   /// An unique token used to identify this object
 582   CM_OBJECT_TOKEN   Token;
 583   /// Number of ID mappings
 584   UINT32            IdMappingCount;
 585   /// Reference token for the ID mapping array
 586   CM_OBJECT_TOKEN   IdMappingToken;
 587
 588   /// Base Address for performance monitor counter group
 589   UINT64            BaseAddress;
 590   /// GSIV for the Overflow interrupt
 591   UINT32            OverflowInterrupt;
 592   /// Page 1 Base address
 593   UINT64            Page1BaseAddress;
 594
 595   /// Reference token for the IORT node associated with this node
 596   CM_OBJECT_TOKEN   ReferenceToken;
 597 } CM_ARM_PMCG_NODE;
 598
 599 /** A structure that describes the
 600     ID Mappings for the Platform.
 601
 602     ID: EArmObjIdMappingArray
 603 */
 604 typedef struct CmArmIdMapping {
 605   /// Input base
 606   UINT32           InputBase;
 607   /// Number of input IDs
 608   UINT32           NumIds;
 609   /// Output Base
 610   UINT32           OutputBase;
 611   /// Reference token for the output node
 612   CM_OBJECT_TOKEN  OutputReferenceToken;
 613   /// Flags
 614   UINT32    Flags;
 615 } CM_ARM_ID_MAPPING;
 616
 617 /** A structure that describes the
 618     SMMU interrupts for the Platform.
 619
 620     ID: EArmObjSmmuInterruptArray
 621 */
 622 typedef struct CmArmSmmuInterrupt {
 623   /// Interrupt number
 624   UINT32    Interrupt;
 625
 626   /// Flags
 627   UINT32    Flags;
 628 } CM_ARM_SMMU_INTERRUPT;
 629
 630 #pragma pack()
 631
 632 #endif // ARM_NAMESPACE_OBJECTS_H_