DynamicTablesPkg/Include/ArmNameSpaceObjects.h

   1 /** @file
   2
   3   Copyright (c) 2017 - 2020, ARM Limited. All rights reserved.
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7   @par Glossary:
   8     - Cm or CM   - Configuration Manager
   9     - Obj or OBJ - Object
  10     - Std or STD - Standard
  11 **/
  12
  13 #ifndef ARM_NAMESPACE_OBJECTS_H_
  14 #define ARM_NAMESPACE_OBJECTS_H_
  15
  16 #include <StandardNameSpaceObjects.h>
  17
  18 #pragma pack(1)
  19
  20 /** The EARM_OBJECT_ID enum describes the Object IDs
  21     in the ARM Namespace
  22 */
  23 typedef enum ArmObjectID {
  24   EArmObjReserved,                     ///<  0 - Reserved
  25   EArmObjBootArchInfo,                 ///<  1 - Boot Architecture Info
  26   EArmObjCpuInfo,                      ///<  2 - CPU Info
  27   EArmObjPowerManagementProfileInfo,   ///<  3 - Power Management Profile Info
  28   EArmObjGicCInfo,                     ///<  4 - GIC CPU Interface Info
  29   EArmObjGicDInfo,                     ///<  5 - GIC Distributor Info
  30   EArmObjGicMsiFrameInfo,              ///<  6 - GIC MSI Frame Info
  31   EArmObjGicRedistributorInfo,         ///<  7 - GIC Redistributor Info
  32   EArmObjGicItsInfo,                   ///<  8 - GIC ITS Info
  33   EArmObjSerialConsolePortInfo,        ///<  9 - Serial Console Port Info
  34   EArmObjSerialDebugPortInfo,          ///< 10 - Serial Debug Port Info
  35   EArmObjGenericTimerInfo,             ///< 11 - Generic Timer Info
  36   EArmObjPlatformGTBlockInfo,          ///< 12 - Platform GT Block Info
  37   EArmObjGTBlockTimerFrameInfo,        ///< 13 - Generic Timer Block Frame Info
  38   EArmObjPlatformGenericWatchdogInfo,  ///< 14 - Platform Generic Watchdog
  39   EArmObjPciConfigSpaceInfo,           ///< 15 - PCI Configuration Space Info
  40   EArmObjHypervisorVendorIdentity,     ///< 16 - Hypervisor Vendor Id
  41   EArmObjFixedFeatureFlags,            ///< 17 - Fixed feature flags for FADT
  42   EArmObjItsGroup,                     ///< 18 - ITS Group
  43   EArmObjNamedComponent,               ///< 19 - Named Component
  44   EArmObjRootComplex,                  ///< 20 - Root Complex
  45   EArmObjSmmuV1SmmuV2,                 ///< 21 - SMMUv1 or SMMUv2
  46   EArmObjSmmuV3,                       ///< 22 - SMMUv3
  47   EArmObjPmcg,                         ///< 23 - PMCG
  48   EArmObjGicItsIdentifierArray,        ///< 24 - GIC ITS Identifier Array
  49   EArmObjIdMappingArray,               ///< 25 - ID Mapping Array
  50   EArmObjSmmuInterruptArray,           ///< 26 - SMMU Interrupt Array
  51   EArmObjProcHierarchyInfo,            ///< 27 - Processor Hierarchy Info
  52   EArmObjCacheInfo,                    ///< 28 - Cache Info
  53   EArmObjProcNodeIdInfo,               ///< 29 - Processor Node ID Info
  54   EArmObjCmRef,                        ///< 30 - CM Object Reference
  55   EArmObjMemoryAffinityInfo,           ///< 31 - Memory Affinity Info
  56   EArmObjDeviceHandleAcpi,             ///< 32 - Device Handle Acpi
  57   EArmObjDeviceHandlePci,              ///< 33 - Device Handle Pci
  58   EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity
  59   EArmObjMax
  60 } EARM_OBJECT_ID;
  61
  62 /** A structure that describes the
  63     ARM Boot Architecture flags.
  64
  65     ID: EArmObjBootArchInfo
  66 */
  67 typedef struct CmArmBootArchInfo {
  68   /** This is the ARM_BOOT_ARCH flags field of the FADT Table
  69       described in the ACPI Table Specification.
  70   */
  71   UINT16  BootArchFlags;
  72 } CM_ARM_BOOT_ARCH_INFO;
  73
  74 /** A structure that describes the
  75     Power Management Profile Information for the Platform.
  76
  77     ID: EArmObjPowerManagementProfileInfo
  78 */
  79 typedef struct CmArmPowerManagementProfileInfo {
  80   /** This is the Preferred_PM_Profile field of the FADT Table
  81       described in the ACPI Specification
  82   */
  83   UINT8  PowerManagementProfile;
  84 } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;
  85
  86 /** A structure that describes the
  87     GIC CPU Interface for the Platform.
  88
  89     ID: EArmObjGicCInfo
  90 */
  91 typedef struct CmArmGicCInfo {
  92   /// The GIC CPU Interface number.
  93   UINT32  CPUInterfaceNumber;
  94
  95   /** The ACPI Processor UID. This must match the
  96       _UID of the CPU Device object information described
  97       in the DSDT/SSDT for the CPU.
  98   */
  99   UINT32  AcpiProcessorUid;
 100
 101   /** The flags field as described by the GICC structure
 102       in the ACPI Specification.
 103   */
 104   UINT32  Flags;
 105
 106   /** The parking protocol version field as described by
 107     the GICC structure in the ACPI Specification.
 108   */
 109   UINT32  ParkingProtocolVersion;
 110
 111   /** The Performance Interrupt field as described by
 112       the GICC structure in the ACPI Specification.
 113   */
 114   UINT32  PerformanceInterruptGsiv;
 115
 116   /** The CPU Parked address field as described by
 117       the GICC structure in the ACPI Specification.
 118   */
 119   UINT64  ParkedAddress;
 120
 121   /** The base address for the GIC CPU Interface
 122       as described by the GICC structure in the
 123       ACPI Specification.
 124   */
 125   UINT64  PhysicalBaseAddress;
 126
 127   /** The base address for GICV interface
 128       as described by the GICC structure in the
 129       ACPI Specification.
 130   */
 131   UINT64  GICV;
 132
 133   /** The base address for GICH interface
 134       as described by the GICC structure in the
 135       ACPI Specification.
 136   */
 137   UINT64  GICH;
 138
 139   /** The GICV maintenance interrupt
 140       as described by the GICC structure in the
 141       ACPI Specification.
 142   */
 143   UINT32  VGICMaintenanceInterrupt;
 144
 145   /** The base address for GICR interface
 146       as described by the GICC structure in the
 147       ACPI Specification.
 148   */
 149   UINT64  GICRBaseAddress;
 150
 151   /** The MPIDR for the CPU
 152       as described by the GICC structure in the
 153       ACPI Specification.
 154   */
 155   UINT64  MPIDR;
 156
 157   /** The Processor Power Efficiency class
 158       as described by the GICC structure in the
 159       ACPI Specification.
 160   */
 161   UINT8   ProcessorPowerEfficiencyClass;
 162
 163   /** Statistical Profiling Extension buffer overflow GSIV. Zero if
 164       unsupported by this processor. This field was introduced in
 165       ACPI 6.3 (MADT revision 5) and is therefore ignored when
 166       generating MADT revision 4 or lower.
 167   */
 168   UINT16  SpeOverflowInterrupt;
 169
 170   /** The proximity domain to which the logical processor belongs.
 171       This field is used to populate the GICC affinity structure
 172       in the SRAT table.
 173   */
 174   UINT32  ProximityDomain;
 175
 176   /** The clock domain to which the logical processor belongs.
 177       This field is used to populate the GICC affinity structure
 178       in the SRAT table.
 179   */
 180   UINT32  ClockDomain;
 181
 182   /** The GICC Affinity flags field as described by the GICC Affinity structure
 183       in the SRAT table.
 184   */
 185   UINT32  AffinityFlags;
 186 } CM_ARM_GICC_INFO;
 187
 188 /** A structure that describes the
 189     GIC Distributor information for the Platform.
 190
 191     ID: EArmObjGicDInfo
 192 */
 193 typedef struct CmArmGicDInfo {
 194   /// The Physical Base address for the GIC Distributor.
 195   UINT64  PhysicalBaseAddress;
 196
 197   /** The global system interrupt
 198       number where this GIC Distributor's
 199       interrupt inputs start.
 200   */
 201   UINT32  SystemVectorBase;
 202
 203   /** The GIC version as described
 204       by the GICD structure in the
 205       ACPI Specification.
 206   */
 207   UINT8   GicVersion;
 208 } CM_ARM_GICD_INFO;
 209
 210 /** A structure that describes the
 211     GIC MSI Frame information for the Platform.
 212
 213     ID: EArmObjGicMsiFrameInfo
 214 */
 215 typedef struct CmArmGicMsiFrameInfo {
 216   /// The GIC MSI Frame ID
 217   UINT32  GicMsiFrameId;
 218
 219   /// The Physical base address for the MSI Frame
 220   UINT64  PhysicalBaseAddress;
 221
 222   /** The GIC MSI Frame flags
 223       as described by the GIC MSI frame
 224       structure in the ACPI Specification.
 225   */
 226   UINT32  Flags;
 227
 228   /// SPI Count used by this frame
 229   UINT16  SPICount;
 230
 231   /// SPI Base used by this frame
 232   UINT16  SPIBase;
 233 } CM_ARM_GIC_MSI_FRAME_INFO;
 234
 235 /** A structure that describes the
 236     GIC Redistributor information for the Platform.
 237
 238     ID: EArmObjGicRedistributorInfo
 239 */
 240 typedef struct CmArmGicRedistInfo {
 241   /** The physical address of a page range
 242       containing all GIC Redistributors.
 243   */
 244   UINT64  DiscoveryRangeBaseAddress;
 245
 246   /// Length of the GIC Redistributor Discovery page range
 247   UINT32  DiscoveryRangeLength;
 248 } CM_ARM_GIC_REDIST_INFO;
 249
 250 /** A structure that describes the
 251     GIC Interrupt Translation Service information for the Platform.
 252
 253     ID: EArmObjGicItsInfo
 254 */
 255 typedef struct CmArmGicItsInfo {
 256   /// The GIC ITS ID
 257   UINT32  GicItsId;
 258
 259   /// The physical address for the Interrupt Translation Service
 260   UINT64  PhysicalBaseAddress;
 261
 262   /** The proximity domain to which the logical processor belongs.
 263       This field is used to populate the GIC ITS affinity structure
 264       in the SRAT table.
 265   */
 266   UINT32  ProximityDomain;
 267 } CM_ARM_GIC_ITS_INFO;
 268
 269 /** A structure that describes the
 270     Serial Port information for the Platform.
 271
 272     ID: EArmObjSerialConsolePortInfo or
 273         EArmObjSerialDebugPortInfo
 274 */
 275 typedef struct CmArmSerialPortInfo {
 276   /// The physical base address for the serial port
 277   UINT64  BaseAddress;
 278
 279   /// The serial port interrupt
 280   UINT32  Interrupt;
 281
 282   /// The serial port baud rate
 283   UINT64  BaudRate;
 284
 285   /// The serial port clock
 286   UINT32  Clock;
 287
 288   /// Serial Port subtype
 289   UINT16  PortSubtype;
 290 } CM_ARM_SERIAL_PORT_INFO;
 291
 292 /** A structure that describes the
 293     Generic Timer information for the Platform.
 294
 295     ID: EArmObjGenericTimerInfo
 296 */
 297 typedef struct CmArmGenericTimerInfo {
 298   /// The physical base address for the counter control frame
 299   UINT64  CounterControlBaseAddress;
 300
 301   /// The physical base address for the counter read frame
 302   UINT64  CounterReadBaseAddress;
 303
 304   /// The secure PL1 timer interrupt
 305   UINT32  SecurePL1TimerGSIV;
 306
 307   /// The secure PL1 timer flags
 308   UINT32  SecurePL1TimerFlags;
 309
 310   /// The non-secure PL1 timer interrupt
 311   UINT32  NonSecurePL1TimerGSIV;
 312
 313   /// The non-secure PL1 timer flags
 314   UINT32  NonSecurePL1TimerFlags;
 315
 316   /// The virtual timer interrupt
 317   UINT32  VirtualTimerGSIV;
 318
 319   /// The virtual timer flags
 320   UINT32  VirtualTimerFlags;
 321
 322   /// The non-secure PL2 timer interrupt
 323   UINT32  NonSecurePL2TimerGSIV;
 324
 325   /// The non-secure PL2 timer flags
 326   UINT32  NonSecurePL2TimerFlags;
 327
 328   /// GSIV for the virtual EL2 timer
 329   UINT32  VirtualPL2TimerGSIV;
 330
 331   /// Flags for the virtual EL2 timer
 332   UINT32  VirtualPL2TimerFlags;
 333 } CM_ARM_GENERIC_TIMER_INFO;
 334
 335 /** A structure that describes the
 336     Platform Generic Block Timer Frame information for the Platform.
 337
 338     ID: EArmObjGTBlockTimerFrameInfo
 339 */
 340 typedef struct CmArmGTBlockTimerFrameInfo {
 341   /// The Generic Timer frame number
 342   UINT8   FrameNumber;
 343
 344   /// The physical base address for the CntBase block
 345   UINT64  PhysicalAddressCntBase;
 346
 347   /// The physical base address for the CntEL0Base block
 348   UINT64  PhysicalAddressCntEL0Base;
 349
 350   /// The physical timer interrupt
 351   UINT32  PhysicalTimerGSIV;
 352
 353   /** The physical timer flags as described by the GT Block
 354       Timer frame Structure in the ACPI Specification.
 355   */
 356   UINT32  PhysicalTimerFlags;
 357
 358   /// The virtual timer interrupt
 359   UINT32  VirtualTimerGSIV;
 360
 361   /** The virtual timer flags as described by the GT Block
 362       Timer frame Structure in the ACPI Specification.
 363   */
 364   UINT32  VirtualTimerFlags;
 365
 366   /** The common timer flags as described by the GT Block
 367       Timer frame Structure in the ACPI Specification.
 368   */
 369   UINT32  CommonFlags;
 370 } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;
 371
 372 /** A structure that describes the
 373     Platform Generic Block Timer information for the Platform.
 374
 375     ID: EArmObjPlatformGTBlockInfo
 376 */
 377 typedef struct CmArmGTBlockInfo {
 378   /// The physical base address for the GT Block Timer structure
 379   UINT64            GTBlockPhysicalAddress;
 380
 381   /// The number of timer frames implemented in the GT Block
 382   UINT32            GTBlockTimerFrameCount;
 383
 384   /// Reference token for the GT Block timer frame list
 385   CM_OBJECT_TOKEN   GTBlockTimerFrameToken;
 386 } CM_ARM_GTBLOCK_INFO;
 387
 388 /** A structure that describes the
 389     SBSA Generic Watchdog information for the Platform.
 390
 391     ID: EArmObjPlatformGenericWatchdogInfo
 392 */
 393 typedef struct CmArmGenericWatchdogInfo {
 394   /// The physical base address of the SBSA Watchdog control frame
 395   UINT64  ControlFrameAddress;
 396
 397   /// The physical base address of the SBSA Watchdog refresh frame
 398   UINT64  RefreshFrameAddress;
 399
 400   /// The watchdog interrupt
 401   UINT32  TimerGSIV;
 402
 403   /** The flags for the watchdog as described by the SBSA watchdog
 404       structure in the ACPI specification.
 405   */
 406   UINT32  Flags;
 407 } CM_ARM_GENERIC_WATCHDOG_INFO;
 408
 409 /** A structure that describes the
 410     PCI Configuration Space information for the Platform.
 411
 412     ID: EArmObjPciConfigSpaceInfo
 413 */
 414 typedef struct CmArmPciConfigSpaceInfo {
 415   /// The physical base address for the PCI segment
 416   UINT64  BaseAddress;
 417
 418   /// The PCI segment group number
 419   UINT16  PciSegmentGroupNumber;
 420
 421   /// The start bus number
 422   UINT8   StartBusNumber;
 423
 424   /// The end bus number
 425   UINT8   EndBusNumber;
 426 } CM_ARM_PCI_CONFIG_SPACE_INFO;
 427
 428 /** A structure that describes the
 429     Hypervisor Vendor ID information for the Platform.
 430
 431     ID: EArmObjHypervisorVendorIdentity
 432 */
 433 typedef struct CmArmHypervisorVendorId {
 434   /// The hypervisor Vendor ID
 435   UINT64  HypervisorVendorId;
 436 } CM_ARM_HYPERVISOR_VENDOR_ID;
 437
 438 /** A structure that describes the
 439     Fixed feature flags for the Platform.
 440
 441     ID: EArmObjFixedFeatureFlags
 442 */
 443 typedef struct CmArmFixedFeatureFlags {
 444   /// The Fixed feature flags
 445   UINT32  Flags;
 446 } CM_ARM_FIXED_FEATURE_FLAGS;
 447
 448 /** A structure that describes the
 449     ITS Group node for the Platform.
 450
 451     ID: EArmObjItsGroup
 452 */
 453 typedef struct CmArmItsGroupNode {
 454   /// An unique token used to identify this object
 455   CM_OBJECT_TOKEN   Token;
 456   /// The number of ITS identifiers in the ITS node
 457   UINT32            ItsIdCount;
 458   /// Reference token for the ITS identifier array
 459   CM_OBJECT_TOKEN   ItsIdToken;
 460 } CM_ARM_ITS_GROUP_NODE;
 461
 462 /** A structure that describes the
 463     GIC ITS Identifiers for an ITS Group node.
 464
 465     ID: EArmObjGicItsIdentifierArray
 466 */
 467 typedef struct CmArmGicItsIdentifier {
 468   /// The ITS Identifier
 469   UINT32  ItsId;
 470 } CM_ARM_ITS_IDENTIFIER;
 471
 472 /** A structure that describes the
 473     Named component node for the Platform.
 474
 475     ID: EArmObjNamedComponent
 476 */
 477 typedef struct CmArmNamedComponentNode {
 478   /// An unique token used to identify this object
 479   CM_OBJECT_TOKEN   Token;
 480   /// Number of ID mappings
 481   UINT32            IdMappingCount;
 482   /// Reference token for the ID mapping array
 483   CM_OBJECT_TOKEN   IdMappingToken;
 484
 485   /// Flags for the named component
 486   UINT32            Flags;
 487
 488   /// Memory access properties : Cache coherent attributes
 489   UINT32            CacheCoherent;
 490   /// Memory access properties : Allocation hints
 491   UINT8             AllocationHints;
 492   /// Memory access properties : Memory access flags
 493   UINT8             MemoryAccessFlags;
 494
 495   /// Memory access properties : Address size limit
 496   UINT8             AddressSizeLimit;
 497   /** ASCII Null terminated string with the full path to
 498       the entry in the namespace for this object.
 499   */
 500   CHAR8*            ObjectName;
 501 } CM_ARM_NAMED_COMPONENT_NODE;
 502
 503 /** A structure that describes the
 504     Root complex node for the Platform.
 505
 506     ID: EArmObjRootComplex
 507 */
 508 typedef struct CmArmRootComplexNode {
 509   /// An unique token used to identify this object
 510   CM_OBJECT_TOKEN   Token;
 511   /// Number of ID mappings
 512   UINT32            IdMappingCount;
 513   /// Reference token for the ID mapping array
 514   CM_OBJECT_TOKEN   IdMappingToken;
 515
 516   /// Memory access properties : Cache coherent attributes
 517   UINT32            CacheCoherent;
 518   /// Memory access properties : Allocation hints
 519   UINT8             AllocationHints;
 520   /// Memory access properties : Memory access flags
 521   UINT8             MemoryAccessFlags;
 522
 523   /// ATS attributes
 524   UINT32            AtsAttribute;
 525   /// PCI segment number
 526   UINT32            PciSegmentNumber;
 527   /// Memory address size limit
 528   UINT8             MemoryAddressSize;
 529 } CM_ARM_ROOT_COMPLEX_NODE;
 530
 531 /** A structure that describes the
 532     SMMUv1 or SMMUv2 node for the Platform.
 533
 534     ID: EArmObjSmmuV1SmmuV2
 535 */
 536 typedef struct CmArmSmmuV1SmmuV2Node {
 537   /// An unique token used to identify this object
 538   CM_OBJECT_TOKEN   Token;
 539   /// Number of ID mappings
 540   UINT32            IdMappingCount;
 541   /// Reference token for the ID mapping array
 542   CM_OBJECT_TOKEN   IdMappingToken;
 543
 544   /// SMMU Base Address
 545   UINT64            BaseAddress;
 546   /// Length of the memory range covered by the SMMU
 547   UINT64            Span;
 548   /// SMMU Model
 549   UINT32            Model;
 550   /// SMMU flags
 551   UINT32            Flags;
 552
 553   /// Number of context interrupts
 554   UINT32            ContextInterruptCount;
 555   /// Reference token for the context interrupt array
 556   CM_OBJECT_TOKEN   ContextInterruptToken;
 557
 558   /// Number of PMU interrupts
 559   UINT32            PmuInterruptCount;
 560   /// Reference token for the PMU interrupt array
 561   CM_OBJECT_TOKEN   PmuInterruptToken;
 562
 563   /// GSIV of the SMMU_NSgIrpt interrupt
 564   UINT32            SMMU_NSgIrpt;
 565   /// SMMU_NSgIrpt interrupt flags
 566   UINT32            SMMU_NSgIrptFlags;
 567   /// GSIV of the SMMU_NSgCfgIrpt interrupt
 568   UINT32            SMMU_NSgCfgIrpt;
 569   /// SMMU_NSgCfgIrpt interrupt flags
 570   UINT32            SMMU_NSgCfgIrptFlags;
 571 } CM_ARM_SMMUV1_SMMUV2_NODE;
 572
 573 /** A structure that describes the
 574     SMMUv3 node for the Platform.
 575
 576     ID: EArmObjSmmuV3
 577 */
 578 typedef struct CmArmSmmuV3Node {
 579   /// An unique token used to identify this object
 580   CM_OBJECT_TOKEN   Token;
 581   /// Number of ID mappings
 582   UINT32            IdMappingCount;
 583   /// Reference token for the ID mapping array
 584   CM_OBJECT_TOKEN   IdMappingToken;
 585
 586   /// SMMU Base Address
 587   UINT64    BaseAddress;
 588   /// SMMU flags
 589   UINT32            Flags;
 590   /// VATOS address
 591   UINT64            VatosAddress;
 592   /// Model
 593   UINT32            Model;
 594   /// GSIV of the Event interrupt if SPI based
 595   UINT32            EventInterrupt;
 596   /// PRI Interrupt if SPI based
 597   UINT32            PriInterrupt;
 598   /// GERR interrupt if GSIV based
 599   UINT32            GerrInterrupt;
 600   /// Sync interrupt if GSIV based
 601   UINT32            SyncInterrupt;
 602
 603   /// Proximity domain flag
 604   UINT32            ProximityDomain;
 605   /// Index into the array of ID mapping
 606   UINT32            DeviceIdMappingIndex;
 607 } CM_ARM_SMMUV3_NODE;
 608
 609 /** A structure that describes the
 610     PMCG node for the Platform.
 611
 612     ID: EArmObjPmcg
 613 */
 614 typedef struct CmArmPmcgNode {
 615   /// An unique token used to identify this object
 616   CM_OBJECT_TOKEN   Token;
 617   /// Number of ID mappings
 618   UINT32            IdMappingCount;
 619   /// Reference token for the ID mapping array
 620   CM_OBJECT_TOKEN   IdMappingToken;
 621
 622   /// Base Address for performance monitor counter group
 623   UINT64            BaseAddress;
 624   /// GSIV for the Overflow interrupt
 625   UINT32            OverflowInterrupt;
 626   /// Page 1 Base address
 627   UINT64            Page1BaseAddress;
 628
 629   /// Reference token for the IORT node associated with this node
 630   CM_OBJECT_TOKEN   ReferenceToken;
 631 } CM_ARM_PMCG_NODE;
 632
 633 /** A structure that describes the
 634     ID Mappings for the Platform.
 635
 636     ID: EArmObjIdMappingArray
 637 */
 638 typedef struct CmArmIdMapping {
 639   /// Input base
 640   UINT32           InputBase;
 641   /// Number of input IDs
 642   UINT32           NumIds;
 643   /// Output Base
 644   UINT32           OutputBase;
 645   /// Reference token for the output node
 646   CM_OBJECT_TOKEN  OutputReferenceToken;
 647   /// Flags
 648   UINT32    Flags;
 649 } CM_ARM_ID_MAPPING;
 650
 651 /** A structure that describes the
 652     SMMU interrupts for the Platform.
 653
 654     ID: EArmObjSmmuInterruptArray
 655 */
 656 typedef struct CmArmSmmuInterrupt {
 657   /// Interrupt number
 658   UINT32    Interrupt;
 659
 660   /// Flags
 661   UINT32    Flags;
 662 } CM_ARM_SMMU_INTERRUPT;
 663
 664 /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT
 665
 666     ID: EArmObjProcHierarchyInfo
 667 */
 668 typedef struct CmArmProcHierarchyInfo {
 669   /// A unique token used to identify this object
 670   CM_OBJECT_TOKEN   Token;
 671   /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)
 672   UINT32            Flags;
 673   /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor
 674   /// topology. A value of CM_NULL_TOKEN means this node has no parent.
 675   CM_OBJECT_TOKEN   ParentToken;
 676   /// Token of the associated CM_ARM_GICC_INFO object which has the
 677   /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this
 678   /// node represents a group of associated processors and it does not have an
 679   /// associated GIC CPU interface.
 680   CM_OBJECT_TOKEN   GicCToken;
 681   /// Number of resources private to this Node
 682   UINT32            NoOfPrivateResources;
 683   /// Token of the array which contains references to the resources private to
 684   /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if
 685   /// the NoOfPrivateResources is 0, in which case it is recommended to set
 686   /// this field to CM_NULL_TOKEN.
 687   CM_OBJECT_TOKEN   PrivateResourcesArrayToken;
 688 } CM_ARM_PROC_HIERARCHY_INFO;
 689
 690 /** A structure that describes the Cache Type Structure (Type 1) in PPTT
 691
 692     ID: EArmObjCacheInfo
 693 */
 694 typedef struct CmArmCacheInfo {
 695   /// A unique token used to identify this object
 696   CM_OBJECT_TOKEN   Token;
 697   /// Reference token for the next level of cache that is private to the same
 698   /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this
 699   /// entry represents the last cache level appropriate to the processor
 700   /// hierarchy node structures using this entry.
 701   CM_OBJECT_TOKEN   NextLevelOfCacheToken;
 702   /// Size of the cache in bytes
 703   UINT32            Size;
 704   /// Number of sets in the cache
 705   UINT32            NumberOfSets;
 706   /// Integer number of ways. The maximum associativity supported by
 707   /// ACPI Cache type structure is limited to MAX_UINT8. However,
 708   /// the maximum number of ways supported by the architecture is
 709   /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field
 710   /// is 32-bit wide.
 711   UINT32            Associativity;
 712   /// Cache attributes (ACPI 6.3 - January 2019, PPTT, Table 5-156)
 713   UINT8             Attributes;
 714   /// Line size in bytes
 715   UINT16            LineSize;
 716 } CM_ARM_CACHE_INFO;
 717
 718 /** A structure that describes the ID Structure (Type 2) in PPTT
 719
 720     ID: EArmObjProcNodeIdInfo
 721 */
 722 typedef struct CmArmProcNodeIdInfo {
 723   /// A unique token used to identify this object
 724   CM_OBJECT_TOKEN   Token;
 725   // Vendor ID (as described in ACPI ID registry)
 726   UINT32            VendorId;
 727   /// First level unique node ID
 728   UINT64            Level1Id;
 729   /// Second level unique node ID
 730   UINT64            Level2Id;
 731   /// Major revision of the node
 732   UINT16            MajorRev;
 733   /// Minor revision of the node
 734   UINT16            MinorRev;
 735   /// Spin revision of the node
 736   UINT16            SpinRev;
 737 } CM_ARM_PROC_NODE_ID_INFO;
 738
 739 /** A structure that describes a reference to another Configuration Manager
 740     object.
 741
 742     This is useful for creating an array of reference tokens. The framework
 743     can then query the configuration manager for these arrays using the
 744     object ID EArmObjCmRef.
 745
 746     This can be used is to represent one-to-many relationships between objects.
 747
 748     ID: EArmObjCmRef
 749 */
 750 typedef struct CmArmObjRef {
 751   /// Token of the CM object being referenced
 752   CM_OBJECT_TOKEN   ReferenceToken;
 753 } CM_ARM_OBJ_REF;
 754
 755 /** A structure that describes the Memory Affinity Structure (Type 1) in SRAT
 756
 757     ID: EArmObjMemoryAffinityInfo
 758 */
 759 typedef struct CmArmMemoryAffinityInfo {
 760   /// The proximity domain to which the "range of memory" belongs.
 761   UINT32            ProximityDomain;
 762
 763   /// Base Address
 764   UINT64            BaseAddress;
 765
 766   /// Length
 767   UINT64            Length;
 768
 769   /// Flags
 770   UINT32            Flags;
 771 } CM_ARM_MEMORY_AFFINITY_INFO;
 772
 773 /** A structure that describes the ACPI Device Handle (Type 0) in the
 774     Generic Initiator Affinity structure in SRAT
 775
 776     ID: EArmObjDeviceHandleAcpi
 777 */
 778 typedef struct CmArmDeviceHandleAcpi {
 779   /// Hardware ID
 780   UINT64  Hid;
 781
 782   /// Unique Id
 783   UINT32  Uid;
 784 } CM_ARM_DEVICE_HANDLE_ACPI;
 785
 786 /** A structure that describes the PCI Device Handle (Type 1) in the
 787     Generic Initiator Affinity structure in SRAT
 788
 789     ID: EArmObjDeviceHandlePci
 790 */
 791 typedef struct CmArmDeviceHandlePci {
 792   /// PCI Segment Number
 793   UINT16  SegmentNumber;
 794
 795   /// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)
 796   UINT8  BusNumber;
 797
 798   /// PCI Device Number - Max 32 devices (Bits 7:3 of BDF)
 799   UINT8   DeviceNumber;
 800
 801   /// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)
 802   UINT8   FunctionNumber;
 803 } CM_ARM_DEVICE_HANDLE_PCI;
 804
 805 /** A structure that describes the Generic Initiator Affinity structure in SRAT
 806
 807     ID: EArmObjGenericInitiatorAffinityInfo
 808 */
 809 typedef struct CmArmGenericInitiatorAffinityInfo {
 810   /// The proximity domain to which the generic initiator belongs.
 811   UINT32            ProximityDomain;
 812
 813   /// Flags
 814   UINT32            Flags;
 815
 816   /// Device Handle Type
 817   UINT8             DeviceHandleType;
 818
 819   /// Reference Token for the Device Handle
 820   CM_OBJECT_TOKEN   DeviceHandleToken;
 821 } CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO;
 822
 823 #pragma pack()
 824
 825 #endif // ARM_NAMESPACE_OBJECTS_H_