EdkCompatibilityPkg/Compatibility/SmmBaseHelper/CpuSaveState.h

   1 /** @file
   2   Definitions for SMM CPU Save State per Framework SMM CIS 0.91 spec.
   3
   4   Copyright (c) 2009, Intel Corporation
   5   All rights reserved. This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _CPU_SAVE_STATE_H_
  16 #define _CPU_SAVE_STATE_H_
  17
  18 typedef unsigned char               ASM_UINT8;
  19 typedef ASM_UINT8                   ASM_BOOL;
  20 typedef unsigned short              ASM_UINT16;
  21 typedef unsigned long               ASM_UINT32;
  22
  23 typedef UINT64                      ASM_UINT64;
  24
  25 #ifndef __GNUC__
  26 #pragma pack (push)
  27 #pragma pack (1)
  28 #endif
  29
  30 typedef struct _EFI_SMM_CPU_STATE32 {
  31   ASM_UINT8                         Reserved1[0xf8];        // fe00h
  32   ASM_UINT32                        SMBASE;                 // fef8h
  33   ASM_UINT32                        SMMRevId;               // fefch
  34   ASM_UINT16                        IORestart;              // ff00h
  35   ASM_UINT16                        AutoHALTRestart;        // ff02h
  36   ASM_UINT32                        IEDBASE;                // ff04h
  37   ASM_UINT8                         Reserved2[0x98];        // ff08h
  38   ASM_UINT32                        IOMemAddr;              // ffa0h
  39   ASM_UINT32                        IOMisc;                 // ffa4h
  40   ASM_UINT32                        _ES;
  41   ASM_UINT32                        _CS;
  42   ASM_UINT32                        _SS;
  43   ASM_UINT32                        _DS;
  44   ASM_UINT32                        _FS;
  45   ASM_UINT32                        _GS;
  46   ASM_UINT32                        _LDTBase;
  47   ASM_UINT32                        _TR;
  48   ASM_UINT32                        _DR7;
  49   ASM_UINT32                        _DR6;
  50   ASM_UINT32                        _EAX;
  51   ASM_UINT32                        _ECX;
  52   ASM_UINT32                        _EDX;
  53   ASM_UINT32                        _EBX;
  54   ASM_UINT32                        _ESP;
  55   ASM_UINT32                        _EBP;
  56   ASM_UINT32                        _ESI;
  57   ASM_UINT32                        _EDI;
  58   ASM_UINT32                        _EIP;
  59   ASM_UINT32                        _EFLAGS;
  60   ASM_UINT32                        _CR3;
  61   ASM_UINT32                        _CR0;
  62 } EFI_SMM_CPU_STATE32;
  63
  64 typedef struct _EFI_SMM_CPU_STATE64 {
  65   ASM_UINT8                         Reserved1[0x1d0];       // fc00h
  66   ASM_UINT32                        GdtBaseHiDword;         // fdd0h
  67   ASM_UINT32                        LdtBaseHiDword;         // fdd4h
  68   ASM_UINT32                        IdtBaseHiDword;         // fdd8h
  69   ASM_UINT8                         Reserved2[0xc];         // fddch
  70   ASM_UINT64                        IO_EIP;                 // fde8h
  71   ASM_UINT8                         Reserved3[0x50];        // fdf0h
  72   ASM_UINT32                        _CR4;                   // fe40h
  73   ASM_UINT8                         Reserved4[0x48];        // fe44h
  74   ASM_UINT32                        GdtBaseLoDword;         // fe8ch
  75   ASM_UINT32                        GdtLimit;               // fe90h
  76   ASM_UINT32                        IdtBaseLoDword;         // fe94h
  77   ASM_UINT32                        IdtLimit;               // fe98h
  78   ASM_UINT32                        LdtBaseLoDword;         // fe9ch
  79   ASM_UINT32                        LdtLimit;               // fea0h
  80   ASM_UINT32                        LdtInfo;                // fea4h
  81   ASM_UINT8                         Reserved5[0x50];        // fea8h
  82   ASM_UINT32                        SMBASE;                 // fef8h
  83   ASM_UINT32                        SMMRevId;               // fefch
  84   ASM_UINT16                        AutoHALTRestart;        // ff00h
  85   ASM_UINT16                        IORestart;              // ff02h
  86   ASM_UINT32                        IEDBASE;                // ff04h
  87   ASM_UINT8                         Reserved6[0x14];        // ff08h
  88   ASM_UINT64                        _R15;                   // ff1ch
  89   ASM_UINT64                        _R14;
  90   ASM_UINT64                        _R13;
  91   ASM_UINT64                        _R12;
  92   ASM_UINT64                        _R11;
  93   ASM_UINT64                        _R10;
  94   ASM_UINT64                        _R9;
  95   ASM_UINT64                        _R8;
  96   ASM_UINT64                        _RAX;                   // ff5ch
  97   ASM_UINT64                        _RCX;
  98   ASM_UINT64                        _RDX;
  99   ASM_UINT64                        _RBX;
 100   ASM_UINT64                        _RSP;
 101   ASM_UINT64                        _RBP;
 102   ASM_UINT64                        _RSI;
 103   ASM_UINT64                        _RDI;
 104   ASM_UINT64                        IOMemAddr;              // ff9ch
 105   ASM_UINT32                        IOMisc;                 // ffa4h
 106   ASM_UINT32                        _ES;                    // ffa8h
 107   ASM_UINT32                        _CS;
 108   ASM_UINT32                        _SS;
 109   ASM_UINT32                        _DS;
 110   ASM_UINT32                        _FS;
 111   ASM_UINT32                        _GS;
 112   ASM_UINT32                        _LDTR;                  // ffc0h
 113   ASM_UINT32                        _TR;
 114   ASM_UINT64                        _DR7;                   // ffc8h
 115   ASM_UINT64                        _DR6;
 116   ASM_UINT64                        _RIP;                   // ffd8h
 117   ASM_UINT64                        IA32_EFER;              // ffe0h
 118   ASM_UINT64                        _RFLAGS;                // ffe8h
 119   ASM_UINT64                        _CR3;                   // fff0h
 120   ASM_UINT64                        _CR0;                   // fff8h
 121 } EFI_SMM_CPU_STATE64;
 122
 123 #ifndef __GNUC__
 124 #pragma warning (push)
 125 #pragma warning (disable: 4201)
 126 #endif
 127
 128 typedef union _EFI_SMM_CPU_STATE {
 129   struct {
 130     ASM_UINT8                       Reserved[0x200];
 131     EFI_SMM_CPU_STATE32             x86;
 132   };
 133   EFI_SMM_CPU_STATE64               x64;
 134 } EFI_SMM_CPU_STATE;
 135
 136 #ifndef __GNUC__
 137 #pragma warning (pop)
 138 #pragma pack (pop)
 139 #endif
 140
 141 #define EFI_SMM_MIN_REV_ID_x64      0x30006
 142
 143 #endif