3 Copyright (c) 2005, Intel Corporation. All rights reserved.<BR>
4 This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 Define data structures used by EFI_SMM_CPU_SAVE_STATE protocol.
25 #ifndef _CPUSAVESTATE_H_
26 #define _CPUSAVESTATE_H_
28 typedef unsigned char ASM_UINT8
;
29 typedef ASM_UINT8 ASM_BOOL
;
30 typedef unsigned short ASM_UINT16
;
31 typedef unsigned long ASM_UINT32
;
34 typedef double ASM_UINT64
;
36 typedef UINT64 ASM_UINT64
;
44 typedef struct _EFI_SMM_CPU_STATE32
{
45 ASM_UINT8 Reserved1
[0xf8]; // fe00h
46 ASM_UINT32 SMBASE
; // fef8h
47 ASM_UINT32 SMMRevId
; // fefch
48 ASM_UINT16 IORestart
; // ff00h
49 ASM_UINT16 AutoHALTRestart
; // ff02h
50 ASM_UINT32 IEDBASE
; // ff04h
51 ASM_UINT8 Reserved2
[0x98]; // ff08h
52 ASM_UINT32 IOMemAddr
; // ffa0h
53 ASM_UINT32 IOMisc
; // ffa4h
76 } EFI_SMM_CPU_STATE32
;
78 typedef struct _EFI_SMM_CPU_STATE64
{
79 ASM_UINT8 Reserved1
[0x1d0]; // fc00h
80 ASM_UINT32 GdtBaseHiDword
; // fdd0h
81 ASM_UINT32 LdtBaseHiDword
; // fdd4h
82 ASM_UINT32 IdtBaseHiDword
; // fdd8h
83 ASM_UINT8 Reserved2
[0xc]; // fddch
84 ASM_UINT64 IO_EIP
; // fde8h
85 ASM_UINT8 Reserved3
[0x50]; // fdf0h
86 ASM_UINT32 _CR4
; // fe40h
87 ASM_UINT8 Reserved4
[0x48]; // fe44h
88 ASM_UINT32 GdtBaseLoDword
; // fe8ch
89 ASM_UINT32 GdtLimit
; // fe90h
90 ASM_UINT32 IdtBaseLoDword
; // fe94h
91 ASM_UINT32 IdtLimit
; // fe98h
92 ASM_UINT32 LdtBaseLoDword
; // fe9ch
93 ASM_UINT32 LdtLimit
; // fea0h
94 ASM_UINT32 LdtInfo
; // fea4h
95 ASM_UINT8 Reserved5
[0x50]; // fea8h
96 ASM_UINT32 SMBASE
; // fef8h
97 ASM_UINT32 SMMRevId
; // fefch
98 ASM_UINT16 IORestart
; // ff00h
99 ASM_UINT16 AutoHALTRestart
; // ff02h
100 ASM_UINT32 IEDBASE
; // ff04h
101 ASM_UINT8 Reserved6
[0x14]; // ff08h
102 ASM_UINT64 _R15
; // ff1ch
110 ASM_UINT64 _RAX
; // ff5ch
118 ASM_UINT64 IOMemAddr
; // ff9ch
119 ASM_UINT32 IOMisc
; // ffa4h
120 ASM_UINT32 _ES
; // ffa8h
126 ASM_UINT32 _LDTR
; // ffc0h
128 ASM_UINT64 _DR7
; // ffc8h
130 ASM_UINT64 _RIP
; // ffd8h
131 ASM_UINT64 IA32_EFER
; // ffe0h
132 ASM_UINT64 _RFLAGS
; // ffe8h
133 ASM_UINT64 _CR3
; // fff0h
134 ASM_UINT64 _CR0
; // fff8h
135 } EFI_SMM_CPU_STATE64
;
138 #pragma warning (push)
139 #pragma warning (disable: 4201)
143 typedef union _EFI_SMM_CPU_STATE
{
145 ASM_UINT8 Reserved
[0x200];
146 EFI_SMM_CPU_STATE32 x86
;
148 EFI_SMM_CPU_STATE64 x64
;
152 #pragma warning (pop)
156 #define EFI_SMM_MIN_REV_ID_x64 0x30006