3 Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
4 This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 Defives data structures per Multi Processor Specification Ver 1.4.
21 #ifndef LEGACY_BIOS_MPTABLE_H_
22 #define LEGACY_BIOS_MPTABLE_H_
26 #define EFI_LEGACY_MP_TABLE_REV_1_4 0x04
29 // Define MP table structures. All are packed.
33 #define EFI_LEGACY_MP_TABLE_FLOATING_POINTER_SIGNATURE EFI_SIGNATURE_32 ('_', 'M', 'P', '_')
36 UINT32 PhysicalAddress
;
43 UINT32 MutipleClk
: 1;
45 UINT32 Reserved2
: 24;
47 } EFI_LEGACY_MP_TABLE_FLOATING_POINTER
;
49 #define EFI_LEGACY_MP_TABLE_HEADER_SIGNATURE EFI_SIGNATURE_32 ('P', 'C', 'M', 'P')
52 UINT16 BaseTableLength
;
56 CHAR8 OemProductId
[12];
57 UINT32 OemTablePointer
;
60 UINT32 LocalApicAddress
;
61 UINT16 ExtendedTableLength
;
62 UINT8 ExtendedChecksum
;
64 } EFI_LEGACY_MP_TABLE_HEADER
;
68 } EFI_LEGACY_MP_TABLE_ENTRY_TYPE
;
71 // Entry Type 0: Processor.
73 #define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_PROCESSOR 0x00
95 UINT32 Reserved2
: 22;
99 } EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR
;
102 // Entry Type 1: Bus.
104 #define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_BUS 0x01
109 } EFI_LEGACY_MP_TABLE_ENTRY_BUS
;
111 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUS "CBUS " // Corollary CBus
112 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUSII "CBUSII" // Corollary CBUS II
113 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_EISA "EISA " // Extended ISA
114 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_FUTURE "FUTURE" // IEEE FutureBus
115 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_INTERN "INTERN" // Internal bus
116 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_ISA "ISA " // Industry Standard Architecture
117 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBI "MBI " // Multibus I
118 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBII "MBII " // Multibus II
119 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MCA "MCA " // Micro Channel Architecture
120 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPI "MPI " // MPI
121 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPSA "MPSA " // MPSA
122 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_NUBUS "NUBUS " // Apple Macintosh NuBus
123 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCI "PCI " // Peripheral Component Interconnect
124 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCMCIA "PCMCIA" // PC Memory Card International Assoc.
125 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_TC "TC " // DEC TurboChannel
126 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VL "VL " // VESA Local Bus
127 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VME "VME " // VMEbus
128 #define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_XPRESS "XPRESS" // Express System Bus
130 // Entry Type 2: I/O APIC.
132 #define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IOAPIC 0x02
142 } EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC
;
145 // Entry Type 3: I/O Interrupt Assignment.
147 #define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IO_INT 0x03
154 UINT16 Reserved
: 12;
167 } EFI_LEGACY_MP_TABLE_ENTRY_IO_INT
;
170 EfiLegacyMpTableEntryIoIntTypeInt
= 0,
171 EfiLegacyMpTableEntryIoIntTypeNmi
= 1,
172 EfiLegacyMpTableEntryIoIntTypeSmi
= 2,
173 EfiLegacyMpTableEntryIoIntTypeExtInt
= 3,
174 } EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_TYPE
;
177 EfiLegacyMpTableEntryIoIntFlagsPolaritySpec
= 0x0,
178 EfiLegacyMpTableEntryIoIntFlagsPolarityActiveHigh
= 0x1,
179 EfiLegacyMpTableEntryIoIntFlagsPolarityReserved
= 0x2,
180 EfiLegacyMpTableEntryIoIntFlagsPolarityActiveLow
= 0x3,
181 } EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_POLARITY
;
184 EfiLegacyMpTableEntryIoIntFlagsTriggerSpec
= 0x0,
185 EfiLegacyMpTableEntryIoIntFlagsTriggerEdge
= 0x1,
186 EfiLegacyMpTableEntryIoIntFlagsTriggerReserved
= 0x2,
187 EfiLegacyMpTableEntryIoIntFlagsTriggerLevel
= 0x3,
188 } EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_TRIGGER
;
191 // Entry Type 4: Local Interrupt Assignment.
193 #define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_LOCAL_INT 0x04
200 UINT16 Reserved
: 12;
206 } EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT
;
209 EfiLegacyMpTableEntryLocalIntTypeInt
= 0,
210 EfiLegacyMpTableEntryLocalIntTypeNmi
= 1,
211 EfiLegacyMpTableEntryLocalIntTypeSmi
= 2,
212 EfiLegacyMpTableEntryLocalIntTypeExtInt
= 3,
213 } EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_TYPE
;
216 EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec
= 0x0,
217 EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveHigh
= 0x1,
218 EfiLegacyMpTableEntryLocalIntFlagsPolarityReserved
= 0x2,
219 EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveLow
= 0x3,
220 } EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_POLARITY
;
223 EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec
= 0x0,
224 EfiLegacyMpTableEntryLocalIntFlagsTriggerEdge
= 0x1,
225 EfiLegacyMpTableEntryLocalIntFlagsTriggerReserved
= 0x2,
226 EfiLegacyMpTableEntryLocalIntFlagsTriggerLevel
= 0x3,
227 } EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_TRIGGER
;
230 // Entry Type 128: System Address Space Mapping.
232 #define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_SYS_ADDR_SPACE_MAPPING 0x80
239 UINT64 AddressLength
;
240 } EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING
;
243 EfiLegacyMpTableEntryExtSysAddrSpaceMappingIo
= 0,
244 EfiLegacyMpTableEntryExtSysAddrSpaceMappingMemory
= 1,
245 EfiLegacyMpTableEntryExtSysAddrSpaceMappingPrefetch
= 2,
246 } EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING_TYPE
;
249 // Entry Type 129: Bus Hierarchy.
251 #define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_BUS_HIERARCHY 0x81
257 UINT8 SubtractiveDecode
: 1;
264 } EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY
;
267 // Entry Type 130: Compatibility Bus Address Space Modifier.
269 #define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_COMPAT_BUS_ADDR_SPACE_MODIFIER 0x82
278 UINT32 PredefinedRangeList
;
279 } EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER
;