]>
git.proxmox.com Git - mirror_edk2.git/blob - EdkCompatibilityPkg/Foundation/Include/Ipf/IpfDefines.h
3 // TODO: fix comment to start with /*++
5 // Copyright (c) 2004, Intel Corporation
6 // All rights reserved. This program and the accompanying materials
7 // are licensed and made available under the terms and conditions of the BSD License
8 // which accompanies this distribution. The full text of the license may be found at
9 // http://opensource.org/licenses/bsd-license.php
11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 // IPF Processor Defines.
21 // NOTE: This file is included by assembly files as well.
29 // IPI DElivery Methods
31 #define IPI_INT_DELIVERY 0x0
32 #define IPI_PMI_DELIVERY 0x2
33 #define IPI_NMI_DELIVERY 0x4
34 #define IPI_INIT_DELIVERY 0x5
35 #define IPI_ExtINT_DELIVERY 0x7
38 // Define Itanium-based system registers.
40 // Define Itanium-based system register bit field offsets.
42 // Processor Status Register (PSR) Bit positions
54 // PSR bits 6-12 reserved (must be zero)
57 #define PSR_MBZ0_V 0x1ffUL L
63 #define PSR_IC_MASK (1 << 13)
67 #define PSR_MBZ1_V 0x1UL L
81 // PSR bits 28-31 reserved (must be zero)
84 #define PSR_MBZ2_V 0xfUL L
94 #define PSR_IT_MASK 0x1000000000
105 // PSR bits 45-63 reserved (must be zero)
108 #define PSR_MBZ3_V 0xfffffUL L
111 // Floating Point Status Register (FPSR) Bit positions
124 // Status Field 0 - Controls
133 // Status Field 0 - Flags
143 // Status Field 1 - Controls
145 #define FPSR1_FTZ0 19
146 #define FPSR1_WRE0 20
152 // Status Field 1 - Flags
162 // Status Field 2 - Controls
164 #define FPSR2_FTZ0 32
165 #define FPSR2_WRE0 33
171 // Status Field 2 - Flags
181 // Status Field 3 - Controls
183 #define FPSR3_FTZ0 45
184 #define FPSR3_WRE0 46
190 // Status Field 0 - Flags
200 // FPSR bits 58-63 Reserved -- Must be zero
203 #define FPSR_MBZ0_V 0x3fUL L
206 // For setting up FPSR on kernel entry
207 // All traps are disabled.
209 #define FPSR_FOR_KERNEL 0x3f
211 #define FP_REG_SIZE 16 // 16 byte spill size
212 #define HIGHFP_REGS_LENGTH (96 * 16)
215 // Define hardware Task Priority Register (TPR)
220 #define TPR_MIC 4 // Bits 0 - 3 ignored
221 #define TPR_MIC_LEN 4
222 #define TPR_MMI 16 // Mask Maskable Interrupt
224 // Define hardware Interrupt Status Register (ISR)
230 #define ISR_CODE_LEN 16
231 #define ISR_CODE_MASK 0xFFFF
232 #define ISR_IA_VECTOR 16
233 #define ISR_IA_VECTOR_LEN 8
235 #define ISR_MBZ0_V 0xff
248 #define ISR_MBZ2_V 0xfffff
253 // For General exceptions: ISR{3:0}
255 #define ISR_ILLEGAL_OP 0 // Illegal operation fault
256 #define ISR_PRIV_OP 1 // Privileged operation fault
257 #define ISR_PRIV_REG 2 // Privileged register fauls
258 #define ISR_RESVD_REG 3 // Reserved register/field flt
259 #define ISR_ILLEGAL_ISA 4 // Disabled instruction set transition fault
261 // Define hardware Default Control Register (DCR)
270 #define DCR_MBZ0_V 0xf
278 #define DCR_DEFER_ALL 0x7f00
280 #define DCR_MBZ1_V 0xffffffffffffUL L
283 // Define hardware RSE Configuration Register
285 // RS Configuration (RSC) bit field positions
291 #define RSC_MBZ0_V 0x3ff
292 #define RSC_LOADRS 16
293 #define RSC_LOADRS_LEN 14
295 #define RSC_MBZ1_V 0x3ffffffffUL L
300 #define RSC_MODE_LY (0x0) // Lazy
301 #define RSC_MODE_SI (0x1) // Store intensive
302 #define RSC_MODE_LI (0x2) // Load intensive
303 #define RSC_MODE_EA (0x3) // Eager
305 // RSC Endian bit values
307 #define RSC_BE_LITTLE 0
311 // Define Interruption Function State (IFS) Register
313 // IFS bit field positions
316 #define IFS_IFM_LEN 38
318 #define IFS_MBZ0_V 0x1ffffff
323 // IFS is valid when IFS_V = IFS_VALID
328 // Define Page Table Address (PTA)
333 #define PTA_SIZE_LEN 6
337 // Define Region Register (RR)
340 // RR bit field positions
347 #define RR_RID_LEN 24
351 // SAL uses region register 0 and RID of 1000
353 #define SAL_RID 0x1000
354 #define SAL_RR_REG 0x0
358 // Total number of region registers
363 // Define Protection Key Register (PKR)
365 // PKR bit field positions
373 #define PKR_KEY_LEN 24
376 #define PKR_VALID (1 << PKR_V)
379 // Number of protection key registers
384 // Define Interruption TLB Insertion register (ITIR)
387 // Define Translation Insertion Format (TR)
389 // PTE0 bit field positions
404 // ITIR bit field positions
408 #define ITIR_PS_LEN 6
410 #define ITIR_KEY_LEN 24
412 #define ITIR_MBZ1_LEN 16
414 #define ITIR_PPN_LEN 15
417 #define ATTR_IPAGE 0x661 // Access Rights = RWX (bits 11-9=011), PL 0(8-7=0)
418 #define ATTR_DEF_BITS 0x661 // Access Rights = RWX (bits 11-9=010), PL 0(8-7=0)
419 // Dirty (bit 6=1), Accessed (bit 5=1),
420 // MA WB (bits 4-2=000), Present (bit 0=1)
422 // Memory access rights
424 #define AR_UR_KR 0x0 // user/kernel read
425 #define AR_URX_KRX 0x1 // user/kernel read and execute
426 #define AR_URW_KRW 0x2 // user/kernel read & write
427 #define AR_URWX_KRWX 0x3 // user/kernel read,write&execute
428 #define AR_UR_KRW 0x4 // user read/kernel read,write
429 #define AR_URX_KRWX 0x5 // user read/execute, kernel all
430 #define AR_URWX_KRW 0x6 // user all, kernel read & write
431 #define AR_UX_KRX 0x7 // user execute only, kernel read and execute
433 // Memory attribute values
436 // The next 4 are all cached, non-sequential & speculative, coherent
438 #define MA_WBU 0x0 // Write back, unordered
440 // The next 3 are all non-cached, sequential & non-speculative
442 #define MA_UC 0x4 // Non-coalescing, sequential & non-speculative
443 #define MA_UCE 0x5 // Non-coalescing, sequential, non-speculative
444 // & fetchadd exported
446 #define MA_WC 0x6 // Non-cached, Coalescing, non-seq., spec.
447 #define MA_NAT 0xf // NaT page
449 // Definition of the offset of TRAP/INTERRUPT/FAULT handlers from the
450 // base of IVA (Interruption Vector Address)
452 #define IVT_SIZE 0x8000
453 #define EXTRA_ALIGNMENT 0x1000
455 #define OFF_VHPTFLT 0x0000 // VHPT Translation fault
456 #define OFF_ITLBFLT 0x0400 // Instruction TLB fault
457 #define OFF_DTLBFLT 0x0800 // Data TLB fault
458 #define OFF_ALTITLBFLT 0x0C00 // Alternate ITLB fault
459 #define OFF_ALTDTLBFLT 0x1000 // Alternate DTLB fault
460 #define OFF_NESTEDTLBFLT 0x1400 // Nested TLB fault
461 #define OFF_IKEYMISSFLT 0x1800 // Inst Key Miss fault
462 #define OFF_DKEYMISSFLT 0x1C00 // Data Key Miss fault
463 #define OFF_DIRTYBITFLT 0x2000 // Dirty-Bit fault
464 #define OFF_IACCESSBITFLT 0x2400 // Inst Access-Bit fault
465 #define OFF_DACCESSBITFLT 0x2800 // Data Access-Bit fault
466 #define OFF_BREAKFLT 0x2C00 // Break Inst fault
467 #define OFF_EXTINT 0x3000 // External Interrupt
469 // Offset 0x3400 to 0x0x4C00 are reserved
471 #define OFF_PAGENOTPFLT 0x5000 // Page Not Present fault
472 #define OFF_KEYPERMFLT 0x5100 // Key Permission fault
473 #define OFF_IACCESSRTFLT 0x5200 // Inst Access-Rights flt
474 #define OFF_DACCESSRTFLT 0x5300 // Data Access-Rights fault
475 #define OFF_GPFLT 0x5400 // General Exception fault
476 #define OFF_FPDISFLT 0x5500 // Disable-FP fault
477 #define OFF_NATFLT 0x5600 // NAT Consumption fault
478 #define OFF_SPECLNFLT 0x5700 // Speculation fault
479 #define OFF_DBGFLT 0x5900 // Debug fault
480 #define OFF_ALIGNFLT 0x5A00 // Unaligned Reference fault
481 #define OFF_LOCKDREFFLT 0x5B00 // Locked Data Reference fault
482 #define OFF_FPFLT 0x5C00 // Floating Point fault
483 #define OFF_FPTRAP 0x5D00 // Floating Point Trap
484 #define OFF_LOPRIVTRAP 0x5E00 // Lower-Privilege Transfer Trap
485 #define OFF_TAKENBRTRAP 0x5F00 // Taken Branch Trap
486 #define OFF_SSTEPTRAP 0x6000 // Single Step Trap
488 // Offset 0x6100 to 0x6800 are reserved
490 #define OFF_IA32EXCEPTN 0x6900 // iA32 Exception
491 #define OFF_IA32INTERCEPT 0x6A00 // iA32 Intercept
492 #define OFF_IA32INT 0x6B00 // iA32 Interrupt
493 #define NUMBER_OF_VECTORS 0x100
501 // Instruction set (IS) bits
507 // RSC while in kernel: enabled, little endian, PL = 0, eager mode
509 #define RSC_KERNEL ((RSC_MODE_EA << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
512 // Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode
514 #define RSC_KERNEL_LAZ ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
517 // RSE disabled: disabled, PL = 0, little endian, eager mode
519 #define RSC_KERNEL_DISABLED ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE))
521 #define NAT_BITS_PER_RNAT_REG 63
524 // Macros for generating PTE0 and PTE1 value
526 #define PTE0(ed, ppn12_47, ar, pl, d, a, ma, p) \
527 ( ( ed << PTE0_ED ) | \
528 ( ppn12_47 << PTE0_PPN ) | \
529 ( ar << PTE0_AR ) | \
530 ( pl << PTE0_PL ) | \
533 ( ma << PTE0_MA ) | \
537 #define ITIR(ppn48_63, key, ps) \
538 ( ( ps << ITIR_PS ) | \
539 ( key << ITIR_KEY ) | \
540 ( ppn48_63 << ITIR_PPN ) \
544 // Macro to generate mask value from bit position. The result is a
547 #define BITMASK(bp, value) (value << bp)
549 #define BUNDLE_SIZE 16
550 #define SPURIOUS_INT 0xF
552 #define FAST_DISABLE_INTERRUPTS rsm BITMASK (PSR_I, 1);;
554 #define FAST_ENABLE_INTERRUPTS ssm BITMASK (PSR_I, 1);;