EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Include/Library/EdkIIGluePciExpressLib.h

   1 /*++
   2
   3 Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
   4 This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12
  13 Module Name:
  14
  15   EdkIIGluePciExpressLib.h
  16
  17 Abstract:
  18
  19   Public header file for Pci Express Lib
  20
  21 --*/
  22
  23 #ifndef __EDKII_GLUE_PCI_EXPRESS_LIB_H__
  24 #define __EDKII_GLUE_PCI_EXPRESS_LIB_H__
  25
  26
  27 /**
  28   Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
  29   address that can be passed to the PCI Library functions.
  30
  31   Computes an address that is compatible with the PCI Library functions. The
  32   unused upper bits of Bus, Device, Function and Register are stripped prior to
  33   the generation of the address.
  34
  35   @param  Bus       PCI Bus number. Range 0..255.
  36   @param  Device    PCI Device number. Range 0..31.
  37   @param  Function  PCI Function number. Range 0..7.
  38   @param  Register  PCI Register number. Range 0..4095.
  39
  40   @return The encode PCI address.
  41
  42 **/
  43 #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \
  44   (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
  45
  46 /**
  47   Reads an 8-bit PCI configuration register.
  48
  49   Reads and returns the 8-bit PCI configuration register specified by Address.
  50   This function must guarantee that all PCI read and write operations are
  51   serialized.
  52
  53   If Address > 0x0FFFFFFF, then ASSERT().
  54
  55   @param  Address Address that encodes the PCI Bus, Device, Function and
  56                   Register.
  57
  58   @return The read value from the PCI configuration register.
  59
  60 **/
  61 UINT8
  62 EFIAPI
  63 PciExpressRead8 (
  64   IN      UINTN                     Address
  65   );
  66
  67 /**
  68   Writes an 8-bit PCI configuration register.
  69
  70   Writes the 8-bit PCI configuration register specified by Address with the
  71   value specified by Value. Value is returned. This function must guarantee
  72   that all PCI read and write operations are serialized.
  73
  74   If Address > 0x0FFFFFFF, then ASSERT().
  75
  76   @param  Address Address that encodes the PCI Bus, Device, Function and
  77                   Register.
  78   @param  Value   The value to write.
  79
  80   @return The value written to the PCI configuration register.
  81
  82 **/
  83 UINT8
  84 EFIAPI
  85 PciExpressWrite8 (
  86   IN      UINTN                     Address,
  87   IN      UINT8                     Data
  88   );
  89
  90 /**
  91   Performs a bitwise inclusive OR of an 8-bit PCI configuration register with
  92   an 8-bit value.
  93
  94   Reads the 8-bit PCI configuration register specified by Address, performs a
  95   bitwise inclusive OR between the read result and the value specified by
  96   OrData, and writes the result to the 8-bit PCI configuration register
  97   specified by Address. The value written to the PCI configuration register is
  98   returned. This function must guarantee that all PCI read and write operations
  99   are serialized.
 100
 101   If Address > 0x0FFFFFFF, then ASSERT().
 102
 103   @param  Address Address that encodes the PCI Bus, Device, Function and
 104                   Register.
 105   @param  OrData  The value to OR with the PCI configuration register.
 106
 107   @return The value written back to the PCI configuration register.
 108
 109 **/
 110 UINT8
 111 EFIAPI
 112 PciExpressOr8 (
 113   IN      UINTN                     Address,
 114   IN      UINT8                     OrData
 115   );
 116
 117 /**
 118   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 119   value.
 120
 121   Reads the 8-bit PCI configuration register specified by Address, performs a
 122   bitwise AND between the read result and the value specified by AndData, and
 123   writes the result to the 8-bit PCI configuration register specified by
 124   Address. The value written to the PCI configuration register is returned.
 125   This function must guarantee that all PCI read and write operations are
 126   serialized.
 127
 128   If Address > 0x0FFFFFFF, then ASSERT().
 129
 130   @param  Address Address that encodes the PCI Bus, Device, Function and
 131                   Register.
 132   @param  AndData The value to AND with the PCI configuration register.
 133
 134   @return The value written back to the PCI configuration register.
 135
 136 **/
 137 UINT8
 138 EFIAPI
 139 PciExpressAnd8 (
 140   IN      UINTN                     Address,
 141   IN      UINT8                     AndData
 142   );
 143
 144 /**
 145   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
 146   value, followed a  bitwise inclusive OR with another 8-bit value.
 147
 148   Reads the 8-bit PCI configuration register specified by Address, performs a
 149   bitwise AND between the read result and the value specified by AndData,
 150   performs a bitwise inclusive OR between the result of the AND operation and
 151   the value specified by OrData, and writes the result to the 8-bit PCI
 152   configuration register specified by Address. The value written to the PCI
 153   configuration register is returned. This function must guarantee that all PCI
 154   read and write operations are serialized.
 155
 156   If Address > 0x0FFFFFFF, then ASSERT().
 157
 158   @param  Address Address that encodes the PCI Bus, Device, Function and
 159                   Register.
 160   @param  AndData The value to AND with the PCI configuration register.
 161   @param  OrData  The value to OR with the result of the AND operation.
 162
 163   @return The value written back to the PCI configuration register.
 164
 165 **/
 166 UINT8
 167 EFIAPI
 168 PciExpressAndThenOr8 (
 169   IN      UINTN                     Address,
 170   IN      UINT8                     AndData,
 171   IN      UINT8                     OrData
 172   );
 173
 174 /**
 175   Reads a bit field of a PCI configuration register.
 176
 177   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 178   specified by the StartBit and the EndBit. The value of the bit field is
 179   returned.
 180
 181   If Address > 0x0FFFFFFF, then ASSERT().
 182   If StartBit is greater than 7, then ASSERT().
 183   If EndBit is greater than 7, then ASSERT().
 184   If EndBit is less than StartBit, then ASSERT().
 185
 186   @param  Address   PCI configuration register to read.
 187   @param  StartBit  The ordinal of the least significant bit in the bit field.
 188                     Range 0..7.
 189   @param  EndBit    The ordinal of the most significant bit in the bit field.
 190                     Range 0..7.
 191
 192   @return The value of the bit field read from the PCI configuration register.
 193
 194 **/
 195 UINT8
 196 EFIAPI
 197 PciExpressBitFieldRead8 (
 198   IN      UINTN                     Address,
 199   IN      UINTN                     StartBit,
 200   IN      UINTN                     EndBit
 201   );
 202
 203 /**
 204   Writes a bit field to a PCI configuration register.
 205
 206   Writes Value to the bit field of the PCI configuration register. The bit
 207   field is specified by the StartBit and the EndBit. All other bits in the
 208   destination PCI configuration register are preserved. The new value of the
 209   8-bit register is returned.
 210
 211   If Address > 0x0FFFFFFF, then ASSERT().
 212   If StartBit is greater than 7, then ASSERT().
 213   If EndBit is greater than 7, then ASSERT().
 214   If EndBit is less than StartBit, then ASSERT().
 215
 216   @param  Address   PCI configuration register to write.
 217   @param  StartBit  The ordinal of the least significant bit in the bit field.
 218                     Range 0..7.
 219   @param  EndBit    The ordinal of the most significant bit in the bit field.
 220                     Range 0..7.
 221   @param  Value     New value of the bit field.
 222
 223   @return The value written back to the PCI configuration register.
 224
 225 **/
 226 UINT8
 227 EFIAPI
 228 PciExpressBitFieldWrite8 (
 229   IN      UINTN                     Address,
 230   IN      UINTN                     StartBit,
 231   IN      UINTN                     EndBit,
 232   IN      UINT8                     Value
 233   );
 234
 235 /**
 236   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 237   writes the result back to the bit field in the 8-bit port.
 238
 239   Reads the 8-bit PCI configuration register specified by Address, performs a
 240   bitwise inclusive OR between the read result and the value specified by
 241   OrData, and writes the result to the 8-bit PCI configuration register
 242   specified by Address. The value written to the PCI configuration register is
 243   returned. This function must guarantee that all PCI read and write operations
 244   are serialized. Extra left bits in OrData are stripped.
 245
 246   If Address > 0x0FFFFFFF, then ASSERT().
 247   If StartBit is greater than 7, then ASSERT().
 248   If EndBit is greater than 7, then ASSERT().
 249   If EndBit is less than StartBit, then ASSERT().
 250
 251   @param  Address   PCI configuration register to write.
 252   @param  StartBit  The ordinal of the least significant bit in the bit field.
 253                     Range 0..7.
 254   @param  EndBit    The ordinal of the most significant bit in the bit field.
 255                     Range 0..7.
 256   @param  OrData    The value to OR with the PCI configuration register.
 257
 258   @return The value written back to the PCI configuration register.
 259
 260 **/
 261 UINT8
 262 EFIAPI
 263 PciExpressBitFieldOr8 (
 264   IN      UINTN                     Address,
 265   IN      UINTN                     StartBit,
 266   IN      UINTN                     EndBit,
 267   IN      UINT8                     OrData
 268   );
 269
 270 /**
 271   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 272   AND, and writes the result back to the bit field in the 8-bit register.
 273
 274   Reads the 8-bit PCI configuration register specified by Address, performs a
 275   bitwise AND between the read result and the value specified by AndData, and
 276   writes the result to the 8-bit PCI configuration register specified by
 277   Address. The value written to the PCI configuration register is returned.
 278   This function must guarantee that all PCI read and write operations are
 279   serialized. Extra left bits in AndData are stripped.
 280
 281   If Address > 0x0FFFFFFF, then ASSERT().
 282   If StartBit is greater than 7, then ASSERT().
 283   If EndBit is greater than 7, then ASSERT().
 284   If EndBit is less than StartBit, then ASSERT().
 285
 286   @param  Address   PCI configuration register to write.
 287   @param  StartBit  The ordinal of the least significant bit in the bit field.
 288                     Range 0..7.
 289   @param  EndBit    The ordinal of the most significant bit in the bit field.
 290                     Range 0..7.
 291   @param  AndData   The value to AND with the PCI configuration register.
 292
 293   @return The value written back to the PCI configuration register.
 294
 295 **/
 296 UINT8
 297 EFIAPI
 298 PciExpressBitFieldAnd8 (
 299   IN      UINTN                     Address,
 300   IN      UINTN                     StartBit,
 301   IN      UINTN                     EndBit,
 302   IN      UINT8                     AndData
 303   );
 304
 305 /**
 306   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 307   bitwise inclusive OR, and writes the result back to the bit field in the
 308   8-bit port.
 309
 310   Reads the 8-bit PCI configuration register specified by Address, performs a
 311   bitwise AND followed by a bitwise inclusive OR between the read result and
 312   the value specified by AndData, and writes the result to the 8-bit PCI
 313   configuration register specified by Address. The value written to the PCI
 314   configuration register is returned. This function must guarantee that all PCI
 315   read and write operations are serialized. Extra left bits in both AndData and
 316   OrData are stripped.
 317
 318   If Address > 0x0FFFFFFF, then ASSERT().
 319   If StartBit is greater than 7, then ASSERT().
 320   If EndBit is greater than 7, then ASSERT().
 321   If EndBit is less than StartBit, then ASSERT().
 322
 323   @param  Address   PCI configuration register to write.
 324   @param  StartBit  The ordinal of the least significant bit in the bit field.
 325                     Range 0..7.
 326   @param  EndBit    The ordinal of the most significant bit in the bit field.
 327                     Range 0..7.
 328   @param  AndData   The value to AND with the PCI configuration register.
 329   @param  OrData    The value to OR with the result of the AND operation.
 330
 331   @return The value written back to the PCI configuration register.
 332
 333 **/
 334 UINT8
 335 EFIAPI
 336 PciExpressBitFieldAndThenOr8 (
 337   IN      UINTN                     Address,
 338   IN      UINTN                     StartBit,
 339   IN      UINTN                     EndBit,
 340   IN      UINT8                     AndData,
 341   IN      UINT8                     OrData
 342   );
 343
 344 /**
 345   Reads a 16-bit PCI configuration register.
 346
 347   Reads and returns the 16-bit PCI configuration register specified by Address.
 348   This function must guarantee that all PCI read and write operations are
 349   serialized.
 350
 351   If Address > 0x0FFFFFFF, then ASSERT().
 352   If Address is not aligned on a 16-bit boundary, then ASSERT().
 353
 354   @param  Address Address that encodes the PCI Bus, Device, Function and
 355                   Register.
 356
 357   @return The read value from the PCI configuration register.
 358
 359 **/
 360 UINT16
 361 EFIAPI
 362 PciExpressRead16 (
 363   IN      UINTN                     Address
 364   );
 365
 366 /**
 367   Writes a 16-bit PCI configuration register.
 368
 369   Writes the 16-bit PCI configuration register specified by Address with the
 370   value specified by Value. Value is returned. This function must guarantee
 371   that all PCI read and write operations are serialized.
 372
 373   If Address > 0x0FFFFFFF, then ASSERT().
 374   If Address is not aligned on a 16-bit boundary, then ASSERT().
 375
 376   @param  Address Address that encodes the PCI Bus, Device, Function and
 377                   Register.
 378   @param  Value   The value to write.
 379
 380   @return The value written to the PCI configuration register.
 381
 382 **/
 383 UINT16
 384 EFIAPI
 385 PciExpressWrite16 (
 386   IN      UINTN                     Address,
 387   IN      UINT16                    Data
 388   );
 389
 390 /**
 391   Performs a bitwise inclusive OR of a 16-bit PCI configuration register with
 392   a 16-bit value.
 393
 394   Reads the 16-bit PCI configuration register specified by Address, performs a
 395   bitwise inclusive OR between the read result and the value specified by
 396   OrData, and writes the result to the 16-bit PCI configuration register
 397   specified by Address. The value written to the PCI configuration register is
 398   returned. This function must guarantee that all PCI read and write operations
 399   are serialized.
 400
 401   If Address > 0x0FFFFFFF, then ASSERT().
 402   If Address is not aligned on a 16-bit boundary, then ASSERT().
 403
 404   @param  Address Address that encodes the PCI Bus, Device, Function and
 405                   Register.
 406   @param  OrData  The value to OR with the PCI configuration register.
 407
 408   @return The value written back to the PCI configuration register.
 409
 410 **/
 411 UINT16
 412 EFIAPI
 413 PciExpressOr16 (
 414   IN      UINTN                     Address,
 415   IN      UINT16                    OrData
 416   );
 417
 418 /**
 419   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 420   value.
 421
 422   Reads the 16-bit PCI configuration register specified by Address, performs a
 423   bitwise AND between the read result and the value specified by AndData, and
 424   writes the result to the 16-bit PCI configuration register specified by
 425   Address. The value written to the PCI configuration register is returned.
 426   This function must guarantee that all PCI read and write operations are
 427   serialized.
 428
 429   If Address > 0x0FFFFFFF, then ASSERT().
 430   If Address is not aligned on a 16-bit boundary, then ASSERT().
 431
 432   @param  Address Address that encodes the PCI Bus, Device, Function and
 433                   Register.
 434   @param  AndData The value to AND with the PCI configuration register.
 435
 436   @return The value written back to the PCI configuration register.
 437
 438 **/
 439 UINT16
 440 EFIAPI
 441 PciExpressAnd16 (
 442   IN      UINTN                     Address,
 443   IN      UINT16                    AndData
 444   );
 445
 446 /**
 447   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
 448   value, followed a  bitwise inclusive OR with another 16-bit value.
 449
 450   Reads the 16-bit PCI configuration register specified by Address, performs a
 451   bitwise AND between the read result and the value specified by AndData,
 452   performs a bitwise inclusive OR between the result of the AND operation and
 453   the value specified by OrData, and writes the result to the 16-bit PCI
 454   configuration register specified by Address. The value written to the PCI
 455   configuration register is returned. This function must guarantee that all PCI
 456   read and write operations are serialized.
 457
 458   If Address > 0x0FFFFFFF, then ASSERT().
 459   If Address is not aligned on a 16-bit boundary, then ASSERT().
 460
 461   @param  Address Address that encodes the PCI Bus, Device, Function and
 462                   Register.
 463   @param  AndData The value to AND with the PCI configuration register.
 464   @param  OrData  The value to OR with the result of the AND operation.
 465
 466   @return The value written back to the PCI configuration register.
 467
 468 **/
 469 UINT16
 470 EFIAPI
 471 PciExpressAndThenOr16 (
 472   IN      UINTN                     Address,
 473   IN      UINT16                    AndData,
 474   IN      UINT16                    OrData
 475   );
 476
 477 /**
 478   Reads a bit field of a PCI configuration register.
 479
 480   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 481   specified by the StartBit and the EndBit. The value of the bit field is
 482   returned.
 483
 484   If Address > 0x0FFFFFFF, then ASSERT().
 485   If Address is not aligned on a 16-bit boundary, then ASSERT().
 486   If StartBit is greater than 15, then ASSERT().
 487   If EndBit is greater than 15, then ASSERT().
 488   If EndBit is less than StartBit, then ASSERT().
 489
 490   @param  Address   PCI configuration register to read.
 491   @param  StartBit  The ordinal of the least significant bit in the bit field.
 492                     Range 0..15.
 493   @param  EndBit    The ordinal of the most significant bit in the bit field.
 494                     Range 0..15.
 495
 496   @return The value of the bit field read from the PCI configuration register.
 497
 498 **/
 499 UINT16
 500 EFIAPI
 501 PciExpressBitFieldRead16 (
 502   IN      UINTN                     Address,
 503   IN      UINTN                     StartBit,
 504   IN      UINTN                     EndBit
 505   );
 506
 507 /**
 508   Writes a bit field to a PCI configuration register.
 509
 510   Writes Value to the bit field of the PCI configuration register. The bit
 511   field is specified by the StartBit and the EndBit. All other bits in the
 512   destination PCI configuration register are preserved. The new value of the
 513   16-bit register is returned.
 514
 515   If Address > 0x0FFFFFFF, then ASSERT().
 516   If Address is not aligned on a 16-bit boundary, then ASSERT().
 517   If StartBit is greater than 15, then ASSERT().
 518   If EndBit is greater than 15, then ASSERT().
 519   If EndBit is less than StartBit, then ASSERT().
 520
 521   @param  Address   PCI configuration register to write.
 522   @param  StartBit  The ordinal of the least significant bit in the bit field.
 523                     Range 0..15.
 524   @param  EndBit    The ordinal of the most significant bit in the bit field.
 525                     Range 0..15.
 526   @param  Value     New value of the bit field.
 527
 528   @return The value written back to the PCI configuration register.
 529
 530 **/
 531 UINT16
 532 EFIAPI
 533 PciExpressBitFieldWrite16 (
 534   IN      UINTN                     Address,
 535   IN      UINTN                     StartBit,
 536   IN      UINTN                     EndBit,
 537   IN      UINT16                    Value
 538   );
 539
 540 /**
 541   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
 542   writes the result back to the bit field in the 16-bit port.
 543
 544   Reads the 16-bit PCI configuration register specified by Address, performs a
 545   bitwise inclusive OR between the read result and the value specified by
 546   OrData, and writes the result to the 16-bit PCI configuration register
 547   specified by Address. The value written to the PCI configuration register is
 548   returned. This function must guarantee that all PCI read and write operations
 549   are serialized. Extra left bits in OrData are stripped.
 550
 551   If Address > 0x0FFFFFFF, then ASSERT().
 552   If Address is not aligned on a 16-bit boundary, then ASSERT().
 553   If StartBit is greater than 15, then ASSERT().
 554   If EndBit is greater than 15, then ASSERT().
 555   If EndBit is less than StartBit, then ASSERT().
 556
 557   @param  Address   PCI configuration register to write.
 558   @param  StartBit  The ordinal of the least significant bit in the bit field.
 559                     Range 0..15.
 560   @param  EndBit    The ordinal of the most significant bit in the bit field.
 561                     Range 0..15.
 562   @param  OrData    The value to OR with the PCI configuration register.
 563
 564   @return The value written back to the PCI configuration register.
 565
 566 **/
 567 UINT16
 568 EFIAPI
 569 PciExpressBitFieldOr16 (
 570   IN      UINTN                     Address,
 571   IN      UINTN                     StartBit,
 572   IN      UINTN                     EndBit,
 573   IN      UINT16                    OrData
 574   );
 575
 576 /**
 577   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 578   AND, and writes the result back to the bit field in the 16-bit register.
 579
 580   Reads the 16-bit PCI configuration register specified by Address, performs a
 581   bitwise AND between the read result and the value specified by AndData, and
 582   writes the result to the 16-bit PCI configuration register specified by
 583   Address. The value written to the PCI configuration register is returned.
 584   This function must guarantee that all PCI read and write operations are
 585   serialized. Extra left bits in AndData are stripped.
 586
 587   If Address > 0x0FFFFFFF, then ASSERT().
 588   If Address is not aligned on a 16-bit boundary, then ASSERT().
 589   If StartBit is greater than 15, then ASSERT().
 590   If EndBit is greater than 15, then ASSERT().
 591   If EndBit is less than StartBit, then ASSERT().
 592
 593   @param  Address   PCI configuration register to write.
 594   @param  StartBit  The ordinal of the least significant bit in the bit field.
 595                     Range 0..15.
 596   @param  EndBit    The ordinal of the most significant bit in the bit field.
 597                     Range 0..15.
 598   @param  AndData   The value to AND with the PCI configuration register.
 599
 600   @return The value written back to the PCI configuration register.
 601
 602 **/
 603 UINT16
 604 EFIAPI
 605 PciExpressBitFieldAnd16 (
 606   IN      UINTN                     Address,
 607   IN      UINTN                     StartBit,
 608   IN      UINTN                     EndBit,
 609   IN      UINT16                    AndData
 610   );
 611
 612 /**
 613   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 614   bitwise inclusive OR, and writes the result back to the bit field in the
 615   16-bit port.
 616
 617   Reads the 16-bit PCI configuration register specified by Address, performs a
 618   bitwise AND followed by a bitwise inclusive OR between the read result and
 619   the value specified by AndData, and writes the result to the 16-bit PCI
 620   configuration register specified by Address. The value written to the PCI
 621   configuration register is returned. This function must guarantee that all PCI
 622   read and write operations are serialized. Extra left bits in both AndData and
 623   OrData are stripped.
 624
 625   If Address > 0x0FFFFFFF, then ASSERT().
 626   If Address is not aligned on a 16-bit boundary, then ASSERT().
 627   If StartBit is greater than 15, then ASSERT().
 628   If EndBit is greater than 15, then ASSERT().
 629   If EndBit is less than StartBit, then ASSERT().
 630
 631   @param  Address   PCI configuration register to write.
 632   @param  StartBit  The ordinal of the least significant bit in the bit field.
 633                     Range 0..15.
 634   @param  EndBit    The ordinal of the most significant bit in the bit field.
 635                     Range 0..15.
 636   @param  AndData   The value to AND with the PCI configuration register.
 637   @param  OrData    The value to OR with the result of the AND operation.
 638
 639   @return The value written back to the PCI configuration register.
 640
 641 **/
 642 UINT16
 643 EFIAPI
 644 PciExpressBitFieldAndThenOr16 (
 645   IN      UINTN                     Address,
 646   IN      UINTN                     StartBit,
 647   IN      UINTN                     EndBit,
 648   IN      UINT16                    AndData,
 649   IN      UINT16                    OrData
 650   );
 651
 652 /**
 653   Reads a 32-bit PCI configuration register.
 654
 655   Reads and returns the 32-bit PCI configuration register specified by Address.
 656   This function must guarantee that all PCI read and write operations are
 657   serialized.
 658
 659   If Address > 0x0FFFFFFF, then ASSERT().
 660   If Address is not aligned on a 32-bit boundary, then ASSERT().
 661
 662   @param  Address Address that encodes the PCI Bus, Device, Function and
 663                   Register.
 664
 665   @return The read value from the PCI configuration register.
 666
 667 **/
 668 UINT32
 669 EFIAPI
 670 PciExpressRead32 (
 671   IN      UINTN                     Address
 672   );
 673
 674 /**
 675   Writes a 32-bit PCI configuration register.
 676
 677   Writes the 32-bit PCI configuration register specified by Address with the
 678   value specified by Value. Value is returned. This function must guarantee
 679   that all PCI read and write operations are serialized.
 680
 681   If Address > 0x0FFFFFFF, then ASSERT().
 682   If Address is not aligned on a 32-bit boundary, then ASSERT().
 683
 684   @param  Address Address that encodes the PCI Bus, Device, Function and
 685                   Register.
 686   @param  Value   The value to write.
 687
 688   @return The value written to the PCI configuration register.
 689
 690 **/
 691 UINT32
 692 EFIAPI
 693 PciExpressWrite32 (
 694   IN      UINTN                     Address,
 695   IN      UINT32                    Data
 696   );
 697
 698 /**
 699   Performs a bitwise inclusive OR of a 32-bit PCI configuration register with
 700   a 32-bit value.
 701
 702   Reads the 32-bit PCI configuration register specified by Address, performs a
 703   bitwise inclusive OR between the read result and the value specified by
 704   OrData, and writes the result to the 32-bit PCI configuration register
 705   specified by Address. The value written to the PCI configuration register is
 706   returned. This function must guarantee that all PCI read and write operations
 707   are serialized.
 708
 709   If Address > 0x0FFFFFFF, then ASSERT().
 710   If Address is not aligned on a 32-bit boundary, then ASSERT().
 711
 712   @param  Address Address that encodes the PCI Bus, Device, Function and
 713                   Register.
 714   @param  OrData  The value to OR with the PCI configuration register.
 715
 716   @return The value written back to the PCI configuration register.
 717
 718 **/
 719 UINT32
 720 EFIAPI
 721 PciExpressOr32 (
 722   IN      UINTN                     Address,
 723   IN      UINT32                    OrData
 724   );
 725
 726 /**
 727   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 728   value.
 729
 730   Reads the 32-bit PCI configuration register specified by Address, performs a
 731   bitwise AND between the read result and the value specified by AndData, and
 732   writes the result to the 32-bit PCI configuration register specified by
 733   Address. The value written to the PCI configuration register is returned.
 734   This function must guarantee that all PCI read and write operations are
 735   serialized.
 736
 737   If Address > 0x0FFFFFFF, then ASSERT().
 738   If Address is not aligned on a 32-bit boundary, then ASSERT().
 739
 740   @param  Address Address that encodes the PCI Bus, Device, Function and
 741                   Register.
 742   @param  AndData The value to AND with the PCI configuration register.
 743
 744   @return The value written back to the PCI configuration register.
 745
 746 **/
 747 UINT32
 748 EFIAPI
 749 PciExpressAnd32 (
 750   IN      UINTN                     Address,
 751   IN      UINT32                    AndData
 752   );
 753
 754 /**
 755   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
 756   value, followed a  bitwise inclusive OR with another 32-bit value.
 757
 758   Reads the 32-bit PCI configuration register specified by Address, performs a
 759   bitwise AND between the read result and the value specified by AndData,
 760   performs a bitwise inclusive OR between the result of the AND operation and
 761   the value specified by OrData, and writes the result to the 32-bit PCI
 762   configuration register specified by Address. The value written to the PCI
 763   configuration register is returned. This function must guarantee that all PCI
 764   read and write operations are serialized.
 765
 766   If Address > 0x0FFFFFFF, then ASSERT().
 767   If Address is not aligned on a 32-bit boundary, then ASSERT().
 768
 769   @param  Address Address that encodes the PCI Bus, Device, Function and
 770                   Register.
 771   @param  AndData The value to AND with the PCI configuration register.
 772   @param  OrData  The value to OR with the result of the AND operation.
 773
 774   @return The value written back to the PCI configuration register.
 775
 776 **/
 777 UINT32
 778 EFIAPI
 779 PciExpressAndThenOr32 (
 780   IN      UINTN                     Address,
 781   IN      UINT32                    AndData,
 782   IN      UINT32                    OrData
 783   );
 784
 785 /**
 786   Reads a bit field of a PCI configuration register.
 787
 788   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 789   specified by the StartBit and the EndBit. The value of the bit field is
 790   returned.
 791
 792   If Address > 0x0FFFFFFF, then ASSERT().
 793   If Address is not aligned on a 32-bit boundary, then ASSERT().
 794   If StartBit is greater than 31, then ASSERT().
 795   If EndBit is greater than 31, then ASSERT().
 796   If EndBit is less than StartBit, then ASSERT().
 797
 798   @param  Address   PCI configuration register to read.
 799   @param  StartBit  The ordinal of the least significant bit in the bit field.
 800                     Range 0..31.
 801   @param  EndBit    The ordinal of the most significant bit in the bit field.
 802                     Range 0..31.
 803
 804   @return The value of the bit field read from the PCI configuration register.
 805
 806 **/
 807 UINT32
 808 EFIAPI
 809 PciExpressBitFieldRead32 (
 810   IN      UINTN                     Address,
 811   IN      UINTN                     StartBit,
 812   IN      UINTN                     EndBit
 813   );
 814
 815 /**
 816   Writes a bit field to a PCI configuration register.
 817
 818   Writes Value to the bit field of the PCI configuration register. The bit
 819   field is specified by the StartBit and the EndBit. All other bits in the
 820   destination PCI configuration register are preserved. The new value of the
 821   32-bit register is returned.
 822
 823   If Address > 0x0FFFFFFF, then ASSERT().
 824   If Address is not aligned on a 32-bit boundary, then ASSERT().
 825   If StartBit is greater than 31, then ASSERT().
 826   If EndBit is greater than 31, then ASSERT().
 827   If EndBit is less than StartBit, then ASSERT().
 828
 829   @param  Address   PCI configuration register to write.
 830   @param  StartBit  The ordinal of the least significant bit in the bit field.
 831                     Range 0..31.
 832   @param  EndBit    The ordinal of the most significant bit in the bit field.
 833                     Range 0..31.
 834   @param  Value     New value of the bit field.
 835
 836   @return The value written back to the PCI configuration register.
 837
 838 **/
 839 UINT32
 840 EFIAPI
 841 PciExpressBitFieldWrite32 (
 842   IN      UINTN                     Address,
 843   IN      UINTN                     StartBit,
 844   IN      UINTN                     EndBit,
 845   IN      UINT32                    Value
 846   );
 847
 848 /**
 849   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 850   writes the result back to the bit field in the 32-bit port.
 851
 852   Reads the 32-bit PCI configuration register specified by Address, performs a
 853   bitwise inclusive OR between the read result and the value specified by
 854   OrData, and writes the result to the 32-bit PCI configuration register
 855   specified by Address. The value written to the PCI configuration register is
 856   returned. This function must guarantee that all PCI read and write operations
 857   are serialized. Extra left bits in OrData are stripped.
 858
 859   If Address > 0x0FFFFFFF, then ASSERT().
 860   If Address is not aligned on a 32-bit boundary, then ASSERT().
 861   If StartBit is greater than 31, then ASSERT().
 862   If EndBit is greater than 31, then ASSERT().
 863   If EndBit is less than StartBit, then ASSERT().
 864
 865   @param  Address   PCI configuration register to write.
 866   @param  StartBit  The ordinal of the least significant bit in the bit field.
 867                     Range 0..31.
 868   @param  EndBit    The ordinal of the most significant bit in the bit field.
 869                     Range 0..31.
 870   @param  OrData    The value to OR with the PCI configuration register.
 871
 872   @return The value written back to the PCI configuration register.
 873
 874 **/
 875 UINT32
 876 EFIAPI
 877 PciExpressBitFieldOr32 (
 878   IN      UINTN                     Address,
 879   IN      UINTN                     StartBit,
 880   IN      UINTN                     EndBit,
 881   IN      UINT32                    OrData
 882   );
 883
 884 /**
 885   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 886   AND, and writes the result back to the bit field in the 32-bit register.
 887
 888   Reads the 32-bit PCI configuration register specified by Address, performs a
 889   bitwise AND between the read result and the value specified by AndData, and
 890   writes the result to the 32-bit PCI configuration register specified by
 891   Address. The value written to the PCI configuration register is returned.
 892   This function must guarantee that all PCI read and write operations are
 893   serialized. Extra left bits in AndData are stripped.
 894
 895   If Address > 0x0FFFFFFF, then ASSERT().
 896   If Address is not aligned on a 32-bit boundary, then ASSERT().
 897   If StartBit is greater than 31, then ASSERT().
 898   If EndBit is greater than 31, then ASSERT().
 899   If EndBit is less than StartBit, then ASSERT().
 900
 901   @param  Address   PCI configuration register to write.
 902   @param  StartBit  The ordinal of the least significant bit in the bit field.
 903                     Range 0..31.
 904   @param  EndBit    The ordinal of the most significant bit in the bit field.
 905                     Range 0..31.
 906   @param  AndData   The value to AND with the PCI configuration register.
 907
 908   @return The value written back to the PCI configuration register.
 909
 910 **/
 911 UINT32
 912 EFIAPI
 913 PciExpressBitFieldAnd32 (
 914   IN      UINTN                     Address,
 915   IN      UINTN                     StartBit,
 916   IN      UINTN                     EndBit,
 917   IN      UINT32                    AndData
 918   );
 919
 920 /**
 921   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 922   bitwise inclusive OR, and writes the result back to the bit field in the
 923   32-bit port.
 924
 925   Reads the 32-bit PCI configuration register specified by Address, performs a
 926   bitwise AND followed by a bitwise inclusive OR between the read result and
 927   the value specified by AndData, and writes the result to the 32-bit PCI
 928   configuration register specified by Address. The value written to the PCI
 929   configuration register is returned. This function must guarantee that all PCI
 930   read and write operations are serialized. Extra left bits in both AndData and
 931   OrData are stripped.
 932
 933   If Address > 0x0FFFFFFF, then ASSERT().
 934   If Address is not aligned on a 32-bit boundary, then ASSERT().
 935   If StartBit is greater than 31, then ASSERT().
 936   If EndBit is greater than 31, then ASSERT().
 937   If EndBit is less than StartBit, then ASSERT().
 938
 939   @param  Address   PCI configuration register to write.
 940   @param  StartBit  The ordinal of the least significant bit in the bit field.
 941                     Range 0..31.
 942   @param  EndBit    The ordinal of the most significant bit in the bit field.
 943                     Range 0..31.
 944   @param  AndData   The value to AND with the PCI configuration register.
 945   @param  OrData    The value to OR with the result of the AND operation.
 946
 947   @return The value written back to the PCI configuration register.
 948
 949 **/
 950 UINT32
 951 EFIAPI
 952 PciExpressBitFieldAndThenOr32 (
 953   IN      UINTN                     Address,
 954   IN      UINTN                     StartBit,
 955   IN      UINTN                     EndBit,
 956   IN      UINT32                    AndData,
 957   IN      UINT32                    OrData
 958   );
 959
 960 /**
 961   Reads a range of PCI configuration registers into a caller supplied buffer.
 962
 963   Reads the range of PCI configuration registers specified by StartAddress and
 964   Size into the buffer specified by Buffer. This function only allows the PCI
 965   configuration registers from a single PCI function to be read. Size is
 966   returned. When possible 32-bit PCI configuration read cycles are used to read
 967   from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
 968   and 16-bit PCI configuration read cycles may be used at the beginning and the
 969   end of the range.
 970
 971   If StartAddress > 0x0FFFFFFF, then ASSERT().
 972   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 973   If Size > 0 and Buffer is NULL, then ASSERT().
 974
 975   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
 976                         Function and Register.
 977   @param  Size          Size in bytes of the transfer.
 978   @param  Buffer        Pointer to a buffer receiving the data read.
 979
 980   @return Size
 981
 982 **/
 983 UINTN
 984 EFIAPI
 985 PciExpressReadBuffer (
 986   IN      UINTN                     StartAddress,
 987   IN      UINTN                     Size,
 988   OUT     VOID                      *Buffer
 989   );
 990
 991 /**
 992   Copies the data in a caller supplied buffer to a specified range of PCI
 993   configuration space.
 994
 995   Writes the range of PCI configuration registers specified by StartAddress and
 996   Size from the buffer specified by Buffer. This function only allows the PCI
 997   configuration registers from a single PCI function to be written. Size is
 998   returned. When possible 32-bit PCI configuration write cycles are used to
 999   write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1000   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1001   and the end of the range.
1002
1003   If StartAddress > 0x0FFFFFFF, then ASSERT().
1004   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1005   If Size > 0 and Buffer is NULL, then ASSERT().
1006
1007   @param  StartAddress  Starting address that encodes the PCI Bus, Device,
1008                         Function and Register.
1009   @param  Size          Size in bytes of the transfer.
1010   @param  Buffer        Pointer to a buffer containing the data to write.
1011
1012   @return Size
1013
1014 **/
1015 UINTN
1016 EFIAPI
1017 PciExpressWriteBuffer (
1018   IN      UINTN                     StartAddress,
1019   IN      UINTN                     Size,
1020   IN      VOID                      *Buffer
1021   );
1022
1023 #endif