EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/FlushCacheRange.s

   1 /// Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>
   2 /// This program and the accompanying materials
   3 /// are licensed and made available under the terms and conditions of the BSD License
   4 /// which accompanies this distribution.  The full text of the license may be found at
   5 /// http://opensource.org/licenses/bsd-license.php
   6 ///
   7 /// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
   8 /// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   9 ///
  10 /// Module Name:
  11 ///
  12 ///   FlushCacheRange.s
  13 ///
  14 /// Abstract:
  15 ///
  16 ///
  17
  18 .file  "IpfCpuCache.s"
  19
  20 #include  "IpfMacro.i"
  21 #include  "IpfDefines.h"
  22
  23 //
  24 //  Invalidates a range of instruction cache lines in the cache coherency domain
  25 //  of the calling CPU.
  26 //
  27 //  Invalidates the instruction cache lines specified by Address and Length. If
  28 //  Address is not aligned on a cache line boundary, then entire instruction
  29 //  cache line containing Address is invalidated. If Address + Length is not
  30 //  aligned on a cache line boundary, then the entire instruction cache line
  31 //  containing Address + Length -1 is invalidated. This function may choose to
  32 //  invalidate the entire instruction cache if that is more efficient than
  33 //  invalidating the specified range. If Length is 0, the no instruction cache
  34 //  lines are invalidated. Address is returned.
  35 //  This function is only available on IPF.
  36 //
  37 //  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  38 //
  39 //  @param  Address The base address of the instruction cache lines to
  40 //                  invalidate. If the CPU is in a physical addressing mode, then
  41 //                  Address is a physical address. If the CPU is in a virtual
  42 //                  addressing mode, then Address is a virtual address.
  43 //
  44 //  @param  Length  The number of bytes to invalidate from the instruction cache.
  45 //
  46 //  @return Address
  47 //
  48 //  VOID *
  49 //  EFIAPI
  50 //  AsmFlushCacheRange (
  51 //    IN      VOID                      *Address,
  52 //    IN      UINTN                     Length
  53 //    );
  54 //
  55 PROCEDURE_ENTRY (AsmFlushCacheRange)
  56
  57       NESTED_SETUP (5,8,0,0)
  58
  59       mov         loc2 = ar.lc
  60
  61       mov         loc3 = in0                  // Start address.
  62       mov         loc4 = in1;;                // Length in bytes.
  63
  64       cmp.eq  p6,p7 = loc4, r0;;               // If Length is zero then don't flush any cache
  65       (p6)  br.spnt.many DoneFlushingC;;
  66
  67       add         loc4 = loc4,loc3
  68       mov         loc5 = 1;;
  69       sub         loc4 = loc4, loc5 ;; // the End address to flush
  70
  71       dep         loc3 = r0,loc3,0,5
  72       dep         loc4 = r0,loc4,0,5;;
  73       shr         loc3 = loc3,5
  74       shr         loc4 = loc4,5;;    // 32 byte cache line
  75
  76       sub         loc4 = loc4,loc3;; // total flush count, It should be add 1 but
  77                                      // the br.cloop will first execute one time
  78       mov         loc3 = in0
  79       mov         loc5 = 32
  80       mov         ar.lc = loc4;;
  81
  82 StillFlushingC:
  83       fc          loc3;;
  84       sync.i;;
  85       srlz.i;;
  86       add         loc3 = loc5,loc3;;
  87       br.cloop.sptk.few StillFlushingC;;
  88
  89 DoneFlushingC:
  90       mov         ar.lc = loc2
  91       mov          r8   = in0       // return *Address
  92       NESTED_RETURN
  93
  94 PROCEDURE_EXIT (AsmFlushCacheRange)
  95