EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/X64/Thunk16.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2006 - 2008, Intel Corporation
   4 # All rights reserved. This program and the accompanying materials
   5 # are licensed and made available under the terms and conditions of the BSD License
   6 # which accompanies this distribution.  The full text of the license may be found at
   7 # http://opensource.org/licenses/bsd-license.php
   8 #
   9 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 #
  12 # Module Name:
  13 #
  14 #   Thunk16.S
  15 #
  16 # Abstract:
  17 #
  18 #   Real mode thunk
  19 #
  20 #------------------------------------------------------------------------------
  21 #include <EdkIIGlueBase.h>
  22
  23 .globl ASM_PFX(m16Start)
  24 .globl ASM_PFX(m16Size)
  25 .globl ASM_PFX(mThunk16Attr)
  26 .globl ASM_PFX(m16Gdt)
  27 .globl ASM_PFX(m16GdtrBase)
  28 .globl ASM_PFX(mTransition)
  29 .globl ASM_PFX(InternalAsmThunk16)
  30
  31 # define the structure of IA32_REGS
  32 .equ  _EDI, 0       #size 4
  33 .equ  _ESI, 4       #size 4
  34 .equ  _EBP, 8       #size 4
  35 .equ  _ESP, 12      #size 4
  36 .equ  _EBX, 16      #size 4
  37 .equ  _EDX, 20      #size 4
  38 .equ  _ECX, 24      #size 4
  39 .equ  _EAX, 28      #size 4
  40 .equ  _DS,  32      #size 2
  41 .equ  _ES,  34      #size 2
  42 .equ  _FS,  36      #size 2
  43 .equ  _GS,  38      #size 2
  44 .equ  _EFLAGS, 40   #size 8
  45 .equ  _EIP, 48      #size 4
  46 .equ  _CS, 52       #size 2
  47 .equ  _SS, 54       #size 2
  48 .equ  IA32_REGS_SIZE, 56
  49
  50     .data
  51
  52 ASM_PFX(m16Size):         .word      ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)
  53 ASM_PFX(mThunk16Attr):    .word      _ThunkAttr - ASM_PFX(m16Start)
  54 ASM_PFX(m16Gdt):          .word      _NullSeg - ASM_PFX(m16Start)
  55 ASM_PFX(m16GdtrBase):     .word      _16GdtrBase - ASM_PFX(m16Start)
  56 ASM_PFX(mTransition):     .word      _EntryPoint - ASM_PFX(m16Start)
  57
  58     .text
  59
  60 ASM_PFX(m16Start):
  61
  62 SavedGdt:    .space 10
  63
  64 #------------------------------------------------------------------------------
  65 # _BackFromUserCode() takes control in real mode after 'retf' has been executed
  66 # by user code. It will be shadowed to somewhere in memory below 1MB.
  67 #------------------------------------------------------------------------------
  68 .globl ASM_PFX(BackFromUserCode)
  69 ASM_PFX(BackFromUserCode):
  70     #
  71     # The order of saved registers on the stack matches the order they appears
  72     # in IA32_REGS structure. This facilitates wrapper function to extract them
  73     # into that structure.
  74     #
  75     # Some instructions for manipulation of segment registers have to be written
  76     # in opcode since 64-bit MASM prevents accesses to those registers.
  77     #
  78     .byte 0x16                          # push ss
  79     .byte 0xe                           # push cs
  80     .byte 0x66
  81     call    @Base                       # push eip
  82 @Base:
  83     .byte 0x66
  84     pushq   $0                          # reserved high order 32 bits of EFlags
  85     .byte 0x66, 0x9c                    # pushfd actually
  86     cli                                 # disable interrupts
  87     push    %gs
  88     push    %fs
  89     .byte 6                             # push es
  90     .byte 0x1e                          # push ds
  91     .byte 0x66,0x60                     # pushad
  92     .byte 0x66,0xba                     # mov edx, imm32
  93 _ThunkAttr:  .space  4
  94     testb   $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl
  95     jz      @1
  96     movl    $0x15cd2401,%eax            # mov ax, 2401h & int 15h
  97     cli                                 # disable interrupts
  98     jnc     @2
  99 @1:
 100     testb   $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl
 101     jz      @2
 102     inb     $0x92,%al
 103     orb     $2,%al
 104     outb    %al, $0x92                   # deactivate A20M#
 105 @2:
 106     movl    %ss,%eax
 107     lea     IA32_REGS_SIZE(%esp), %bp
 108     #
 109     # rsi in the following 2 instructions is indeed bp in 16-bit code
 110     #
 111     movw    %bp, (_ESP - IA32_REGS_SIZE)(%rsi)
 112     .byte 0x66
 113     movl    (_EIP - IA32_REGS_SIZE)(%rsi), %ebx
 114     shlw    $4,%ax                      # shl eax, 4
 115     addw    %ax,%bp                     # add ebp, eax
 116     movw    %cs,%ax
 117     shlw    $4,%ax
 118     lea     (@64BitCode - @Base)(%ebx, %eax), %ax
 119     .byte 0x66,0x2e,0x89,0x87           # mov cs:[bx + (@64Eip - @Base)], eax
 120     .word   @64Eip - @Base
 121     .byte 0x66,0xb8                     # mov eax, imm32
 122 SavedCr4:   .space  4
 123     movq    %rax, %cr4
 124     #
 125     # rdi in the instruction below is indeed bx in 16-bit code
 126     #
 127     .byte 0x66,0x2e                     # 2eh is "cs:" segment override
 128     lgdt    (SavedGdt - @Base)(%rdi)
 129     .byte 0x66
 130     movl    $0xc0000080,%ecx
 131     rdmsr
 132     orb     $1,%ah
 133     wrmsr
 134     .byte 0x66,0xb8                     # mov eax, imm32
 135 SavedCr0:    .space      4
 136     movq    %rax, %cr0
 137     .byte 0x66,0xea                     # jmp far cs:@64Bit
 138 @64Eip:      .space      4
 139 SavedCs:     .space      2
 140 @64BitCode:
 141     movq     %r8, %rsp
 142     ret
 143
 144 _EntryPoint: .long      ASM_PFX(ToUserCode) - ASM_PFX(m16Start)
 145              .word      CODE16
 146 _16Gdtr:     .word      GDT_SIZE - 1
 147 _16GdtrBase: .quad      _NullSeg
 148 _16Idtr:     .word      0x3ff
 149              .long      0
 150
 151 #------------------------------------------------------------------------------
 152 # _ToUserCode() takes control in real mode before passing control to user code.
 153 # It will be shadowed to somewhere in memory below 1MB.
 154 #------------------------------------------------------------------------------
 155 .globl ASM_PFX(ToUserCode)
 156 ASM_PFX(ToUserCode):
 157     movl    %edx,%ss                    # set new segment selectors
 158     movl    %edx,%ds
 159     movl    %edx,%es
 160     movl    %edx,%fs
 161     movl    %edx,%gs
 162     .byte 0x66
 163     movl    $0xc0000080,%ecx
 164     movq    %rax, %cr0
 165     rdmsr
 166     andb    $0b11111110, %ah
 167     wrmsr
 168     movq    %rbp, %cr4
 169     movl    %esi,%ss                    # set up 16-bit stack segment
 170     movw    %bx,%sp                     # set up 16-bit stack pointer
 171     .byte 0x66                          # make the following call 32-bit
 172     call    @Base1                       # push eip
 173 @Base1:
 174     popw    %bp                         # ebp <- address of @Base1
 175     pushq   (IA32_REGS_SIZE + 2)(%esp)
 176     lea     0x0c(%rsi), %eax
 177     pushq   %rax
 178     lret                                # execution begins at next instruction
 179 @RealMode:
 180     .byte 0x66,0x2e                     # CS and operand size override
 181     lidt    (_16Idtr - @Base1)(%rsi)
 182     .byte 0x66,0x61                     # popad
 183     .byte 0x1f                          # pop ds
 184     .byte 0x7                           # pop es
 185     .byte 0x0f, 0xa1                    # pop fs
 186     .byte 0x0f, 0xa9                    # pop gs
 187     .byte 0x66, 0x9d                    # popfd
 188     leaw    4(%esp),%sp                 # skip high order 32 bits of EFlags
 189     .byte 0x66                          # make the following retf 32-bit
 190     lret                                # transfer control to user code
 191
 192 .equ  CODE16,  ASM_PFX(16Code) - .
 193 .equ  DATA16,  ASM_PFX(16Data) - .
 194 .equ  DATA32,  ASM_PFX(32Data) - .
 195
 196 _NullSeg:   .quad      0
 197 ASM_PFX(16Code):
 198             .word -1
 199             .word 0
 200             .byte 0
 201             .byte 0x9b
 202             .byte 0x8f                  # 16-bit segment, 4GB limit
 203             .byte 0
 204 ASM_PFX(16Data):
 205             .word -1
 206             .word 0
 207             .byte 0
 208             .byte 0x93
 209             .byte 0x8f                  # 16-bit segment, 4GB limit
 210             .byte 0
 211 ASM_PFX(32Data):
 212             .word -1
 213             .word 0
 214             .byte 0
 215             .byte 0x93
 216             .byte 0xcf                  # 16-bit segment, 4GB limit
 217             .byte 0
 218
 219 .equ  GDT_SIZE, . - ASM_PFX(NullSeg)
 220
 221 #------------------------------------------------------------------------------
 222 # IA32_REGISTER_SET *
 223 # EFIAPI
 224 # InternalAsmThunk16 (
 225 #   IN      IA32_REGISTER_SET         *RegisterSet,
 226 #   IN OUT  VOID                      *Transition
 227 #   );
 228 #------------------------------------------------------------------------------
 229 # MISMATCH: "InternalAsmThunk16  PROC    USES    rbp rbx rsi rdi"
 230
 231 .globl ASM_PFX(InternalAsmThunk16)
 232 ASM_PFX(InternalAsmThunk16):
 233     pushq   %rbp
 234     pushq   %rbx
 235     pushq   %rsi
 236     pushq   %rdi
 237
 238     movl    %ds, %r10d                  # r9 ~ r11 are not accessible in 16-bit
 239     movl    %es, %r11d                  # so use them for saving seg registers
 240     movl    %ss, %r9d
 241     .byte   0x0f, 0xa0                  #push   fs
 242     .byte   0x0f, 0xa8                  #push   gs
 243     movq    %rcx, %rsi
 244     movzwl  _SS(%rsi), %r8d
 245     movl    _ESP(%rsi), %edi
 246     lea     -(IA32_REGS_SIZE + 4)(%edi), %rdi
 247     imul    $16, %r8d, %eax
 248     movl    %edi,%ebx                   # ebx <- stack for 16-bit code
 249     pushq   $(IA32_REGS_SIZE / 4)
 250     addl    %eax,%edi                   # edi <- linear address of 16-bit stack
 251     popq    %rcx
 252     rep
 253     movsl                               # copy RegSet
 254     lea     (SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx
 255     movl    %edx,%eax                   # eax <- transition code address
 256     andl    $0xf,%edx
 257     shll    $12,%eax                    # segment address in high order 16 bits
 258     lea     (_BackFromUserCode - ASM_PFX(m16Start))(%rdx), %ax
 259     stosl                               # [edi] <- return address of user code
 260     sgdt    (SavedGdt - SavedCr4)(%rcx)
 261     sidt    0x38(%rsp)
 262     movq    %cr0, %rax
 263     movl    %eax, (SavedCr0 - SavedCr4)(%rcx)
 264     andl    $0x7ffffffe,%eax            # clear PE, PG bits
 265     movq    %cr4, %rbp
 266     movl    %ebp, (%rcx)                # save CR4 in SavedCr4
 267     andl    $0x300,%ebp                 # clear all but PCE and OSFXSR bits
 268     movl    %r8d, %esi                  # esi <- 16-bit stack segment
 269     .byte      0x6a, DATA32
 270     popq    %rdx
 271     lgdt    (_16Gdtr - SavedCr4)(%rcx)
 272     movl    %edx,%ss
 273     pushfq
 274     lea     -8(%rdx), %edx
 275     lea     @RetFromRealMode, %r8
 276     pushq   %r8
 277     movl    %cs, %r8d
 278     movw    %r8w, (SavedCs - SavedCr4)(%rcx)
 279     movq     %rsp, %r8
 280     .byte   0xff, 0x69                  #  jmp (_EntryPoint - SavedCr4)(%rcx)
 281     .byte   _EntryPoint - SavedCr4
 282 @RetFromRealMode:
 283     popfq
 284     lidt    0x38(%rsp)
 285     lea     -IA32_REGS_SIZE(%rbp), %eax
 286     .byte 0x0f, 0xa9                    # pop gs
 287     .byte 0x0f, 0xa1                    # pop fs
 288     movl    %r9d, %ss
 289     movl    %r11d, %es
 290     movl    %r10d, %ds
 291
 292     popq    %rdi
 293     popq    %rsi
 294     popq    %rbx
 295     popq    %rbp
 296
 297     ret