2 Header file for IDE Bus Driver's Data Structures
4 Copyright (c) 2006, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
31 #define bit10 (1 << 10)
32 #define bit11 (1 << 11)
33 #define bit12 (1 << 12)
34 #define bit13 (1 << 13)
35 #define bit14 (1 << 14)
36 #define bit15 (1 << 15)
37 #define bit16 (1 << 16)
38 #define bit17 (1 << 17)
39 #define bit18 (1 << 18)
40 #define bit19 (1 << 19)
41 #define bit20 (1 << 20)
42 #define bit21 (1 << 21)
43 #define bit22 (1 << 22)
44 #define bit23 (1 << 23)
45 #define bit24 (1 << 24)
46 #define bit25 (1 << 25)
47 #define bit26 (1 << 26)
48 #define bit27 (1 << 27)
49 #define bit28 (1 << 28)
50 #define bit29 (1 << 29)
51 #define bit30 (1 << 30)
52 #define bit31 (1 << 31)
57 #define STALL_1_MILLI_SECOND 1000 // stall 1 ms
58 #define STALL_1_SECOND 1000000 // stall 1 second
72 IdeMagnetic
, /* ZIP Drive or LS120 Floppy Drive */
73 IdeCdRom
, /* ATAPI CDROM */
74 IdeHardDisk
, /* Hard Disk */
75 Ide48bitAddressingHardDisk
, /* Hard Disk larger than 120GB */
83 UINT16 Command
; /* when write */
84 UINT16 Status
; /* when read */
88 UINT16 Error
; /* when read */
89 UINT16 Feature
; /* when write */
90 } IDE_ERROR_OR_FEATURE
;
93 UINT16 AltStatus
; /* when read */
94 UINT16 DeviceControl
; /* when write */
95 } IDE_AltStatus_OR_DeviceControl
;
102 IDE_ERROR_OR_FEATURE Reg1
;
108 IDE_CMD_OR_STATUS Reg
;
110 IDE_AltStatus_OR_DeviceControl Alt
;
114 UINT16 BusMasterBaseAddr
;
115 } IDE_BASE_REGISTERS
;
118 // IDE registers' base addresses
121 UINT16 CommandBlockBaseAddr
;
122 UINT16 ControlBlockBaseAddr
;
123 UINT16 BusMasterBaseAddr
;
124 } IDE_REGISTERS_BASE_ADDR
;
127 // Bit definitions in Programming Interface byte of the Class Code field
128 // in PCI IDE controller's Configuration Space
130 #define IDE_PRIMARY_OPERATING_MODE bit0
131 #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR bit1
132 #define IDE_SECONDARY_OPERATING_MODE bit2
133 #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR bit3
136 // IDE registers bit definitions
142 #define BBK_ERR bit7 /* Bad block detected */
143 #define UNC_ERR bit6 /* Uncorrectable Data */
144 #define MC_ERR bit5 /* Media Change */
145 #define IDNF_ERR bit4 /* ID Not Found */
146 #define MCR_ERR bit3 /* Media Change Requested */
147 #define ABRT_ERR bit2 /* Aborted Command */
148 #define TK0NF_ERR bit1 /* Track 0 Not Found */
149 #define AMNF_ERR bit0 /* Address Mark Not Found */
154 #define LBA_MODE bit6
169 #define BSY bit7 /* Controller Busy */
170 #define DRDY bit6 /* Drive Ready */
171 #define DWF bit5 /* Drive Write Fault */
172 #define DSC bit4 /* Disk Seek Complete */
173 #define DRQ bit3 /* Data Request */
174 #define CORR bit2 /* Corrected Data */
175 #define IDX bit1 /* Index */
176 #define ERR bit0 /* Error */
179 // Device Control Reg
181 #define SRST bit2 /* Software Reset */
182 #define IEN_L bit1 /* Interrupt Enable #*/
187 #define BMIC_nREAD bit3
188 #define BMIC_START bit0
189 #define BMIS_INTERRUPT bit2
190 #define BMIS_ERROR bit1
192 #define BMICP_OFFSET 0x00
193 #define BMISP_OFFSET 0x02
194 #define BMIDP_OFFSET 0x04
195 #define BMICS_OFFSET 0x08
196 #define BMISS_OFFSET 0x0A
197 #define BMIDS_OFFSET 0x0C
200 // Time Out Value For IDE Device Polling
204 // ATATIMEOUT is used for waiting time out for ATA device
210 #define ATATIMEOUT 1000
213 // ATAPITIMEOUT is used for waiting operation
214 // except read and write time out for ATAPI device
220 #define ATAPITIMEOUT 1000
223 // ATAPILONGTIMEOUT is used for waiting read and
224 // write operation timeout for ATAPI device
230 #define CDROMLONGTIMEOUT 2000
235 #define ATAPILONGTIMEOUT 5000
240 #define ATA_INITIALIZE_DEVICE 0x91
245 #define IDENTIFY_DRIVE_CMD 0xec
246 #define READ_BUFFER_CMD 0xe4
247 #define READ_SECTORS_CMD 0x20
248 #define READ_SECTORS_WITH_RETRY_CMD 0x21
249 #define READ_LONG_CMD 0x22
250 #define READ_LONG_WITH_RETRY_CMD 0x23
252 // Class 1 - Atapi6 enhanced commands
254 #define READ_SECTORS_EXT_CMD 0x24
259 #define FORMAT_TRACK_CMD 0x50
260 #define WRITE_BUFFER_CMD 0xe8
261 #define WRITE_SECTORS_CMD 0x30
262 #define WRITE_SECTORS_WITH_RETRY_CMD 0x31
263 #define WRITE_LONG_CMD 0x32
264 #define WRITE_LONG_WITH_RETRY_CMD 0x33
265 #define WRITE_VERIFY_CMD 0x3c
267 // Class 2 - Atapi6 enhanced commands
269 #define WRITE_SECTORS_EXT_CMD 0x34
274 #define ACK_MEDIA_CHANGE_CMD 0xdb
275 #define BOOT_POST_BOOT_CMD 0xdc
276 #define BOOT_PRE_BOOT_CMD 0xdd
277 #define CHECK_POWER_MODE_CMD 0x98
278 #define CHECK_POWER_MODE_CMD_ALIAS 0xe5
279 #define DOOR_LOCK_CMD 0xde
280 #define DOOR_UNLOCK_CMD 0xdf
281 #define EXEC_DRIVE_DIAG_CMD 0x90
282 #define IDLE_CMD_ALIAS 0x97
283 #define IDLE_CMD 0xe3
284 #define IDLE_IMMEDIATE_CMD 0x95
285 #define IDLE_IMMEDIATE_CMD_ALIAS 0xe1
286 #define INIT_DRIVE_PARAM_CMD 0x91
287 #define RECALIBRATE_CMD 0x10 /* aliased to 1x */
288 #define READ_DRIVE_STATE_CMD 0xe9
289 #define SET_MULTIPLE_MODE_CMD 0xC6
290 #define READ_DRIVE_STATE_CMD 0xe9
291 #define READ_VERIFY_CMD 0x40
292 #define READ_VERIFY_WITH_RETRY_CMD 0x41
293 #define SEEK_CMD 0x70 /* aliased to 7x */
294 #define SET_FEATURES_CMD 0xef
295 #define STANDBY_CMD 0x96
296 #define STANDBY_CMD_ALIAS 0xe2
297 #define STANDBY_IMMEDIATE_CMD 0x94
298 #define STANDBY_IMMEDIATE_CMD_ALIAS 0xe0
303 #define READ_DMA_CMD 0xc8
304 #define READ_DMA_WITH_RETRY_CMD 0xc9
305 #define READ_DMA_EXT_CMD 0x25
306 #define WRITE_DMA_CMD 0xca
307 #define WRITE_DMA_WITH_RETRY_CMD 0xcb
308 #define WRITE_DMA_EXT_CMD 0x35
313 #define READ_MULTIPLE_CMD 0xc4
314 #define REST_CMD 0xe7
315 #define RESTORE_DRIVE_STATE_CMD 0xea
316 #define SET_SLEEP_MODE_CMD 0x99
317 #define SET_SLEEP_MODE_CMD_ALIAS 0xe6
318 #define WRITE_MULTIPLE_CMD 0xc5
319 #define WRITE_SAME_CMD 0xe9
322 // Class 6 - Host protected area access feature set
324 #define READ_NATIVE_MAX_ADDRESS_CMD 0xf8
325 #define SET_MAX_ADDRESS_CMD 0xf9
328 // Class 6 - ATA/ATAPI-6 enhanced commands
330 #define READ_NATIVE_MAX_ADDRESS_EXT_CMD 0x27
331 #define SET_MAX_ADDRESS_CMD_EXT 0x37
334 // Class 6 - SET_MAX related sub command (in feature register)
336 #define PARTIES_SET_MAX_ADDRESS_SUB_CMD 0x00
337 #define PARTIES_SET_PASSWORD_SUB_CMD 0x01
338 #define PARTIES_LOCK_SUB_CMD 0x02
339 #define PARTIES_UNLOCK_SUB_CMD 0x03
340 #define PARTIES_FREEZE_SUB_CMD 0x04
345 #define ATA_SMART_CMD 0xb0
346 #define ATA_CONSTANT_C2 0xc2
347 #define ATA_CONSTANT_4F 0x4f
348 #define ATA_SMART_ENABLE_OPERATION 0xd8
349 #define ATA_SMART_RETURN_STATUS 0xda
352 // Error codes for Exec Drive Diag
354 #define DRIV_DIAG_NO_ERROR (0x01)
355 #define DRIV_DIAG_FORMATTER_ERROR (0x02)
356 #define DRIV_DIAG_DATA_BUFFER_ERROR (0x03)
357 #define DRIV_DIAG_ECC_CKT_ERRROR (0x04)
358 #define DRIV_DIAG_UP_ERROR (0x05)
359 #define DRIV_DIAG_SLAVE_DRV_ERROR (0x80) /* aliased to 0x8x */
362 // Codes for Format Track
364 #define FORMAT_GOOD_SECTOR (0x00)
365 #define FORMAT_SUSPEND_ALLOC (0x01)
366 #define FORMAT_REALLOC_SECTOR (0x02)
367 #define FORMAT_MARK_SECTOR_DEFECTIVE (0x03)
373 #define ID_CONFIG_RESERVED0 bit0
374 #define ID_CONFIG_HARD_SECTORED_DRIVE bit1
375 #define ID_CONFIG_SOFT_SECTORED_DRIVE bit2
376 #define ID_CONFIG_NON_MFM bit3
377 #define ID_CONFIG_15uS_HEAD_SWITCHING bit4
378 #define ID_CONFIG_SPINDLE_MOTOR_CONTROL bit5
379 #define ID_CONFIG_HARD_DRIVE bit6
380 #define ID_CONFIG_CHANGEABLE_MEDIUM bit7
381 #define ID_CONFIG_DATA_RATE_TO_5MHZ bit8
382 #define ID_CONFIG_DATA_RATE_5_TO_10MHZ bit9
383 #define ID_CONFIG_DATA_RATE_ABOVE_10MHZ bit10
384 #define ID_CONFIG_MOTOR_SPEED_TOLERANCE_ABOVE_0_5_PERC bit11
385 #define ID_CONFIG_DATA_CLK_OFFSET_AVAIL bit12
386 #define ID_CONFIG_TRACK_OFFSET_AVAIL bit13
387 #define ID_CONFIG_SPEED_TOLERANCE_GAP_NECESSARY bit14
388 #define ID_CONFIG_RESERVED1 bit15
390 #define ID_DOUBLE_WORD_IO_POSSIBLE bit01
391 #define ID_LBA_SUPPORTED bit9
392 #define ID_DMA_SUPPORTED bit8
394 #define SET_FEATURE_ENABLE_8BIT_TRANSFER (0x01)
395 #define SET_FEATURE_ENABLE_WRITE_CACHE (0x02)
396 #define SET_FEATURE_TRANSFER_MODE (0x03)
397 #define SET_FEATURE_WRITE_SAME_WRITE_SPECIFIC_AREA (0x22)
398 #define SET_FEATURE_DISABLE_RETRIES (0x33)
400 // for Read & Write Longs
402 #define SET_FEATURE_VENDOR_SPEC_ECC_LENGTH (0x44)
403 #define SET_FEATURE_PLACE_NO_OF_CACHE_SEGMENTS_IN_SECTOR_NO_REG (0x54)
404 #define SET_FEATURE_DISABLE_READ_AHEAD (0x55)
405 #define SET_FEATURE_MAINTAIN_PARAM_AFTER_RESET (0x66)
406 #define SET_FEATURE_DISABLE_ECC (0x77)
407 #define SET_FEATURE_DISABLE_8BIT_TRANSFER (0x81)
408 #define SET_FEATURE_DISABLE_WRITE_CACHE (0x82)
409 #define SET_FEATURE_ENABLE_ECC (0x88)
410 #define SET_FEATURE_ENABLE_RETRIES (0x99)
411 #define SET_FEATURE_ENABLE_READ_AHEAD (0xaa)
412 #define SET_FEATURE_SET_SECTOR_CNT_REG_AS_NO_OF_READ_AHEAD_SECTORS (0xab)
413 #define SET_FEATURE_ALLOW_REST_MODE (0xac)
415 // for Read & Write Longs
417 #define SET_FEATURE_4BYTE_ECC (0xbb)
418 #define SET_FEATURE_DEFALUT_FEATURES_ON_SOFTWARE_RESET (0xcc)
419 #define SET_FEATURE_WRITE_SAME_TO_WRITE_ENTIRE_MEDIUM (0xdd)
421 #define BLOCK_TRANSFER_MODE (0x00)
422 #define SINGLE_WORD_DMA_TRANSFER_MODE (0x10)
423 #define MULTI_WORD_DMA_TRANSFER_MODE (0x20)
424 #define TRANSFER_MODE_MASK (0x07) // 3 LSBs
429 #define DEFAULT_DRIVE (0x00)
430 #define DEFAULT_CMD (0xa0)
432 // default content of device control register, disable INT
434 #define DEFAULT_CTL (0x0a)
435 #define DEFAULT_IDE_BM_IO_BASE_ADR (0xffa0)
438 // ATAPI6 related data structure definition
442 // The maximum sectors count in 28 bit addressing mode
444 #define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff
447 // Move the IDENTIFY section to DXE\Protocol\IdeControllerInit
453 #define ATAPI_SOFT_RESET_CMD 0x08
454 #define ATAPI_PACKET_CMD 0xA0
455 #define PACKET_CMD 0xA0
456 #define ATAPI_IDENTIFY_DEVICE_CMD 0xA1
457 #define ATAPI_SERVICE_CMD 0xA2
460 // ATAPI Packet Command
477 } TEST_UNIT_READY_CMD
;
481 UINT8 reserved_1
: 4;
485 UINT8 allocation_length
;
497 UINT8 reserved_1
: 4;
501 UINT8 allocation_length
;
513 UINT8 reserved_1
: 4;
516 UINT8 page_control
: 4;
521 UINT8 parameter_list_length_hi
;
522 UINT8 parameter_list_length_lo
;
530 UINT8 reserved_1
: 5;
552 UINT8 allocation_length_hi
;
553 UINT8 allocation_length_lo
;
557 } READ_FORMAT_CAP_CMD
;
561 TEST_UNIT_READY_CMD TestUnitReady
;
563 REQUEST_SENSE_CMD RequestSence
;
565 MODE_SENSE_CMD ModeSense
;
566 READ_FORMAT_CAP_CMD ReadFormatCapacity
;
567 } ATAPI_PACKET_COMMAND
;
570 UINT32 RegionBaseAddr
;
575 #define MAX_DMA_EXT_COMMAND_SECTORS 0x10000
576 #define MAX_DMA_COMMAND_SECTORS 0x100
581 // Packet Command Code
583 #define TEST_UNIT_READY 0x00
585 #define REQUEST_SENSE 0x03
586 #define FORMAT_UNIT 0x04
587 #define REASSIGN_BLOCKS 0x07
589 #define START_STOP_UNIT 0x1B
590 #define PREVENT_ALLOW_MEDIA_REMOVAL 0x1E
591 #define READ_FORMAT_CAPACITY 0x23
592 #define OLD_FORMAT_UNIT 0x24
593 #define READ_CAPACITY 0x25
595 #define WRITE_10 0x2A
597 #define SEND_DIAGNOSTICS 0x3D
598 #define WRITE_VERIFY 0x2E
600 #define READ_DEFECT_DATA 0x37
601 #define WRITE_BUFFER 0x38
602 #define READ_BUFFER 0x3C
603 #define READ_LONG 0x3E
604 #define WRITE_LONG 0x3F
605 #define MODE_SELECT 0x55
606 #define MODE_SENSE 0x5A
608 #define WRITE_12 0xAA
609 #define MAX_ATAPI_BYTE_COUNT (0xfffe)
614 #define REQUEST_SENSE_ERROR (0x70)
615 #define SK_NO_SENSE (0x0)
616 #define SK_RECOVERY_ERROR (0x1)
617 #define SK_NOT_READY (0x2)
618 #define SK_MEDIUM_ERROR (0x3)
619 #define SK_HARDWARE_ERROR (0x4)
620 #define SK_ILLEGAL_REQUEST (0x5)
621 #define SK_UNIT_ATTENTION (0x6)
622 #define SK_DATA_PROTECT (0x7)
623 #define SK_BLANK_CHECK (0x8)
624 #define SK_VENDOR_SPECIFIC (0x9)
625 #define SK_RESERVED_A (0xA)
626 #define SK_ABORT (0xB)
627 #define SK_RESERVED_C (0xC)
628 #define SK_OVERFLOW (0xD)
629 #define SK_MISCOMPARE (0xE)
630 #define SK_RESERVED_F (0xF)
633 // Additional Sense Codes
635 #define ASC_NOT_READY (0x04)
636 #define ASC_MEDIA_ERR1 (0x10)
637 #define ASC_MEDIA_ERR2 (0x11)
638 #define ASC_MEDIA_ERR3 (0x14)
639 #define ASC_MEDIA_ERR4 (0x30)
640 #define ASC_MEDIA_UPSIDE_DOWN (0x06)
641 #define ASC_INVALID_CMD (0x20)
642 #define ASC_LBA_OUT_OF_RANGE (0x21)
643 #define ASC_INVALID_FIELD (0x24)
644 #define ASC_WRITE_PROTECTED (0x27)
645 #define ASC_MEDIA_CHANGE (0x28)
646 #define ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */
647 #define ASC_ILLEGAL_FIELD (0x26)
648 #define ASC_NO_MEDIA (0x3A)
649 #define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
652 // Additional Sense Code Qualifier
654 #define ASCQ_IN_PROGRESS (0x01)
656 #define SETFEATURE TRUE
657 #define CLEARFEATURE FALSE
660 // ATAPI Data structure
665 UINT8 peripheral_type
;
668 UINT8 response_data_format
;
673 UINT8 vendor_info
[8];
674 UINT8 product_id
[12];
675 UINT8 eeprom_product_code
[4];
676 UINT8 firmware_rev_level
[4];
677 UINT8 firmware_sub_rev_level
[1];
681 UINT8 max_capacity_hi
;
682 UINT8 max_capacity_mid
;
683 UINT8 max_capacity_lo
;
684 UINT8 reserved_43_95
[95 - 43 + 1];
688 UINT8 peripheral_type
;
691 UINT8 response_data_format
;
696 UINT8 vendor_info
[8];
697 UINT8 product_id
[16];
698 UINT8 product_revision_level
[4];
699 UINT8 vendor_specific
[20];
700 UINT8 reserved_56_95
[40];
701 } CDROM_INQUIRY_DATA
;
704 UINT8 error_code
: 7;
708 UINT8 reserved_21
: 1;
710 UINT8 reserved_22
: 2;
711 UINT8 vendor_specific_3
;
712 UINT8 vendor_specific_4
;
713 UINT8 vendor_specific_5
;
714 UINT8 vendor_specific_6
;
715 UINT8 addnl_sense_length
; // n - 7
716 UINT8 vendor_specific_8
;
717 UINT8 vendor_specific_9
;
718 UINT8 vendor_specific_10
;
719 UINT8 vendor_specific_11
;
720 UINT8 addnl_sense_code
; // mandatory
721 UINT8 addnl_sense_code_qualifier
; // mandatory
722 UINT8 field_replaceable_unit_code
; // optional
727 // Followed by additional sense bytes : FIXME
729 } REQUEST_SENSE_DATA
;
740 } READ_CAPACITY_DATA
;
746 UINT8 Capacity_Length
;
752 UINT8 reserved_9
: 6;
756 } READ_FORMAT_CAPACITY_DATA
;
761 // PIO mode definition
764 ATA_PIO_MODE_BELOW_2
,
771 // Multi word DMA definition
780 // UDMA mode definition
791 #define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00
792 #define ATA_MODE_CATEGORY_FLOW_PIO 0x01
793 #define ATA_MODE_CATEGORY_MDMA 0x04
794 #define ATA_MODE_CATEGORY_UDMA 0x08
799 UINT8 ModeNumber
: 3;
800 UINT8 ModeCategory
: 5;
806 UINT8 MultipleSector
;
811 // IORDY Sample Point field value
819 // Recovery Time field value
821 #define RECVY_4_CLK 0
822 #define RECVY_3_CLK 1
823 #define RECVY_2_CLK 2
824 #define RECVY_1_CLK 3
827 // Slave IDE Timing Register Enable
832 // DMA Timing Enable Only Select 1
837 // Pre-fetch and Posting Enable Select 1
842 // IORDY Sample Point Enable Select 1
847 // Fast Timing Bank Drive Select 1
852 // DMA Timing Enable Only Select 0
857 // Pre-fetch and Posting Enable Select 0
862 // IOREY Sample Point Enable Select 0
867 // Fast Timing Bank Drive Select 0