Fix capitalization.
[mirror_edk2.git] / EdkModulePkg / Bus / Pci / Uhci / Dxe / uhci.h
1 /*++
2
3 Copyright (c) 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 Module Name:
13
14 Uhci.h
15
16 Abstract:
17
18
19 Revision History
20 --*/
21
22 #ifndef _UHCI_H
23 #define _UHCI_H
24
25 /*
26 * Universal Host Controller Interface data structures and defines
27 */
28
29 #include <IndustryStandard/pci22.h>
30
31 #define EFI_D_UHCI EFI_D_INFO
32
33 //
34 // stall time
35 //
36 #define STALL_1_MILLI_SECOND 1000
37 #define STALL_1_SECOND 1000 * STALL_1_MILLI_SECOND
38
39 #define FORCE_GLOBAL_RESUME_TIME 20 * STALL_1_MILLI_SECOND
40
41 #define ROOT_PORT_REST_TIME 50 * STALL_1_MILLI_SECOND
42
43 #define PORT_RESET_RECOVERY_TIME 10 * STALL_1_MILLI_SECOND
44
45 //
46 // 50 ms
47 //
48 #define INTERRUPT_POLLING_TIME 50 * 1000 * 10
49
50 //
51 // UHCI IO Space Address Register Register locates at
52 // offset 20 ~ 23h of PCI Configuration Space (UHCI spec, Revision 1.1),
53 // so, its BAR Index is 4.
54 //
55 #define USB_BAR_INDEX 4
56
57 //
58 // One memory block uses 1 page (common buffer for QH,TD use.)
59 //
60 #define NORMAL_MEMORY_BLOCK_UNIT_IN_PAGES 1
61
62
63 #define bit(a) 1 << (a)
64
65 //
66 // ////////////////////////////////////////////////////////////////////////
67 //
68 // Universal Host Controller Registers Definitions
69 //
70 //////////////////////////////////////////////////////////////////////////
71 extern UINT16 USBBaseAddr;
72
73 /* Command register */
74 #define USBCMD 0 /* Command Register Offset 00-01h */
75 #define USBCMD_RS bit (0) /* Run/Stop */
76 #define USBCMD_HCRESET bit (1) /* Host reset */
77 #define USBCMD_GRESET bit (2) /* Global reset */
78 #define USBCMD_EGSM bit (3) /* Global Suspend Mode */
79 #define USBCMD_FGR bit (4) /* Force Global Resume */
80 #define USBCMD_SWDBG bit (5) /* SW Debug mode */
81 #define USBCMD_CF bit (6) /* Config Flag (sw only) */
82 #define USBCMD_MAXP bit (7) /* Max Packet (0 = 32, 1 = 64) */
83
84 /* Status register */
85 #define USBSTS 2 /* Status Register Offset 02-03h */
86 #define USBSTS_USBINT bit (0) /* Interrupt due to IOC */
87 #define USBSTS_ERROR bit (1) /* Interrupt due to error */
88 #define USBSTS_RD bit (2) /* Resume Detect */
89 #define USBSTS_HSE bit (3) /* Host System Error*/
90 #define USBSTS_HCPE bit (4) /* Host Controller Process Error*/
91 #define USBSTS_HCH bit (5) /* HC Halted */
92
93 /* Interrupt enable register */
94 #define USBINTR 4 /* Interrupt Enable Register 04-05h */
95 #define USBINTR_TIMEOUT bit (0) /* Timeout/CRC error enable */
96 #define USBINTR_RESUME bit (1) /* Resume interrupt enable */
97 #define USBINTR_IOC bit (2) /* Interrupt On Complete enable */
98 #define USBINTR_SP bit (3) /* Short packet interrupt enable */
99
100 /* Frame Number Register Offset 06-08h */
101 #define USBFRNUM 6
102
103 /* Frame List Base Address Register Offset 08-0Bh */
104 #define USBFLBASEADD 8
105
106 /* Start of Frame Modify Register Offset 0Ch */
107 #define USBSOF 0x0c
108
109 /* USB port status and control registers */
110 #define USBPORTSC1 0x10 /*Port 1 offset 10-11h */
111 #define USBPORTSC2 0x12 /*Port 2 offset 12-13h */
112
113 #define USBPORTSC_CCS bit (0) /* Current Connect Status*/
114 #define USBPORTSC_CSC bit (1) /* Connect Status Change */
115 #define USBPORTSC_PED bit (2) /* Port Enable / Disable */
116 #define USBPORTSC_PEDC bit (3) /* Port Enable / Disable Change */
117 #define USBPORTSC_LSL bit (4) /* Line Status Low bit*/
118 #define USBPORTSC_LSH bit (5) /* Line Status High bit*/
119 #define USBPORTSC_RD bit (6) /* Resume Detect */
120 #define USBPORTSC_LSDA bit (8) /* Low Speed Device Attached */
121 #define USBPORTSC_PR bit (9) /* Port Reset */
122 #define USBPORTSC_SUSP bit (12) /* Suspend */
123
124 /* PCI Configuration Registers for USB */
125
126 //
127 // Class Code Register offset
128 //
129 #define CLASSC 0x09
130 //
131 // USB IO Space Base Address Register offset
132 //
133 #define USBBASE 0x20
134
135 //
136 // USB legacy Support
137 //
138 #define USB_EMULATION 0xc0
139
140 //
141 // USB Base Class Code,Sub-Class Code and Programming Interface.
142 //
143 #define PCI_CLASSC_PI_UHCI 0x00
144
145 #define SETUP_PACKET_ID 0x2D
146 #define INPUT_PACKET_ID 0x69
147 #define OUTPUT_PACKET_ID 0xE1
148 #define ERROR_PACKET_ID 0x55
149
150 //
151 // ////////////////////////////////////////////////////////////////////////
152 //
153 // USB Transfer Mechanism Data Structures
154 //
155 //////////////////////////////////////////////////////////////////////////
156 #pragma pack(1)
157 //
158 // USB Class Code structure
159 //
160 typedef struct {
161 UINT8 PI;
162 UINT8 SubClassCode;
163 UINT8 BaseCode;
164 } USB_CLASSC;
165
166 typedef struct {
167 UINT32 QHHorizontalTerminate : 1;
168 UINT32 QHHorizontalQSelect : 1;
169 UINT32 QHHorizontalRsvd : 2;
170 UINT32 QHHorizontalPtr : 28;
171 UINT32 QHVerticalTerminate : 1;
172 UINT32 QHVerticalQSelect : 1;
173 UINT32 QHVerticalRsvd : 2;
174 UINT32 QHVerticalPtr : 28;
175 } QUEUE_HEAD;
176
177 typedef struct {
178 UINT32 TDLinkPtrTerminate : 1;
179 UINT32 TDLinkPtrQSelect : 1;
180 UINT32 TDLinkPtrDepthSelect : 1;
181 UINT32 TDLinkPtrRsvd : 1;
182 UINT32 TDLinkPtr : 28;
183 UINT32 TDStatusActualLength : 11;
184 UINT32 TDStatusRsvd : 5;
185 UINT32 TDStatus : 8;
186 UINT32 TDStatusIOC : 1;
187 UINT32 TDStatusIOS : 1;
188 UINT32 TDStatusLS : 1;
189 UINT32 TDStatusErr : 2;
190 UINT32 TDStatusSPD : 1;
191 UINT32 TDStatusRsvd2 : 2;
192 UINT32 TDTokenPID : 8;
193 UINT32 TDTokenDevAddr : 7;
194 UINT32 TDTokenEndPt : 4;
195 UINT32 TDTokenDataToggle : 1;
196 UINT32 TDTokenRsvd : 1;
197 UINT32 TDTokenMaxLen : 11;
198 UINT32 TDBufferPtr;
199 } TD;
200
201 #pragma pack()
202
203 typedef struct {
204 QUEUE_HEAD QH;
205 VOID *ptrNext;
206 VOID *ptrDown;
207 VOID *ptrNextIntQH; // for interrupt transfer's special use
208 VOID *LoopPtr;
209 } QH_STRUCT;
210
211 typedef struct {
212 TD TDData;
213 UINT8 *pTDBuffer;
214 VOID *ptrNextTD;
215 VOID *ptrNextQH;
216 UINT16 TDBufferLength;
217 UINT16 reserved;
218 } TD_STRUCT;
219
220 //
221 // ////////////////////////////////////////////////////////////////////////
222 //
223 // Universal Host Controller Device Data Structure
224 //
225 //////////////////////////////////////////////////////////////////////////
226 #define USB_HC_DEV_FROM_THIS(a) CR (a, USB_HC_DEV, UsbHc, USB_HC_DEV_SIGNATURE)
227
228 #define USB_HC_DEV_SIGNATURE EFI_SIGNATURE_32 ('u', 'h', 'c', 'i')
229 #define INTERRUPT_LIST_SIGNATURE EFI_SIGNATURE_32 ('i', 'n', 't', 's')
230 typedef struct {
231 UINTN Signature;
232
233 LIST_ENTRY Link;
234 UINT8 DevAddr;
235 UINT8 EndPoint;
236 UINT8 DataToggle;
237 UINT8 Reserved[5];
238 TD_STRUCT *PtrFirstTD;
239 QH_STRUCT *PtrQH;
240 UINTN DataLen;
241 UINTN PollInterval;
242 VOID *Mapping;
243 UINT8 *DataBuffer; // allocated host memory, not mapped memory
244 EFI_ASYNC_USB_TRANSFER_CALLBACK InterruptCallBack;
245 VOID *InterruptContext;
246 } INTERRUPT_LIST;
247
248 #define INTERRUPT_LIST_FROM_LINK(a) CR (a, INTERRUPT_LIST, Link, INTERRUPT_LIST_SIGNATURE)
249
250 typedef struct {
251 UINT32 FrameListPtrTerminate : 1;
252 UINT32 FrameListPtrQSelect : 1;
253 UINT32 FrameListRsvd : 2;
254 UINT32 FrameListPtr : 28;
255
256 } FRAMELIST_ENTRY;
257
258 typedef struct _MEMORY_MANAGE_HEADER {
259 UINT8 *BitArrayPtr;
260 UINTN BitArraySizeInBytes;
261 UINT8 *MemoryBlockPtr;
262 UINTN MemoryBlockSizeInBytes;
263 VOID *Mapping;
264 struct _MEMORY_MANAGE_HEADER *Next;
265 } MEMORY_MANAGE_HEADER;
266
267 typedef struct {
268 UINTN Signature;
269 EFI_USB_HC_PROTOCOL UsbHc;
270 EFI_PCI_IO_PROTOCOL *PciIo;
271
272 //
273 // local data
274 //
275 LIST_ENTRY InterruptListHead;
276 FRAMELIST_ENTRY *FrameListEntry;
277 VOID *FrameListMapping;
278 MEMORY_MANAGE_HEADER *MemoryHeader;
279 EFI_EVENT InterruptTransTimer;
280 EFI_UNICODE_STRING_TABLE *ControllerNameTable;
281
282 } USB_HC_DEV;
283
284 extern EFI_DRIVER_BINDING_PROTOCOL gUhciDriverBinding;
285 extern EFI_COMPONENT_NAME_PROTOCOL gUhciComponentName;
286
287 EFI_STATUS
288 WriteUHCCommandReg (
289 IN EFI_PCI_IO_PROTOCOL *PciIo,
290 IN UINT32 CmdAddrOffset,
291 IN UINT16 UsbCmd
292 );
293
294 EFI_STATUS
295 ReadUHCCommandReg (
296 IN EFI_PCI_IO_PROTOCOL *PciIo,
297 IN UINT32 CmdAddrOffset,
298 IN OUT UINT16 *Data
299 );
300
301 EFI_STATUS
302 WriteUHCStatusReg (
303 IN EFI_PCI_IO_PROTOCOL *PciIo,
304 IN UINT32 StatusAddrOffset,
305 IN UINT16 UsbSts
306 );
307
308 EFI_STATUS
309 ReadUHCStatusReg (
310 IN EFI_PCI_IO_PROTOCOL *PciIo,
311 IN UINT32 StatusAddrOffset,
312 IN OUT UINT16 *Data
313 );
314
315 EFI_STATUS
316 ClearStatusReg (
317 IN EFI_PCI_IO_PROTOCOL *PciIo,
318 IN UINT32 StatusAddrOffset
319 );
320
321 EFI_STATUS
322 ReadUHCFrameNumberReg (
323 IN EFI_PCI_IO_PROTOCOL *PciIo,
324 IN UINT32 FrameNumAddrOffset,
325 IN OUT UINT16 *Data
326 );
327
328 EFI_STATUS
329 WriteUHCFrameListBaseReg (
330 IN EFI_PCI_IO_PROTOCOL *PciIo,
331 IN UINT32 FlBaseAddrOffset,
332 IN UINT32 UsbFrameListBaseAddr
333 );
334
335 EFI_STATUS
336 ReadRootPortReg (
337 IN EFI_PCI_IO_PROTOCOL *PciIo,
338 IN UINT32 PortAddrOffset,
339 IN OUT UINT16 *Data
340 );
341
342 EFI_STATUS
343 WriteRootPortReg (
344 IN EFI_PCI_IO_PROTOCOL *PciIo,
345 IN UINT32 PortAddrOffset,
346 IN UINT16 ControlBits
347 );
348
349 EFI_STATUS
350 WaitForUHCHalt (
351 IN EFI_PCI_IO_PROTOCOL *PciIo,
352 IN UINT32 StatusRegAddr,
353 IN UINTN Timeout
354 );
355
356 BOOLEAN
357 IsStatusOK (
358 IN EFI_PCI_IO_PROTOCOL *PciIo,
359 IN UINT32 StatusRegAddr
360 );
361
362 BOOLEAN
363 IsHostSysOrProcessErr (
364 IN EFI_PCI_IO_PROTOCOL *PciIo,
365 IN UINT32 StatusRegAddr
366 );
367
368 //
369 // This routine programs the USB frame number register. We assume that the
370 // HC schedule execution is stopped.
371 //
372 EFI_STATUS
373 SetFrameNumberReg (
374 IN EFI_PCI_IO_PROTOCOL *PciIo,
375 IN UINT32 FRNUMAddr,
376 IN UINT16 Index
377 );
378
379 UINT16
380 GetCurrentFrameNumber (
381 IN EFI_PCI_IO_PROTOCOL *PciIo,
382 IN UINT32 FRNUMAddr
383 );
384
385 EFI_STATUS
386 SetFrameListBaseAddress (
387 IN EFI_PCI_IO_PROTOCOL *PciIo,
388 IN UINT32 FLBASEADDRReg,
389 IN UINT32 Addr
390 );
391
392 UINT32
393 GetFrameListBaseAddress (
394 IN EFI_PCI_IO_PROTOCOL *PciIo,
395 IN UINT32 FLBAddr
396 );
397
398 EFI_STATUS
399 CreateFrameList (
400 IN USB_HC_DEV *HcDev,
401 IN UINT32 FLBASEADDRReg
402 );
403
404 EFI_STATUS
405 FreeFrameListEntry (
406 IN USB_HC_DEV *UhcDev
407 );
408
409 VOID
410 InitFrameList (
411 IN USB_HC_DEV *HcDev
412 );
413
414
415 EFI_STATUS
416 CreateQH (
417 IN USB_HC_DEV *HcDev,
418 OUT QH_STRUCT **pptrQH
419 );
420
421 VOID
422 SetQHHorizontalLinkPtr (
423 IN QH_STRUCT *ptrQH,
424 IN VOID *ptrNext
425 );
426
427 VOID *
428 GetQHHorizontalLinkPtr (
429 IN QH_STRUCT *ptrQH
430 );
431
432 VOID
433 SetQHHorizontalQHorTDSelect (
434 IN QH_STRUCT *ptrQH,
435 IN BOOLEAN bQH
436 );
437
438 VOID
439 SetQHHorizontalValidorInvalid (
440 IN QH_STRUCT *ptrQH,
441 IN BOOLEAN bValid
442 );
443
444 VOID
445 SetQHVerticalLinkPtr (
446 IN QH_STRUCT *ptrQH,
447 IN VOID *ptrNext
448 );
449
450 VOID *
451 GetQHVerticalLinkPtr (
452 IN QH_STRUCT *ptrQH
453 );
454
455 VOID
456 SetQHVerticalQHorTDSelect (
457 IN QH_STRUCT *ptrQH,
458 IN BOOLEAN bQH
459 );
460
461 BOOLEAN
462 IsQHHorizontalQHSelect (
463 IN QH_STRUCT *ptrQH
464 );
465
466 VOID
467 SetQHVerticalValidorInvalid (
468 IN QH_STRUCT *ptrQH,
469 IN BOOLEAN bValid
470 );
471
472 BOOLEAN
473 GetQHVerticalValidorInvalid (
474 IN QH_STRUCT *ptrQH
475 );
476
477 EFI_STATUS
478 AllocateTDStruct (
479 IN USB_HC_DEV *HcDev,
480 OUT TD_STRUCT **ppTDStruct
481 );
482 /*++
483
484 Routine Description:
485
486 Allocate TD Struct
487
488 Arguments:
489
490 HcDev - USB_HC_DEV
491 ppTDStruct - place to store TD_STRUCT pointer
492 Returns:
493
494 EFI_SUCCESS
495
496 --*/
497
498 EFI_STATUS
499 CreateTD (
500 IN USB_HC_DEV *HcDev,
501 OUT TD_STRUCT **pptrTD
502 );
503 /*++
504
505 Routine Description:
506
507 Create TD
508
509 Arguments:
510
511 HcDev - USB_HC_DEV
512 pptrTD - TD_STRUCT pointer to store
513
514 Returns:
515
516 EFI_OUT_OF_RESOURCES - Can't allocate resources
517 EFI_SUCCESS - Success
518
519 --*/
520
521
522 EFI_STATUS
523 GenSetupStageTD (
524 IN USB_HC_DEV *HcDev,
525 IN UINT8 DevAddr,
526 IN UINT8 Endpoint,
527 IN BOOLEAN bSlow,
528 IN UINT8 *pDevReq,
529 IN UINT8 RequestLen,
530 OUT TD_STRUCT **ppTD
531 );
532 /*++
533
534 Routine Description:
535
536 Generate Setup Stage TD
537
538 Arguments:
539
540 HcDev - USB_HC_DEV
541 DevAddr - Device address
542 Endpoint - Endpoint number
543 bSlow - Full speed or low speed
544 pDevReq - Device request
545 RequestLen - Request length
546 ppTD - TD_STRUCT to return
547 Returns:
548
549 EFI_OUT_OF_RESOURCES - Can't allocate memory
550 EFI_SUCCESS - Success
551
552 --*/
553
554 EFI_STATUS
555 GenDataTD (
556 IN USB_HC_DEV *HcDev,
557 IN UINT8 DevAddr,
558 IN UINT8 Endpoint,
559 IN UINT8 *pData,
560 IN UINT8 Len,
561 IN UINT8 PktID,
562 IN UINT8 Toggle,
563 IN BOOLEAN bSlow,
564 OUT TD_STRUCT **ppTD
565 );
566 /*++
567
568 Routine Description:
569
570 Generate Data Stage TD
571
572 Arguments:
573
574 HcDev - USB_HC_DEV
575 DevAddr - Device address
576 Endpoint - Endpoint number
577 pData - Data buffer
578 Len - Data length
579 PktID - Packet ID
580 Toggle - Data toggle value
581 bSlow - Full speed or low speed
582 ppTD - TD_STRUCT to return
583 Returns:
584
585 EFI_OUT_OF_RESOURCES - Can't allocate memory
586 EFI_SUCCESS - Success
587
588 --*/
589
590 EFI_STATUS
591 CreateStatusTD (
592 IN USB_HC_DEV *HcDev,
593 IN UINT8 DevAddr,
594 IN UINT8 Endpoint,
595 IN UINT8 PktID,
596 IN BOOLEAN bSlow,
597 OUT TD_STRUCT **ppTD
598 );
599 /*++
600
601 Routine Description:
602
603 Generate Setup Stage TD
604
605 Arguments:
606
607 HcDev - USB_HC_DEV
608 DevAddr - Device address
609 Endpoint - Endpoint number
610 bSlow - Full speed or low speed
611 pDevReq - Device request
612 RequestLen - Request length
613 ppTD - TD_STRUCT to return
614 Returns:
615
616 EFI_OUT_OF_RESOURCES - Can't allocate memory
617 EFI_SUCCESS - Success
618
619 --*/
620
621 VOID
622 SetTDLinkPtrValidorInvalid (
623 IN TD_STRUCT *ptrTDStruct,
624 IN BOOLEAN bValid
625 );
626
627 VOID
628 SetTDLinkPtrQHorTDSelect (
629 IN TD_STRUCT *ptrTDStruct,
630 IN BOOLEAN bQH
631 );
632
633 VOID
634 SetTDLinkPtrDepthorBreadth (
635 IN TD_STRUCT *ptrTDStruct,
636 IN BOOLEAN bDepth
637 );
638
639 VOID
640 SetTDLinkPtr (
641 IN TD_STRUCT *ptrTDStruct,
642 IN VOID *ptrNext
643 );
644
645 VOID *
646 GetTDLinkPtr (
647 IN TD_STRUCT *ptrTDStruct
648 );
649
650 VOID
651 EnableorDisableTDShortPacket (
652 IN TD_STRUCT *ptrTDStruct,
653 IN BOOLEAN bEnable
654 );
655
656 VOID
657 SetTDControlErrorCounter (
658 IN TD_STRUCT *ptrTDStruct,
659 IN UINT8 nMaxErrors
660 );
661
662 VOID
663 SetTDLoworFullSpeedDevice (
664 IN TD_STRUCT *ptrTDStruct,
665 IN BOOLEAN bLowSpeedDevice
666 );
667
668 VOID
669 SetTDControlIsochronousorNot (
670 IN TD_STRUCT *ptrTDStruct,
671 IN BOOLEAN bIsochronous
672 );
673
674 VOID
675 SetorClearTDControlIOC (
676 IN TD_STRUCT *ptrTDStruct,
677 IN BOOLEAN bSet
678 );
679
680 VOID
681 SetTDStatusActiveorInactive (
682 IN TD_STRUCT *ptrTDStruct,
683 IN BOOLEAN bActive
684 );
685
686 UINT16
687 SetTDTokenMaxLength (
688 IN TD_STRUCT *ptrTDStruct,
689 IN UINT16 nMaxLen
690 );
691
692 VOID
693 SetTDTokenDataToggle1 (
694 IN TD_STRUCT *ptrTDStruct
695 );
696
697 VOID
698 SetTDTokenDataToggle0 (
699 IN TD_STRUCT *ptrTDStruct
700 );
701
702 UINT8
703 GetTDTokenDataToggle (
704 IN TD_STRUCT *ptrTDStruct
705 );
706
707 VOID
708 SetTDTokenEndPoint (
709 IN TD_STRUCT *ptrTDStruct,
710 IN UINTN nEndPoint
711 );
712
713 VOID
714 SetTDTokenDeviceAddress (
715 IN TD_STRUCT *ptrTDStruct,
716 IN UINTN nDevAddr
717 );
718
719 VOID
720 SetTDTokenPacketID (
721 IN TD_STRUCT *ptrTDStruct,
722 IN UINT8 nPID
723 );
724
725 VOID
726 SetTDDataBuffer (
727 IN TD_STRUCT *ptrTDStruct
728 );
729
730 BOOLEAN
731 IsTDStatusActive (
732 IN TD_STRUCT *ptrTDStruct
733 );
734
735 BOOLEAN
736 IsTDStatusStalled (
737 IN TD_STRUCT *ptrTDStruct
738 );
739
740 BOOLEAN
741 IsTDStatusBufferError (
742 IN TD_STRUCT *ptrTDStruct
743 );
744
745 BOOLEAN
746 IsTDStatusBabbleError (
747 IN TD_STRUCT *ptrTDStruct
748 );
749
750 BOOLEAN
751 IsTDStatusNAKReceived (
752 IN TD_STRUCT *ptrTDStruct
753 );
754
755 BOOLEAN
756 IsTDStatusCRCTimeOutError (
757 IN TD_STRUCT *ptrTDStruct
758 );
759
760 BOOLEAN
761 IsTDStatusBitStuffError (
762 IN TD_STRUCT *ptrTDStruct
763 );
764
765 UINT16
766 GetTDStatusActualLength (
767 IN TD_STRUCT *ptrTDStruct
768 );
769
770 UINT16
771 GetTDTokenMaxLength (
772 IN TD_STRUCT *ptrTDStruct
773 );
774
775 UINT8
776 GetTDTokenEndPoint (
777 IN TD_STRUCT *ptrTDStruct
778 );
779
780 UINT8
781 GetTDTokenDeviceAddress (
782 IN TD_STRUCT *ptrTDStruct
783 );
784
785 UINT8
786 GetTDTokenPacketID (
787 IN TD_STRUCT *ptrTDStruct
788 );
789
790 UINT8 *
791 GetTDDataBuffer (
792 IN TD_STRUCT *ptrTDStruct
793 );
794
795 BOOLEAN
796 GetTDLinkPtrValidorInvalid (
797 IN TD_STRUCT *ptrTDStruct
798 );
799
800 UINTN
801 CountTDsNumber (
802 IN TD_STRUCT *ptrFirstTD
803 );
804
805 VOID
806 LinkTDToQH (
807 IN QH_STRUCT *ptrQH,
808 IN TD_STRUCT *ptrTD
809 );
810
811 VOID
812 LinkTDToTD (
813 IN TD_STRUCT *ptrPreTD,
814 IN TD_STRUCT *ptrTD
815 );
816
817 VOID
818 SetorClearCurFrameListTerminate (
819 IN FRAMELIST_ENTRY *pCurEntry,
820 IN BOOLEAN bSet
821 );
822
823 VOID
824 SetCurFrameListQHorTD (
825 IN FRAMELIST_ENTRY *pCurEntry,
826 IN BOOLEAN bQH
827 );
828
829 BOOLEAN
830 GetCurFrameListTerminate (
831 IN FRAMELIST_ENTRY *pCurEntry
832 );
833
834 VOID
835 SetCurFrameListPointer (
836 IN FRAMELIST_ENTRY *pCurEntry,
837 IN UINT8 *ptr
838 );
839
840 VOID *
841 GetCurFrameListPointer (
842 IN FRAMELIST_ENTRY *pCurEntry
843 );
844
845 VOID
846 LinkQHToFrameList (
847 IN FRAMELIST_ENTRY *pEntry,
848 IN UINT16 FrameListIndex,
849 IN QH_STRUCT *ptrQH
850 );
851 /*++
852
853 Routine Description:
854
855 Link QH To Frame List
856
857 Arguments:
858
859 pEntry - FRAMELIST_ENTRY
860 FrameListIndex - Frame List Index
861 PtrQH - QH to link
862 Returns:
863
864 VOID
865
866 --*/
867 VOID
868 DeleteQHTDs (
869 IN FRAMELIST_ENTRY *pEntry,
870 IN QH_STRUCT *ptrQH,
871 IN TD_STRUCT *ptrFirstTD,
872 IN UINT16 FrameListIndex,
873 IN BOOLEAN SearchOther
874 );
875
876 VOID
877 DelLinkSingleQH (
878 IN USB_HC_DEV *HcDev,
879 IN QH_STRUCT *ptrQH,
880 IN UINT16 FrameListIndex,
881 IN BOOLEAN SearchOther,
882 IN BOOLEAN Delete
883 );
884
885 VOID
886 DeleteQueuedTDs (
887 IN USB_HC_DEV *HcDev,
888 IN TD_STRUCT *ptrFirstTD
889 );
890
891 VOID
892 InsertQHTDToINTList (
893 IN USB_HC_DEV *HcDev,
894 IN QH_STRUCT *ptrQH,
895 IN TD_STRUCT *ptrFirstTD,
896 IN UINT8 DeviceAddress,
897 IN UINT8 EndPointAddress,
898 IN UINT8 DataToggle,
899 IN UINTN DataLength,
900 IN UINTN PollingInterval,
901 IN VOID *Mapping,
902 IN UINT8 *DataBuffer,
903 IN EFI_ASYNC_USB_TRANSFER_CALLBACK CallBackFunction,
904 IN VOID *Context
905 );
906 /*++
907 Routine Description:
908 Insert QH and TD To Interrupt List
909 Arguments:
910
911 HcDev - USB_HC_DEV
912 PtrQH - QH_STRUCT
913 PtrFirstTD - First TD_STRUCT
914 DeviceAddress - Device Address
915 EndPointAddress - EndPoint Address
916 DataToggle - Data Toggle
917 DataLength - Data length
918 PollingInterval - Polling Interval when inserted to frame list
919 Mapping - Mapping alue
920 DataBuffer - Data buffer
921 CallBackFunction- CallBackFunction after interrupt transfeer
922 Context - CallBackFunction Context passed as function parameter
923 Returns:
924 EFI_SUCCESS - Sucess
925 EFI_INVALID_PARAMETER - Paremeter is error
926
927 --*/
928
929 EFI_STATUS
930 DeleteAsyncINTQHTDs (
931 IN USB_HC_DEV *HcDev,
932 IN UINT8 DeviceAddress,
933 IN UINT8 EndPointAddress,
934 OUT UINT8 *DataToggle
935 );
936 /*++
937 Routine Description:
938
939 Delete Async INT QH and TDs
940 Arguments:
941
942 HcDev - USB_HC_DEV
943 DeviceAddress - Device Address
944 EndPointAddress - EndPoint Address
945 DataToggle - Data Toggle
946
947 Returns:
948 EFI_SUCCESS - Sucess
949 EFI_INVALID_PARAMETER - Paremeter is error
950
951 --*/
952 BOOLEAN
953 CheckTDsResults (
954 IN TD_STRUCT *ptrTD,
955 IN UINTN RequiredLen,
956 OUT UINT32 *Result,
957 OUT UINTN *ErrTDPos,
958 OUT UINTN *ActualTransferSize
959 );
960 /*++
961
962 Routine Description:
963
964 Check TDs Results
965
966 Arguments:
967
968 PtrTD - TD_STRUCT to check
969 RequiredLen - Required Len
970 Result - Transfer result
971 ErrTDPos - Error TD Position
972 ActualTransferSize - Actual Transfer Size
973
974 Returns:
975
976 TRUE - Sucess
977 FALSE - Fail
978
979 --*/
980 VOID
981 ExecuteAsyncINTTDs (
982 IN USB_HC_DEV *HcDev,
983 IN INTERRUPT_LIST *ptrList,
984 OUT UINT32 *Result,
985 OUT UINTN *ErrTDPos,
986 OUT UINTN *ActualLen
987 ) ;
988 /*++
989
990 Routine Description:
991
992 Execute Async Interrupt TDs
993
994 Arguments:
995
996 HcDev - USB_HC_DEV
997 PtrList - INTERRUPT_LIST
998 Result - Transfer result
999 ErrTDPos - Error TD Position
1000 ActualTransferSize - Actual Transfer Size
1001
1002 Returns:
1003
1004 VOID
1005
1006 --*/
1007 VOID
1008 UpdateAsyncINTQHTDs (
1009 IN INTERRUPT_LIST *ptrList,
1010 IN UINT32 Result,
1011 IN UINT32 ErrTDPos
1012 );
1013 /*++
1014
1015 Routine Description:
1016
1017 Update Async Interrupt QH and TDs
1018
1019 Arguments:
1020
1021 PtrList - INTERRUPT_LIST
1022 Result - Transfer reslut
1023 ErrTDPos - Error TD Position
1024
1025 Returns:
1026
1027 VOID
1028
1029 --*/
1030 VOID
1031 ReleaseInterruptList (
1032 IN USB_HC_DEV *HcDev,
1033 IN LIST_ENTRY *ListHead
1034 );
1035 /*++
1036
1037 Routine Description:
1038
1039 Release Interrupt List
1040 Arguments:
1041
1042 HcDev - USB_HC_DEV
1043 ListHead - List head
1044
1045 Returns:
1046
1047 VOID
1048
1049 --*/
1050 EFI_STATUS
1051 ExecuteControlTransfer (
1052 IN USB_HC_DEV *HcDev,
1053 IN TD_STRUCT *ptrTD,
1054 IN UINT32 wIndex,
1055 OUT UINTN *ActualLen,
1056 IN UINTN TimeOut,
1057 OUT UINT32 *TransferResult
1058 );
1059 /*++
1060
1061 Routine Description:
1062
1063 Execute Control Transfer
1064
1065 Arguments:
1066
1067 HcDev - USB_HC_DEV
1068 PtrTD - TD_STRUCT
1069 wIndex - No use
1070 ActualLen - Actual transfered Len
1071 TimeOut - TimeOut value in milliseconds
1072 TransferResult - Transfer result
1073 Returns:
1074
1075 EFI_SUCCESS - Sucess
1076 EFI_DEVICE_ERROR - Error
1077
1078
1079 --*/
1080 EFI_STATUS
1081 ExecBulkorSyncInterruptTransfer (
1082 IN USB_HC_DEV *HcDev,
1083 IN TD_STRUCT *ptrTD,
1084 IN UINT32 wIndex,
1085 OUT UINTN *ActualLen,
1086 OUT UINT8 *DataToggle,
1087 IN UINTN TimeOut,
1088 OUT UINT32 *TransferResult
1089 );
1090 /*++
1091
1092 Routine Description:
1093
1094 Execute Bulk or SyncInterrupt Transfer
1095
1096 Arguments:
1097
1098 HcDev - USB_HC_DEV
1099 PtrTD - TD_STRUCT
1100 wIndex - No use
1101 ActualLen - Actual transfered Len
1102 DataToggle - Data Toggle
1103 TimeOut - TimeOut value in milliseconds
1104 TransferResult - Transfer result
1105 Returns:
1106
1107 EFI_SUCCESS - Sucess
1108 EFI_DEVICE_ERROR - Error
1109 --*/
1110
1111 EFI_STATUS
1112 InitializeMemoryManagement (
1113 IN USB_HC_DEV *HcDev
1114 );
1115
1116 EFI_STATUS
1117 CreateMemoryBlock (
1118 IN USB_HC_DEV *HcDev,
1119 IN MEMORY_MANAGE_HEADER **MemoryHeader,
1120 IN UINTN MemoryBlockSizeInPages
1121 );
1122
1123 EFI_STATUS
1124 FreeMemoryHeader (
1125 IN USB_HC_DEV *HcDev,
1126 IN MEMORY_MANAGE_HEADER *MemoryHeader
1127 );
1128
1129 EFI_STATUS
1130 UhciAllocatePool (
1131 IN USB_HC_DEV *UhcDev,
1132 IN UINT8 **Pool,
1133 IN UINTN AllocSize
1134 );
1135
1136 VOID
1137 UhciFreePool (
1138 IN USB_HC_DEV *HcDev,
1139 IN UINT8 *Pool,
1140 IN UINTN AllocSize
1141 );
1142
1143 VOID
1144 InsertMemoryHeaderToList (
1145 IN MEMORY_MANAGE_HEADER *MemoryHeader,
1146 IN MEMORY_MANAGE_HEADER *NewMemoryHeader
1147 );
1148
1149 EFI_STATUS
1150 AllocMemInMemoryBlock (
1151 IN MEMORY_MANAGE_HEADER *MemoryHeader,
1152 IN VOID **Pool,
1153 IN UINTN NumberOfMemoryUnit
1154 );
1155
1156 BOOLEAN
1157 IsMemoryBlockEmptied (
1158 IN MEMORY_MANAGE_HEADER *MemoryHeaderPtr
1159 );
1160
1161 VOID
1162 DelinkMemoryBlock (
1163 IN MEMORY_MANAGE_HEADER *FirstMemoryHeader,
1164 IN MEMORY_MANAGE_HEADER *FreeMemoryHeader
1165 );
1166
1167 EFI_STATUS
1168 DelMemoryManagement (
1169 IN USB_HC_DEV *HcDev
1170 );
1171
1172 VOID
1173 EnableMaxPacketSize (
1174 IN USB_HC_DEV *HcDev
1175 );
1176
1177 VOID
1178 CleanUsbTransactions (
1179 IN USB_HC_DEV *HcDev
1180 );
1181
1182 VOID
1183 TurnOffUSBEmulation (
1184 IN EFI_PCI_IO_PROTOCOL *PciIo
1185 );
1186
1187 #endif