EmbeddedPkg/Drivers/Isp1761UsbDxe/Isp1761UsbDxe.h

   1 /** @file
   2
   3   Copyright (c) 2013-2014, ARM Ltd. All rights reserved.<BR>
   4
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #ifndef __ISP1761_USB_DXE_H__
  10 #define __ISP1761_USB_DXE_H__
  11
  12 #define ISP1761_USB_BASE FixedPcdGet32 (PcdIsp1761BaseAddress)
  13
  14 #define READ_REG32(Offset) MmioRead32 (ISP1761_USB_BASE + Offset)
  15 #define READ_REG16(Offset) (UINT16) READ_REG32 (Offset)
  16 #define WRITE_REG32(Offset, Val)  MmioWrite32 (ISP1761_USB_BASE + Offset, Val)
  17 #define WRITE_REG16(Offset, Val)  MmioWrite32 (ISP1761_USB_BASE + Offset, (UINT32) Val)
  18 #define WRITE_REG8(Offset, Val)   MmioWrite32 (ISP1761_USB_BASE + Offset, (UINT32) Val)
  19
  20 // Max packet size in bytes (For Full Speed USB 64 is the only valid value)
  21 #define MAX_PACKET_SIZE_CONTROL     64
  22
  23 #define MAX_PACKET_SIZE_BULK        512
  24
  25 // 8 Endpoints, in and out. Don't count the Endpoint 0 setup buffer
  26 #define ISP1761_NUM_ENDPOINTS               16
  27
  28 // Endpoint Indexes
  29 #define ISP1761_EP0SETUP                    0x20
  30 #define ISP1761_EP0RX                       0x00
  31 #define ISP1761_EP0TX                       0x01
  32 #define ISP1761_EP1RX                       0x02
  33 #define ISP1761_EP1TX                       0x03
  34
  35 // DcInterrupt bits
  36 #define ISP1761_DC_INTERRUPT_BRESET         BIT0
  37 #define ISP1761_DC_INTERRUPT_SOF            BIT1
  38 #define ISP1761_DC_INTERRUPT_PSOF           BIT2
  39 #define ISP1761_DC_INTERRUPT_SUSP           BIT3
  40 #define ISP1761_DC_INTERRUPT_RESUME         BIT4
  41 #define ISP1761_DC_INTERRUPT_HS_STAT        BIT5
  42 #define ISP1761_DC_INTERRUPT_DMA            BIT6
  43 #define ISP1761_DC_INTERRUPT_VBUS           BIT7
  44 #define ISP1761_DC_INTERRUPT_EP0SETUP       BIT8
  45 #define ISP1761_DC_INTERRUPT_EP0RX          BIT10
  46 #define ISP1761_DC_INTERRUPT_EP0TX          BIT11
  47 #define ISP1761_DC_INTERRUPT_EP1RX          BIT12
  48 #define ISP1761_DC_INTERRUPT_EP1TX          BIT13
  49 // All valid peripheral controller interrupts
  50 #define ISP1761_DC_INTERRUPT_MASK           0x003FFFDFF
  51
  52 #define ISP1761_ADDRESS                     0x200
  53 #define ISP1761_ADDRESS_DEVEN               BIT7
  54
  55 #define ISP1761_MODE                        0x20C
  56 #define ISP1761_MODE_DATA_BUS_WIDTH         BIT8
  57 #define ISP1761_MODE_CLKAON                 BIT7
  58 #define ISP1761_MODE_SFRESET                BIT4
  59 #define ISP1761_MODE_WKUPCS                 BIT2
  60
  61 #define ISP1761_ENDPOINT_MAX_PACKET_SIZE    0x204
  62
  63 #define ISP1761_ENDPOINT_TYPE               0x208
  64 #define ISP1761_ENDPOINT_TYPE_NOEMPKT       BIT4
  65 #define ISP1761_ENDPOINT_TYPE_ENABLE        BIT3
  66
  67 #define ISP1761_INTERRUPT_CONFIG            0x210
  68 // Interrupt config value to only interrupt on ACK of IN and OUT tokens
  69 #define ISP1761_INTERRUPT_CONFIG_ACK_ONLY   BIT2 | BIT5 | BIT6
  70
  71 #define ISP1761_DC_INTERRUPT                0x218
  72 #define ISP1761_DC_INTERRUPT_ENABLE         0x214
  73
  74 #define ISP1761_CTRL_FUNCTION               0x228
  75 #define ISP1761_CTRL_FUNCTION_VENDP         BIT3
  76 #define ISP1761_CTRL_FUNCTION_DSEN          BIT2
  77 #define ISP1761_CTRL_FUNCTION_STATUS        BIT1
  78
  79 #define ISP1761_DEVICE_UNLOCK               0x27C
  80 #define ISP1761_DEVICE_UNLOCK_MAGIC         0xAA37
  81
  82 #define ISP1761_SW_RESET_REG                0x30C
  83 #define ISP1761_SW_RESET_ALL                BIT0
  84
  85 #define ISP1761_DEVICE_ID                   0x370
  86
  87 #define ISP1761_OTG_CTRL_SET                0x374
  88 #define ISP1761_OTG_CTRL_CLR                OTG_CTRL_SET + 2
  89 #define ISP1761_OTG_CTRL_OTG_DISABLE        BIT10
  90 #define ISP1761_OTG_CTRL_VBUS_CHRG          BIT6
  91 #define ISP1761_OTG_CTRL_VBUS_DISCHRG       BIT5
  92 #define ISP1761_OTG_CTRL_DM_PULLDOWN        BIT2
  93 #define ISP1761_OTG_CTRL_DP_PULLDOWN        BIT1
  94 #define ISP1761_OTG_CTRL_DP_PULLUP          BIT0
  95
  96 #define ISP1761_OTG_STATUS                  0x378
  97 #define ISP1761_OTG_STATUS_B_SESS_END       BIT7
  98 #define ISP1761_OTG_STATUS_A_B_SESS_VLD     BIT1
  99
 100 #define ISP1761_OTG_INTERRUPT_LATCH_SET     0x37C
 101 #define ISP1761_OTG_INTERRUPT_LATCH_CLR     0x37E
 102 #define ISP1761_OTG_INTERRUPT_ENABLE_RISE   0x384
 103
 104 #define ISP1761_DMA_ENDPOINT_INDEX          0x258
 105
 106 #define ISP1761_ENDPOINT_INDEX              0x22c
 107 #define ISP1761_DATA_PORT                   0x220
 108 #define ISP1761_BUFFER_LENGTH               0x21c
 109
 110 // Device ID Values
 111 #define PHILLIPS_VENDOR_ID_VAL 0x04cc
 112 #define ISP1761_PRODUCT_ID_VAL 0x1761
 113 #define ISP1761_DEVICE_ID_VAL ((ISP1761_PRODUCT_ID_VAL << 16) |\
 114                                PHILLIPS_VENDOR_ID_VAL)
 115
 116 #endif //ifndef __ISP1761_USB_DXE_H__