EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h

   1 /** @file
   2 *  Header containing the structure specific to the Silicon Image I3132 Sata PCI card
   3 *
   4 *  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
   5 *
   6 *  SPDX-License-Identifier: BSD-2-Clause-Patent
   7 *
   8 **/
   9
  10 #ifndef __SATASII3132_H
  11 #define __SATASII3132_H
  12
  13 #include <PiDxe.h>
  14
  15 #include <Protocol/AtaPassThru.h>
  16 #include <Protocol/PciIo.h>
  17
  18 #include <Library/UefiLib.h>
  19 #include <Library/DebugLib.h>
  20 #include <Library/PcdLib.h>
  21 #include <Library/BaseMemoryLib.h>
  22 #include <Library/UefiBootServicesTableLib.h>
  23
  24 #include <IndustryStandard/Pci.h>
  25
  26 #define SATA_SII3132_DEVICE_ID      0x3132
  27 #define SATA_SII3132_VENDOR_ID      0x1095
  28
  29 #define SII3132_PORT_SIGNATURE_PMP      0x96690101
  30 #define SII3132_PORT_SIGNATURE_ATAPI    0xEB140101
  31 #define SII3132_PORT_SIGNATURE_ATA      0x00000101
  32
  33 /*
  34  * Silicon Image SiI3132 Registers
  35  */
  36 #define SII3132_GLOBAL_CONTROL_REG              0x40
  37 #define SII3132_GLOBAL_FLASHADDR_REG            0x70
  38
  39 #define SII3132_PORT_STATUS_REG                 0x1000
  40 #define SII3132_PORT_CONTROLSET_REG             0x1000
  41 #define SII3132_PORT_CONTROLCLEAR_REG           0x1004
  42 #define SII3132_PORT_INTSTATUS_REG              0x1008
  43 #define SII3132_PORT_ENABLEINT_REG              0x1010
  44 #define SII3132_PORT_INTCLEAR_REG               0x1014
  45 #define SII3132_PORT_32BITACTIVADDR_REG         0x101C
  46 #define SII3132_PORT_CMDEXECFIFO_REG            0x1020
  47 #define SII3132_PORT_CMDERROR_REG               0x1024
  48 #define SII3132_PORT_ERRCOUNTDECODE             0x1040
  49 #define SII3132_PORT_ERRCOUNTCRC                0x1044
  50 #define SII3132_PORT_ERRCOUNTHANDSHAKE          0x1048
  51 #define SII3132_PORT_SLOTSTATUS_REG             0x1800
  52 #define SII3132_PORT_CMDACTIV_REG               0x1C00
  53 #define SII3132_PORT_SSTATUS_REG                0x1F04
  54
  55 #define SII3132_PORT_CONTROL_RESET              (1 << 0)
  56 #define SII3132_PORT_DEVICE_RESET               (1 << 1)
  57 #define SII3132_PORT_CONTROL_INT                (1 << 2)
  58 #define SII3132_PORT_CONTROL_32BITACTIVATION    (1 << 10)
  59
  60 #define SII3132_PORT_STATUS_PORTREADY           0x80000000
  61
  62 #define SII3132_PORT_INT_CMDCOMPL               (1 << 0)
  63 #define SII3132_PORT_INT_CMDERR                 (1 << 1)
  64 #define SII3132_PORT_INT_PORTRDY                (1 << 2)
  65
  66 #define SATA_SII3132_MAXPORT    2
  67
  68 #define PRB_CTRL_ATA            0x0
  69 #define PRB_CTRL_PROT_OVERRIDE  0x1
  70 #define PRB_CTRL_RESTRANSMIT    0x2
  71 #define PRB_CTRL_EXT_CMD        0x4
  72 #define PRB_CTRL_RCV            0x8
  73 #define PRB_CTRL_PKT_READ       0x10
  74 #define PRB_CTRL_PKT_WRITE      0x20
  75 #define PRB_CTRL_INT_MASK       0x40
  76 #define PRB_CTRL_SRST           0x80
  77
  78 #define PRB_PROT_PACKET         0x01
  79 #define PRB_PROT_LEGACY_QUEUE   0x02
  80 #define PRB_PROT_NATIVE_QUEUE   0x04
  81 #define PRB_PROT_READ           0x08
  82 #define PRB_PROT_WRITE          0x10
  83 #define PRB_PROT_TRANSPARENT    0x20
  84
  85 #define SGE_XCF     (1 << 28)
  86 #define SGE_DRD     (1 << 29)
  87 #define SGE_LNK     (1 << 30)
  88 #define SGE_TRM     0x80000000
  89
  90 typedef struct _SATA_SI3132_SGE {
  91     UINT32      DataAddressLow;
  92     UINT32      DataAddressHigh;
  93     UINT32      DataCount;
  94     UINT32      Attributes;
  95 } SATA_SI3132_SGE;
  96
  97 typedef struct _SATA_SI3132_FIS {
  98     UINT8               FisType;
  99     UINT8               Control;
 100     UINT8               Command;
 101     UINT8               Features;
 102     UINT8               Fis[5 * 4];
 103 } SATA_SI3132_FIS;
 104
 105 typedef struct _SATA_SI3132_PRB {
 106     UINT16              Control;
 107     UINT16              ProtocolOverride;
 108     UINT32              RecTransCount;
 109     SATA_SI3132_FIS     Fis;
 110     SATA_SI3132_SGE     Sge[2];
 111 } SATA_SI3132_PRB;
 112
 113 typedef struct _SATA_SI3132_DEVICE {
 114     LIST_ENTRY                  Link; // This attribute must be the first entry of this structure (to avoid pointer computation)
 115     UINTN                       Index;
 116     struct _SATA_SI3132_PORT    *Port;  //Parent Port
 117     UINT32                      BlockSize;
 118 } SATA_SI3132_DEVICE;
 119
 120 typedef struct _SATA_SI3132_PORT {
 121     UINTN                           Index;
 122     UINTN                           RegBase;
 123     struct _SATA_SI3132_INSTANCE    *Instance;
 124
 125     //TODO: Support Port multiplier
 126     LIST_ENTRY                      Devices;
 127
 128     SATA_SI3132_PRB*                HostPRB;
 129     EFI_PHYSICAL_ADDRESS            PhysAddrHostPRB;
 130     VOID*                           PciAllocMappingPRB;
 131 } SATA_SI3132_PORT;
 132
 133 typedef struct _SATA_SI3132_INSTANCE {
 134     UINTN                       Signature;
 135
 136     SATA_SI3132_PORT            Ports[SATA_SII3132_MAXPORT];
 137
 138     EFI_ATA_PASS_THRU_PROTOCOL  AtaPassThruProtocol;
 139
 140     EFI_PCI_IO_PROTOCOL         *PciIo;
 141 } SATA_SI3132_INSTANCE;
 142
 143 #define SATA_SII3132_SIGNATURE              SIGNATURE_32('s', 'i', '3', '2')
 144 #define INSTANCE_FROM_ATAPASSTHRU_THIS(a)   CR(a, SATA_SI3132_INSTANCE, AtaPassThruProtocol, SATA_SII3132_SIGNATURE)
 145
 146 #define SATA_GLOBAL_READ32(Offset, Value)  PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, Value)
 147 #define SATA_GLOBAL_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, &Value32); }
 148
 149 #define SATA_PORT_READ32(Offset, Value)  PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, Value)
 150 #define SATA_PORT_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, &Value32); }
 151
 152 #define SATA_TRACE(txt)  DEBUG((EFI_D_VERBOSE, "ARM_SATA: " txt "\n"))
 153
 154 extern EFI_COMPONENT_NAME_PROTOCOL  gSataSiI3132ComponentName;
 155 extern EFI_COMPONENT_NAME2_PROTOCOL gSataSiI3132ComponentName2;
 156
 157 /*
 158  * Component Name Protocol Functions
 159  */
 160 EFI_STATUS
 161 EFIAPI
 162 SataSiI3132ComponentNameGetDriverName (
 163   IN  EFI_COMPONENT_NAME_PROTOCOL  *This,
 164   IN  CHAR8                        *Language,
 165   OUT CHAR16                       **DriverName
 166   );
 167
 168 EFI_STATUS
 169 EFIAPI
 170 SataSiI3132ComponentNameGetControllerName (
 171   IN  EFI_COMPONENT_NAME_PROTOCOL                     *This,
 172   IN  EFI_HANDLE                                      ControllerHandle,
 173   IN  EFI_HANDLE                                      ChildHandle        OPTIONAL,
 174   IN  CHAR8                                           *Language,
 175   OUT CHAR16                                          **ControllerName
 176   );
 177
 178 EFI_STATUS SiI3132HwResetPort (SATA_SI3132_PORT *Port);
 179
 180 /*
 181  * Driver Binding Protocol Functions
 182  */
 183 EFI_STATUS
 184 EFIAPI
 185 SataSiI3132DriverBindingSupported (
 186   IN EFI_DRIVER_BINDING_PROTOCOL *This,
 187   IN EFI_HANDLE                  Controller,
 188   IN EFI_DEVICE_PATH_PROTOCOL    *RemainingDevicePath
 189   );
 190
 191 EFI_STATUS
 192 EFIAPI
 193 SataSiI3132DriverBindingStart (
 194   IN EFI_DRIVER_BINDING_PROTOCOL *This,
 195   IN EFI_HANDLE                  Controller,
 196   IN EFI_DEVICE_PATH_PROTOCOL    *RemainingDevicePath
 197   );
 198
 199 EFI_STATUS
 200 EFIAPI
 201 SataSiI3132DriverBindingStop (
 202   IN EFI_DRIVER_BINDING_PROTOCOL *This,
 203   IN EFI_HANDLE                  Controller,
 204   IN UINTN                       NumberOfChildren,
 205   IN EFI_HANDLE                  *ChildHandleBuffer
 206   );
 207
 208 EFI_STATUS SiI3132AtaPassThruCommand (
 209   IN     SATA_SI3132_INSTANCE             *pSataSiI3132Instance,
 210   IN     SATA_SI3132_PORT                 *pSataPort,
 211   IN     UINT16                           PortMultiplierPort,
 212   IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,
 213   IN     EFI_EVENT                        Event OPTIONAL
 214   );
 215
 216 /**
 217  * EFI ATA Pass Thru Protocol
 218  */
 219 EFI_STATUS SiI3132AtaPassThru (
 220   IN     EFI_ATA_PASS_THRU_PROTOCOL       *This,
 221   IN     UINT16                           Port,
 222   IN     UINT16                           PortMultiplierPort,
 223   IN OUT EFI_ATA_PASS_THRU_COMMAND_PACKET *Packet,
 224   IN     EFI_EVENT                        Event OPTIONAL
 225   );
 226
 227 EFI_STATUS SiI3132GetNextPort (
 228   IN EFI_ATA_PASS_THRU_PROTOCOL *This,
 229   IN OUT UINT16                 *Port
 230   );
 231
 232 EFI_STATUS SiI3132GetNextDevice (
 233   IN EFI_ATA_PASS_THRU_PROTOCOL *This,
 234   IN UINT16                     Port,
 235   IN OUT UINT16                 *PortMultiplierPort
 236   );
 237
 238 EFI_STATUS SiI3132BuildDevicePath (
 239   IN     EFI_ATA_PASS_THRU_PROTOCOL *This,
 240   IN     UINT16                     Port,
 241   IN     UINT16                     PortMultiplierPort,
 242   IN OUT EFI_DEVICE_PATH_PROTOCOL   **DevicePath
 243   );
 244
 245 EFI_STATUS SiI3132GetDevice (
 246   IN  EFI_ATA_PASS_THRU_PROTOCOL *This,
 247   IN  EFI_DEVICE_PATH_PROTOCOL   *DevicePath,
 248   OUT UINT16                     *Port,
 249   OUT UINT16                     *PortMultiplierPort
 250   );
 251
 252 EFI_STATUS SiI3132ResetPort (
 253   IN EFI_ATA_PASS_THRU_PROTOCOL *This,
 254   IN UINT16                     Port
 255   );
 256
 257 EFI_STATUS SiI3132ResetDevice (
 258   IN EFI_ATA_PASS_THRU_PROTOCOL *This,
 259   IN UINT16                     Port,
 260   IN UINT16                     PortMultiplierPort
 261   );
 262
 263 #endif