3 Copyright (c) 2006 - 2007, Intel Corporation<BR>
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 Include for Serial Driver
30 #include <FrameworkPei.h>
32 #include <Protocol/IsaIo.h>
33 #include <Protocol/SerialIo.h>
34 #include <Protocol/DevicePath.h>
36 #include <Library/DebugLib.h>
37 #include <Library/UefiDriverEntryPoint.h>
38 #include <Library/BaseLib.h>
39 #include <Library/UefiLib.h>
40 #include <Library/DevicePathLib.h>
41 #include <Library/BaseMemoryLib.h>
42 #include <Library/MemoryAllocationLib.h>
43 #include <Library/UefiBootServicesTableLib.h>
44 #include <Library/ReportStatusCodeLib.h>
45 #include <Library/PcdLib.h>
47 // Driver Binding Externs
49 extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver
;
50 extern EFI_COMPONENT_NAME_PROTOCOL gIsaSerialComponentName
;
53 // Internal Data Structures
55 #define SERIAL_DEV_SIGNATURE EFI_SIGNATURE_32 ('s', 'e', 'r', 'd')
56 #define SERIAL_MAX_BUFFER_SIZE 16
57 #define TIMEOUT_STALL_INTERVAL 10
60 // Name: SERIAL_DEV_FIFO
61 // Purpose: To define Receive FIFO and Transmit FIFO
62 // Context: Used by serial data transmit and receive
64 // First UINT32: The index of the first data in array Data[]
65 // Last UINT32: The index, which you can put a new data into array Data[]
66 // Surplus UINT32: Identify how many data you can put into array Data[]
67 // Data[] UINT8 : An array, which used to store data
73 UINT8 Data
[SERIAL_MAX_BUFFER_SIZE
];
85 // Purpose: To provide device specific information
88 // Signature UINTN: The identity of the serial device
89 // SerialIo SERIAL_IO_PROTOCOL: Serial I/O protocol interface
90 // SerialMode SERIAL_IO_MODE:
91 // DevicePath EFI_DEVICE_PATH_PROTOCOL *: Device path of the serial device
92 // Handle EFI_HANDLE: The handle instance attached to serial device
93 // BaseAddress UINT16: The base address of specific serial device
94 // Receive SERIAL_DEV_FIFO: The FIFO used to store data,
95 // which is received by UART
96 // Transmit SERIAL_DEV_FIFO: The FIFO used to store data,
97 // which you want to transmit by UART
98 // SoftwareLoopbackEnable BOOLEAN:
99 // Type EFI_UART_TYPE: Specify the UART type of certain serial device
105 EFI_SERIAL_IO_PROTOCOL SerialIo
;
106 EFI_SERIAL_IO_MODE SerialMode
;
107 EFI_DEVICE_PATH_PROTOCOL
*DevicePath
;
109 EFI_DEVICE_PATH_PROTOCOL
*ParentDevicePath
;
110 UART_DEVICE_PATH UartDevicePath
;
111 EFI_ISA_IO_PROTOCOL
*IsaIo
;
114 SERIAL_DEV_FIFO Receive
;
115 SERIAL_DEV_FIFO Transmit
;
116 BOOLEAN SoftwareLoopbackEnable
;
117 BOOLEAN HardwareFlowControl
;
119 EFI_UNICODE_STRING_TABLE
*ControllerNameTable
;
122 #include "ComponentName.h"
124 #define SERIAL_DEV_FROM_THIS(a) CR (a, SERIAL_DEV, SerialIo, SERIAL_DEV_SIGNATURE)
129 extern EFI_DRIVER_BINDING_PROTOCOL gSerialControllerDriver
;
132 // Serial Driver Defaults
134 #define SERIAL_PORT_DEFAULT_BAUD_RATE 115200
135 #define SERIAL_PORT_DEFAULT_RECEIVE_FIFO_DEPTH 1
136 #define SERIAL_PORT_DEFAULT_TIMEOUT 1000000
137 #define SERIAL_PORT_DEFAULT_PARITY NoParity
138 #define SERIAL_PORT_DEFAULT_DATA_BITS 8
139 #define SERIAL_PORT_DEFAULT_STOP_BITS 1
140 #define SERIAL_PORT_DEFAULT_CONTROL_MASK 0
143 // (24000000/13)MHz input clock
145 #define SERIAL_PORT_INPUT_CLOCK 1843200
148 // 115200 baud with rounding errors
150 #define SERIAL_PORT_MAX_BAUD_RATE 115400
151 #define SERIAL_PORT_MIN_BAUD_RATE 50
153 #define SERIAL_PORT_MAX_RECEIVE_FIFO_DEPTH 16
154 #define SERIAL_PORT_MIN_TIMEOUT 1 // 1 uS
155 #define SERIAL_PORT_MAX_TIMEOUT 100000000 // 100 seconds
159 #define SERIAL_REGISTER_THR 0 // WO Transmit Holding Register
160 #define SERIAL_REGISTER_RBR 0 // RO Receive Buffer Register
161 #define SERIAL_REGISTER_DLL 0 // R/W Divisor Latch LSB
162 #define SERIAL_REGISTER_DLM 1 // R/W Divisor Latch MSB
163 #define SERIAL_REGISTER_IER 1 // R/W Interrupt Enable Register
164 #define SERIAL_REGISTER_IIR 2 // RO Interrupt Identification Register
165 #define SERIAL_REGISTER_FCR 2 // WO FIFO Cotrol Register
166 #define SERIAL_REGISTER_LCR 3 // R/W Line Control Register
167 #define SERIAL_REGISTER_MCR 4 // R/W Modem Control Register
168 #define SERIAL_REGISTER_LSR 5 // R/W Line Status Register
169 #define SERIAL_REGISTER_MSR 6 // R/W Modem Status Register
170 #define SERIAL_REGISTER_SCR 7 // R/W Scratch Pad Register
173 // Name: SERIAL_PORT_IER_BITS
174 // Purpose: Define each bit in Interrupt Enable Register
177 // RAVIE Bit0: Receiver Data Available Interrupt Enable
178 // THEIE Bit1: Transmistter Holding Register Empty Interrupt Enable
179 // RIE Bit2: Receiver Interrupt Enable
180 // MIE Bit3: Modem Interrupt Enable
181 // Reserved Bit4-Bit7: Reserved
189 } SERIAL_PORT_IER_BITS
;
192 // Name: SERIAL_PORT_IER
196 // Bits SERIAL_PORT_IER_BITS: Bits of the IER
197 // Data UINT8: the value of the IER
200 SERIAL_PORT_IER_BITS Bits
;
205 // Name: SERIAL_PORT_IIR_BITS
206 // Purpose: Define each bit in Interrupt Identification Register
209 // IPS Bit0: Interrupt Pending Status
210 // IIB Bit1-Bit3: Interrupt ID Bits
211 // Reserved Bit4-Bit5: Reserved
212 // FIFOES Bit6-Bit7: FIFO Mode Enable Status
219 } SERIAL_PORT_IIR_BITS
;
222 // Name: SERIAL_PORT_IIR
226 // Bits SERIAL_PORT_IIR_BITS: Bits of the IIR
227 // Data UINT8: the value of the IIR
230 SERIAL_PORT_IIR_BITS Bits
;
235 // Name: SERIAL_PORT_FCR_BITS
236 // Purpose: Define each bit in FIFO Control Register
239 // TRFIFOE Bit0: Transmit and Receive FIFO Enable
240 // RESETRF Bit1: Reset Reciever FIFO
241 // RESETTF Bit2: Reset Transmistter FIFO
242 // DMS Bit3: DMA Mode Select
243 // Reserved Bit4-Bit5: Reserved
244 // RTB Bit6-Bit7: Receive Trigger Bits
253 } SERIAL_PORT_FCR_BITS
;
256 // Name: SERIAL_PORT_FCR
260 // Bits SERIAL_PORT_FCR_BITS: Bits of the FCR
261 // Data UINT8: the value of the FCR
264 SERIAL_PORT_FCR_BITS Bits
;
269 // Name: SERIAL_PORT_LCR_BITS
270 // Purpose: Define each bit in Line Control Register
273 // SERIALDB Bit0-Bit1: Number of Serial Data Bits
274 // STOPB Bit2: Number of Stop Bits
275 // PAREN Bit3: Parity Enable
276 // EVENPAR Bit4: Even Parity Select
277 // STICPAR Bit5: Sticky Parity
278 // BRCON Bit6: Break Control
279 // DLAB Bit7: Divisor Latch Access Bit
289 } SERIAL_PORT_LCR_BITS
;
292 // Name: SERIAL_PORT_LCR
296 // Bits SERIAL_PORT_LCR_BITS: Bits of the LCR
297 // Data UINT8: the value of the LCR
300 SERIAL_PORT_LCR_BITS Bits
;
305 // Name: SERIAL_PORT_MCR_BITS
306 // Purpose: Define each bit in Modem Control Register
309 // DTRC Bit0: Data Terminal Ready Control
310 // RTS Bit1: Request To Send Control
311 // OUT1 Bit2: Output1
312 // OUT2 Bit3: Output2, used to disable interrupt
313 // LME; Bit4: Loopback Mode Enable
314 // Reserved Bit5-Bit7: Reserved
323 } SERIAL_PORT_MCR_BITS
;
326 // Name: SERIAL_PORT_MCR
330 // Bits SERIAL_PORT_MCR_BITS: Bits of the MCR
331 // Data UINT8: the value of the MCR
334 SERIAL_PORT_MCR_BITS Bits
;
339 // Name: SERIAL_PORT_LSR_BITS
340 // Purpose: Define each bit in Line Status Register
343 // DR Bit0: Receiver Data Ready Status
344 // OE Bit1: Overrun Error Status
345 // PE Bit2: Parity Error Status
346 // FE Bit3: Framing Error Status
347 // BI Bit4: Break Interrupt Status
348 // THRE Bit5: Transmistter Holding Register Status
349 // TEMT Bit6: Transmitter Empty Status
350 // FIFOE Bit7: FIFO Error Status
361 } SERIAL_PORT_LSR_BITS
;
364 // Name: SERIAL_PORT_LSR
368 // Bits SERIAL_PORT_LSR_BITS: Bits of the LSR
369 // Data UINT8: the value of the LSR
372 SERIAL_PORT_LSR_BITS Bits
;
377 // Name: SERIAL_PORT_MSR_BITS
378 // Purpose: Define each bit in Modem Status Register
381 // DeltaCTS Bit0: Delta Clear To Send Status
382 // DeltaDSR Bit1: Delta Data Set Ready Status
383 // TrailingEdgeRI Bit2: Trailing Edge of Ring Indicator Status
384 // DeltaDCD Bit3: Delta Data Carrier Detect Status
385 // CTS Bit4: Clear To Send Status
386 // DSR Bit5: Data Set Ready Status
387 // RI Bit6: Ring Indicator Status
388 // DCD Bit7: Data Carrier Detect Status
393 UINT8 TrailingEdgeRI
: 1;
399 } SERIAL_PORT_MSR_BITS
;
402 // Name: SERIAL_PORT_MSR
406 // Bits SERIAL_PORT_MSR_BITS: Bits of the MSR
407 // Data UINT8: the value of the MSR
410 SERIAL_PORT_MSR_BITS Bits
;
416 // Define serial register I/O macros
418 #define READ_RBR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_RBR)
419 #define READ_DLL(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_DLL)
420 #define READ_DLM(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_DLM)
421 #define READ_IER(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_IER)
422 #define READ_IIR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_IIR)
423 #define READ_LCR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_LCR)
424 #define READ_MCR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_MCR)
425 #define READ_LSR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_LSR)
426 #define READ_MSR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_MSR)
427 #define READ_SCR(IO, B) IsaSerialReadPort (IO, B, SERIAL_REGISTER_SCR)
429 #define WRITE_THR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_THR, D)
430 #define WRITE_DLL(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_DLL, D)
431 #define WRITE_DLM(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_DLM, D)
432 #define WRITE_IER(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_IER, D)
433 #define WRITE_FCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_FCR, D)
434 #define WRITE_LCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_LCR, D)
435 #define WRITE_MCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_MCR, D)
436 #define WRITE_LSR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_LSR, D)
437 #define WRITE_MSR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_MSR, D)
438 #define WRITE_SCR(IO, B, D) IsaSerialWritePort (IO, B, SERIAL_REGISTER_SCR, D)
442 // Driver model protocol interface
447 SerialControllerDriverSupported (
448 IN EFI_DRIVER_BINDING_PROTOCOL
*This
,
449 IN EFI_HANDLE Controller
,
450 IN EFI_DEVICE_PATH_PROTOCOL
*RemainingDevicePath
455 SerialControllerDriverStart (
456 IN EFI_DRIVER_BINDING_PROTOCOL
*This
,
457 IN EFI_HANDLE Controller
,
458 IN EFI_DEVICE_PATH_PROTOCOL
*RemainingDevicePath
463 SerialControllerDriverStop (
464 IN EFI_DRIVER_BINDING_PROTOCOL
*This
,
465 IN EFI_HANDLE Controller
,
466 IN UINTN NumberOfChildren
,
467 IN EFI_HANDLE
*ChildHandleBuffer
471 // Serial I/O Protocol Interface
476 IN EFI_SERIAL_IO_PROTOCOL
*This
481 IsaSerialSetAttributes (
482 IN EFI_SERIAL_IO_PROTOCOL
*This
,
484 IN UINT32 ReceiveFifoDepth
,
486 IN EFI_PARITY_TYPE Parity
,
488 IN EFI_STOP_BITS_TYPE StopBits
493 IsaSerialSetControl (
494 IN EFI_SERIAL_IO_PROTOCOL
*This
,
500 IsaSerialGetControl (
501 IN EFI_SERIAL_IO_PROTOCOL
*This
,
508 IN EFI_SERIAL_IO_PROTOCOL
*This
,
509 IN OUT UINTN
*BufferSize
,
516 IN EFI_SERIAL_IO_PROTOCOL
*This
,
517 IN OUT UINTN
*BufferSize
,
522 // Internal Functions
525 IsaSerialPortPresent (
526 IN SERIAL_DEV
*SerialDevice
531 IN SERIAL_DEV_FIFO
*Fifo
536 IN SERIAL_DEV_FIFO
*Fifo
541 IN SERIAL_DEV_FIFO
*Fifo
,
546 IsaSerialFifoRemove (
547 IN SERIAL_DEV_FIFO
*Fifo
,
552 IsaSerialReceiveTransmit (
553 IN SERIAL_DEV
*SerialDevice
558 IN EFI_ISA_IO_PROTOCOL
*IsaIo
,
559 IN UINT16 BaseAddress
,
565 IN EFI_ISA_IO_PROTOCOL
*IsaIo
,
566 IN UINT16 BaseAddress
,