2 Header file for IDE Bus Driver's Data Structures
4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
12 #include <IndustryStandard/Atapi.h>
17 #define STALL_1_MILLI_SECOND 1000 // stall 1 ms
18 #define STALL_1_SECOND 1000000 // stall 1 second
32 IdeMagnetic
, /* ZIP Drive or LS120 Floppy Drive */
33 IdeCdRom
, /* ATAPI CDROM */
34 IdeHardDisk
, /* Hard Disk */
35 Ide48bitAddressingHardDisk
, /* Hard Disk larger than 120GB */
41 SenseDeviceNotReadyNoRetry
,
42 SenseDeviceNotReadyNeedRetry
,
60 UINT16 Command
; /* when write */
61 UINT16 Status
; /* when read */
65 UINT16 Error
; /* when read */
66 UINT16 Feature
; /* when write */
67 } IDE_ERROR_OR_FEATURE
;
70 UINT16 AltStatus
; /* when read */
71 UINT16 DeviceControl
; /* when write */
72 } IDE_ALTSTATUS_OR_DEVICECONTROL
;
79 IDE_ERROR_OR_FEATURE Reg1
;
85 IDE_CMD_OR_STATUS Reg
;
87 IDE_ALTSTATUS_OR_DEVICECONTROL Alt
;
91 UINT16 BusMasterBaseAddr
;
95 // IDE registers' base addresses
98 UINT16 CommandBlockBaseAddr
;
99 UINT16 ControlBlockBaseAddr
;
100 UINT16 BusMasterBaseAddr
;
101 } IDE_REGISTERS_BASE_ADDR
;
104 // Bit definitions in Programming Interface byte of the Class Code field
105 // in PCI IDE controller's Configuration Space
107 #define IDE_PRIMARY_OPERATING_MODE BIT0
108 #define IDE_PRIMARY_PROGRAMMABLE_INDICATOR BIT1
109 #define IDE_SECONDARY_OPERATING_MODE BIT2
110 #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR BIT3
116 #define BMIC_NREAD BIT3
117 #define BMIC_START BIT0
118 #define BMIS_INTERRUPT BIT2
119 #define BMIS_ERROR BIT1
121 #define BMICP_OFFSET 0x00
122 #define BMISP_OFFSET 0x02
123 #define BMIDP_OFFSET 0x04
124 #define BMICS_OFFSET 0x08
125 #define BMISS_OFFSET 0x0A
126 #define BMIDS_OFFSET 0x0C
129 // Time Out Value For IDE Device Polling
133 // ATATIMEOUT is used for waiting time out for ATA device
139 #define ATATIMEOUT 1000
142 // ATAPITIMEOUT is used for waiting operation
143 // except read and write time out for ATAPI device
149 #define ATAPITIMEOUT 1000
152 // ATAPILONGTIMEOUT is used for waiting read and
153 // write operation timeout for ATAPI device
159 #define CDROMLONGTIMEOUT 2000
164 #define ATAPILONGTIMEOUT 5000
169 #define ATASMARTTIMEOUT 10000
173 // ATAPI6 related data structure definition
177 // The maximum sectors count in 28 bit addressing mode
179 #define MAX_28BIT_ADDRESSING_CAPACITY 0xfffffff
184 UINT32 RegionBaseAddr
;
191 #define SETFEATURE TRUE
192 #define CLEARFEATURE FALSE
195 /// PIO mode definition
197 typedef enum _ATA_PIO_MODE_
{
205 // Multi word DMA definition
207 typedef enum _ATA_MDMA_MODE_
{
214 // UDMA mode definition
216 typedef enum _ATA_UDMA_MODE_
{
225 #define ATA_MODE_CATEGORY_DEFAULT_PIO 0x00
226 #define ATA_MODE_CATEGORY_FLOW_PIO 0x01
227 #define ATA_MODE_CATEGORY_MDMA 0x04
228 #define ATA_MODE_CATEGORY_UDMA 0x08
233 UINT8 ModeNumber
: 3;
234 UINT8 ModeCategory
: 5;
240 UINT8 MultipleSector
;
245 // IORDY Sample Point field value
253 // Recovery Time field value
255 #define RECVY_4_CLK 0
256 #define RECVY_3_CLK 1
257 #define RECVY_2_CLK 2
258 #define RECVY_1_CLK 3
261 // Slave IDE Timing Register Enable
266 // DMA Timing Enable Only Select 1
271 // Pre-fetch and Posting Enable Select 1
276 // IORDY Sample Point Enable Select 1
281 // Fast Timing Bank Drive Select 1
286 // DMA Timing Enable Only Select 0
291 // Pre-fetch and Posting Enable Select 0
296 // IOREY Sample Point Enable Select 0
301 // Fast Timing Bank Drive Select 0