IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBus.h

   1 /** @file
   2
   3 Copyright (c) 2006, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 **/
  13
  14
  15 #ifndef _EFI_PCI_BUS_H_
  16 #define _EFI_PCI_BUS_H_
  17
  18
  19 #include <FrameworkDxe.h>
  20
  21
  22 #include <Protocol/LoadedImage.h>
  23 #include <Protocol/PciHostBridgeResourceAllocation.h>
  24 #include <Protocol/PciIo.h>
  25 #include <Protocol/LoadFile2.h>
  26 #include <Guid/PciHotplugDevice.h>
  27 #include <Protocol/PciRootBridgeIo.h>
  28 #include <Protocol/PciHotPlugRequest.h>
  29 #include <Protocol/DevicePath.h>
  30 #include <Protocol/PciPlatform.h>
  31 #include <Protocol/PciHotPlugInit.h>
  32 #include <Protocol/Decompress.h>
  33 #include <Guid/PciOptionRomTable.h>
  34 #include <Protocol/BusSpecificDriverOverride.h>
  35 #include <Protocol/UgaIo.h>
  36 #include <Protocol/IncompatiblePciDeviceSupport.h>
  37
  38 #include <Library/DebugLib.h>
  39 #include <Library/UefiDriverEntryPoint.h>
  40 #include <Library/BaseLib.h>
  41 #include <Library/UefiLib.h>
  42 #include <Library/BaseMemoryLib.h>
  43 #include <Library/ReportStatusCodeLib.h>
  44 #include <Library/MemoryAllocationLib.h>
  45 #include <Library/UefiBootServicesTableLib.h>
  46 #include <Library/DevicePathLib.h>
  47 #include <Library/PcdLib.h>
  48 #include <Library/PciIncompatibleDeviceSupportLib.h>
  49 #include <Library/PeCoffLib.h>
  50
  51 #include <IndustryStandard/Pci.h>
  52 #include <IndustryStandard/PeImage.h>
  53 #include <IndustryStandard/Acpi.h>
  54 #include "ComponentName.h"
  55
  56
  57 //
  58 // Global Variables
  59 //
  60 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;
  61 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
  62 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
  63 extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;
  64
  65 //
  66 // Driver Produced Protocol Prototypes
  67 //
  68
  69 #define VGABASE1  0x3B0
  70 #define VGALIMIT1 0x3BB
  71
  72 #define VGABASE2  0x3C0
  73 #define VGALIMIT2 0x3DF
  74
  75 #define ISABASE   0x100
  76 #define ISALIMIT  0x3FF
  77
  78 typedef enum {
  79   PciBarTypeUnknown = 0,
  80   PciBarTypeIo16,
  81   PciBarTypeIo32,
  82   PciBarTypeMem32,
  83   PciBarTypePMem32,
  84   PciBarTypeMem64,
  85   PciBarTypePMem64,
  86   PciBarTypeIo,
  87   PciBarTypeMem,
  88   PciBarTypeMaxType
  89 } PCI_BAR_TYPE;
  90
  91 typedef struct {
  92   UINT64        BaseAddress;
  93   UINT64        Length;
  94   UINT64        Alignment;
  95   PCI_BAR_TYPE  BarType;
  96   BOOLEAN       Prefetchable;
  97   UINT8         MemType;
  98   UINT8         Offset;
  99 } PCI_BAR;
 100
 101 #define PPB_BAR_0                             0
 102 #define PPB_BAR_1                             1
 103 #define PPB_IO_RANGE                          2
 104 #define PPB_MEM32_RANGE                       3
 105 #define PPB_PMEM32_RANGE                      4
 106 #define PPB_PMEM64_RANGE                      5
 107 #define PPB_MEM64_RANGE                       0xFF
 108
 109 #define P2C_BAR_0                             0
 110 #define P2C_MEM_1                             1
 111 #define P2C_MEM_2                             2
 112 #define P2C_IO_1                              3
 113 #define P2C_IO_2                              4
 114
 115 #define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')
 116
 117 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
 118 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
 119 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
 120 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
 121 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
 122 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
 123 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
 124
 125 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
 126
 127 //
 128 // Define option for attribute
 129 //
 130 #define EFI_SET_SUPPORTS    0
 131 #define EFI_SET_ATTRIBUTES  1
 132
 133 typedef struct _PCI_IO_DEVICE {
 134   UINT32                                    Signature;
 135   EFI_HANDLE                                Handle;
 136   EFI_PCI_IO_PROTOCOL                       PciIo;
 137   LIST_ENTRY                                Link;
 138
 139   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 140   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 141   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 142   EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;
 143
 144   //
 145   // PCI configuration space header type
 146   //
 147   PCI_TYPE00                                Pci;
 148
 149   //
 150   // Bus number, Device number, Function number
 151   //
 152   UINT8                                     BusNumber;
 153   UINT8                                     DeviceNumber;
 154   UINT8                                     FunctionNumber;
 155
 156   //
 157   // BAR for this PCI Device
 158   //
 159   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 160
 161   //
 162   // The bridge device this pci device is subject to
 163   //
 164   struct _PCI_IO_DEVICE                     *Parent;
 165
 166   //
 167   // A linked list for children Pci Device if it is bridge device
 168   //
 169   LIST_ENTRY                                ChildList;
 170
 171   //
 172   // TURE if the PCI bus driver creates the handle for this PCI device
 173   //
 174   BOOLEAN                                   Registered;
 175
 176   //
 177   // TRUE if the PCI bus driver successfully allocates the resource required by
 178   // this PCI device
 179   //
 180   BOOLEAN                                   Allocated;
 181
 182   //
 183   // The attribute this PCI device currently set
 184   //
 185   UINT64                                    Attributes;
 186
 187   //
 188   // The attributes this PCI device actually supports
 189   //
 190   UINT64                                    Supports;
 191
 192   //
 193   // The resource decode the bridge supports
 194   //
 195   UINT32                                    Decodes;
 196
 197   //
 198   // The OptionRom Size
 199   //
 200   UINT64                                    RomSize;
 201
 202   //
 203   // The OptionRom Size
 204   //
 205   UINT64                                    RomBase;
 206
 207   //
 208   // TRUE if all OpROM (in device or in platform specific position) have been processed
 209   //
 210   BOOLEAN                                   AllOpRomProcessed;
 211
 212   //
 213   // TRUE if there is any EFI driver in the OptionRom
 214   //
 215   BOOLEAN                                   BusOverride;
 216
 217   //
 218   //  A list tracking reserved resource on a bridge device
 219   //
 220   LIST_ENTRY                                ReservedResourceList;
 221
 222   //
 223   // A list tracking image handle of platform specific overriding driver
 224   //
 225   LIST_ENTRY                                OptionRomDriverList;
 226
 227   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 228   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 229
 230   BOOLEAN                                   IsPciExp;
 231
 232 } PCI_IO_DEVICE;
 233
 234
 235 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 236   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 237
 238 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 239   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 240
 241 #define PCI_IO_DEVICE_FROM_LINK(a) \
 242   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 243
 244 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
 245   CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
 246
 247 //
 248 // Global Variables
 249 //
 250 extern LIST_ENTRY                                   gPciDevicePool;
 251 extern BOOLEAN                                      gFullEnumeration;
 252 extern UINTN                                        gPciHostBridgeNumber;
 253 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 254 extern UINT64                                       gAllOne;
 255 extern UINT64                                       gAllZero;
 256
 257 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 258
 259 #include "PciIo.h"
 260 #include "PciCommand.h"
 261 #include "PciDeviceSupport.h"
 262 #include "PciEnumerator.h"
 263 #include "PciEnumeratorSupport.h"
 264 #include "PciDriverOverride.h"
 265 #include "PciRomTable.h"
 266 #include "PciOptionRomSupport.h"
 267 #include "PciPowerManagement.h"
 268 #include "PciHotPlugSupport.h"
 269 #include "PciLib.h"
 270
 271 //
 272 // PCI Bus Support Function Prototypes
 273 //
 274 /**
 275   Test to see if this driver supports ControllerHandle. Any ControllerHandle
 276   than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
 277
 278   @param  This                Protocol instance pointer.
 279   @param  ControllerHandle    Handle of device to test.
 280   @param  RemainingDevicePath Optional parameter use to pick a specific child.
 281                               device to start.
 282
 283   @retval EFI_SUCCESS         This driver supports this device.
 284   @retval EFI_ALREADY_STARTED This driver is already running on this device.
 285   @retval other               This driver does not support this device.
 286
 287 **/
 288 EFI_STATUS
 289 EFIAPI
 290 PciBusDriverBindingSupported (
 291   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 292   IN EFI_HANDLE                     Controller,
 293   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 294   );
 295
 296 /**
 297   Start this driver on ControllerHandle and enumerate Pci bus and start
 298   all device under PCI bus.
 299
 300   @param  This                 Protocol instance pointer.
 301   @param  ControllerHandle     Handle of device to bind driver to.
 302   @param  RemainingDevicePath  Optional parameter use to pick a specific child.
 303                                device to start.
 304
 305   @retval EFI_SUCCESS          This driver is added to ControllerHandle.
 306   @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.
 307   @retval other                This driver does not support this device.
 308
 309 **/
 310 EFI_STATUS
 311 EFIAPI
 312 PciBusDriverBindingStart (
 313   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 314   IN EFI_HANDLE                     Controller,
 315   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 316   );
 317
 318 /**
 319   Stop this driver on ControllerHandle. Support stoping any child handles
 320   created by this driver.
 321
 322   @param  This              Protocol instance pointer.
 323   @param  ControllerHandle  Handle of device to stop driver on.
 324   @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of
 325                             children is zero stop the entire bus driver.
 326   @param  ChildHandleBuffer List of Child Handles to Stop.
 327
 328   @retval EFI_SUCCESS       This driver is removed ControllerHandle.
 329   @retval other             This driver was not removed from this device.
 330
 331 **/
 332 EFI_STATUS
 333 EFIAPI
 334 PciBusDriverBindingStop (
 335   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
 336   IN  EFI_HANDLE                    Controller,
 337   IN  UINTN                         NumberOfChildren,
 338   IN  EFI_HANDLE                    *ChildHandleBuffer
 339   );
 340
 341 #define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
 342
 343 #endif