IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBus.h

   1 /** @file
   2
   3 Copyright (c) 2006, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 **/
  13
  14
  15 #ifndef _EFI_PCI_BUS_H_
  16 #define _EFI_PCI_BUS_H_
  17
  18
  19 #include <FrameworkDxe.h>
  20
  21
  22 #include <Protocol/LoadedImage.h>
  23 #include <Protocol/PciHostBridgeResourceAllocation.h>
  24 #include <Protocol/PciIo.h>
  25 #include <Protocol/LoadFile2.h>
  26 #include <Protocol/PciRootBridgeIo.h>
  27 #include <Protocol/PciHotPlugRequest.h>
  28 #include <Protocol/DevicePath.h>
  29 #include <Protocol/PciPlatform.h>
  30 #include <Protocol/PciHotPlugInit.h>
  31 #include <Protocol/Decompress.h>
  32 #include <Guid/PciOptionRomTable.h>
  33 #include <Protocol/BusSpecificDriverOverride.h>
  34 #include <Protocol/UgaIo.h>
  35 #include <Protocol/IncompatiblePciDeviceSupport.h>
  36
  37 #include <Library/DebugLib.h>
  38 #include <Library/UefiDriverEntryPoint.h>
  39 #include <Library/BaseLib.h>
  40 #include <Library/UefiLib.h>
  41 #include <Library/BaseMemoryLib.h>
  42 #include <Library/ReportStatusCodeLib.h>
  43 #include <Library/MemoryAllocationLib.h>
  44 #include <Library/UefiBootServicesTableLib.h>
  45 #include <Library/DevicePathLib.h>
  46 #include <Library/PcdLib.h>
  47 #include <Library/PciIncompatibleDeviceSupportLib.h>
  48 #include <Library/PeCoffLib.h>
  49
  50 #include <IndustryStandard/Pci.h>
  51 #include <IndustryStandard/PeImage.h>
  52 #include <IndustryStandard/Acpi.h>
  53 #include "ComponentName.h"
  54
  55
  56 //
  57 // Global Variables
  58 //
  59 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;
  60 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
  61 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
  62 extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;
  63
  64 //
  65 // Driver Produced Protocol Prototypes
  66 //
  67
  68 #define VGABASE1  0x3B0
  69 #define VGALIMIT1 0x3BB
  70
  71 #define VGABASE2  0x3C0
  72 #define VGALIMIT2 0x3DF
  73
  74 #define ISABASE   0x100
  75 #define ISALIMIT  0x3FF
  76
  77 typedef enum {
  78   PciBarTypeUnknown = 0,
  79   PciBarTypeIo16,
  80   PciBarTypeIo32,
  81   PciBarTypeMem32,
  82   PciBarTypePMem32,
  83   PciBarTypeMem64,
  84   PciBarTypePMem64,
  85   PciBarTypeIo,
  86   PciBarTypeMem,
  87   PciBarTypeMaxType
  88 } PCI_BAR_TYPE;
  89
  90 typedef struct {
  91   UINT64        BaseAddress;
  92   UINT64        Length;
  93   UINT64        Alignment;
  94   PCI_BAR_TYPE  BarType;
  95   BOOLEAN       Prefetchable;
  96   UINT8         MemType;
  97   UINT8         Offset;
  98 } PCI_BAR;
  99
 100 #define PPB_BAR_0                             0
 101 #define PPB_BAR_1                             1
 102 #define PPB_IO_RANGE                          2
 103 #define PPB_MEM32_RANGE                       3
 104 #define PPB_PMEM32_RANGE                      4
 105 #define PPB_PMEM64_RANGE                      5
 106 #define PPB_MEM64_RANGE                       0xFF
 107
 108 #define P2C_BAR_0                             0
 109 #define P2C_MEM_1                             1
 110 #define P2C_MEM_2                             2
 111 #define P2C_IO_1                              3
 112 #define P2C_IO_2                              4
 113
 114 #define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')
 115
 116 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
 117 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
 118 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
 119 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
 120 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
 121 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
 122 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
 123
 124 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
 125
 126 //
 127 // Define option for attribute
 128 //
 129 #define EFI_SET_SUPPORTS    0
 130 #define EFI_SET_ATTRIBUTES  1
 131
 132 typedef struct _PCI_IO_DEVICE {
 133   UINT32                                    Signature;
 134   EFI_HANDLE                                Handle;
 135   EFI_PCI_IO_PROTOCOL                       PciIo;
 136   LIST_ENTRY                                Link;
 137
 138   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 139   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 140   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 141   EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;
 142
 143   //
 144   // PCI configuration space header type
 145   //
 146   PCI_TYPE00                                Pci;
 147
 148   //
 149   // Bus number, Device number, Function number
 150   //
 151   UINT8                                     BusNumber;
 152   UINT8                                     DeviceNumber;
 153   UINT8                                     FunctionNumber;
 154
 155   //
 156   // BAR for this PCI Device
 157   //
 158   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 159
 160   //
 161   // The bridge device this pci device is subject to
 162   //
 163   struct _PCI_IO_DEVICE                     *Parent;
 164
 165   //
 166   // A linked list for children Pci Device if it is bridge device
 167   //
 168   LIST_ENTRY                                ChildList;
 169
 170   //
 171   // TURE if the PCI bus driver creates the handle for this PCI device
 172   //
 173   BOOLEAN                                   Registered;
 174
 175   //
 176   // TRUE if the PCI bus driver successfully allocates the resource required by
 177   // this PCI device
 178   //
 179   BOOLEAN                                   Allocated;
 180
 181   //
 182   // The attribute this PCI device currently set
 183   //
 184   UINT64                                    Attributes;
 185
 186   //
 187   // The attributes this PCI device actually supports
 188   //
 189   UINT64                                    Supports;
 190
 191   //
 192   // The resource decode the bridge supports
 193   //
 194   UINT32                                    Decodes;
 195
 196   //
 197   // The OptionRom Size
 198   //
 199   UINT64                                    RomSize;
 200
 201   //
 202   // The OptionRom Size
 203   //
 204   UINT64                                    RomBase;
 205
 206   //
 207   // TRUE if all OpROM (in device or in platform specific position) have been processed
 208   //
 209   BOOLEAN                                   AllOpRomProcessed;
 210
 211   //
 212   // TRUE if there is any EFI driver in the OptionRom
 213   //
 214   BOOLEAN                                   BusOverride;
 215
 216   //
 217   //  A list tracking reserved resource on a bridge device
 218   //
 219   LIST_ENTRY                                ReservedResourceList;
 220
 221   //
 222   // A list tracking image handle of platform specific overriding driver
 223   //
 224   LIST_ENTRY                                OptionRomDriverList;
 225
 226   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 227   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 228
 229   BOOLEAN                                   IsPciExp;
 230
 231 } PCI_IO_DEVICE;
 232
 233
 234 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 235   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 236
 237 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 238   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 239
 240 #define PCI_IO_DEVICE_FROM_LINK(a) \
 241   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 242
 243 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
 244   CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
 245
 246 //
 247 // Global Variables
 248 //
 249 extern LIST_ENTRY                                   gPciDevicePool;
 250 extern BOOLEAN                                      gFullEnumeration;
 251 extern UINTN                                        gPciHostBridgeNumber;
 252 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 253 extern UINT64                                       gAllOne;
 254 extern UINT64                                       gAllZero;
 255
 256 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 257
 258 #include "PciIo.h"
 259 #include "PciCommand.h"
 260 #include "PciDeviceSupport.h"
 261 #include "PciEnumerator.h"
 262 #include "PciEnumeratorSupport.h"
 263 #include "PciDriverOverride.h"
 264 #include "PciRomTable.h"
 265 #include "PciOptionRomSupport.h"
 266 #include "PciPowerManagement.h"
 267 #include "PciHotPlugSupport.h"
 268 #include "PciLib.h"
 269
 270 //
 271 // PCI Bus Support Function Prototypes
 272 //
 273 /**
 274   Test to see if this driver supports ControllerHandle. Any ControllerHandle
 275   than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.
 276
 277   @param  This                Protocol instance pointer.
 278   @param  ControllerHandle    Handle of device to test.
 279   @param  RemainingDevicePath Optional parameter use to pick a specific child.
 280                               device to start.
 281
 282   @retval EFI_SUCCESS         This driver supports this device.
 283   @retval EFI_ALREADY_STARTED This driver is already running on this device.
 284   @retval other               This driver does not support this device.
 285
 286 **/
 287 EFI_STATUS
 288 EFIAPI
 289 PciBusDriverBindingSupported (
 290   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 291   IN EFI_HANDLE                     Controller,
 292   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 293   );
 294
 295 /**
 296   Start this driver on ControllerHandle and enumerate Pci bus and start
 297   all device under PCI bus.
 298
 299   @param  This                 Protocol instance pointer.
 300   @param  ControllerHandle     Handle of device to bind driver to.
 301   @param  RemainingDevicePath  Optional parameter use to pick a specific child.
 302                                device to start.
 303
 304   @retval EFI_SUCCESS          This driver is added to ControllerHandle.
 305   @retval EFI_ALREADY_STARTED  This driver is already running on ControllerHandle.
 306   @retval other                This driver does not support this device.
 307
 308 **/
 309 EFI_STATUS
 310 EFIAPI
 311 PciBusDriverBindingStart (
 312   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 313   IN EFI_HANDLE                     Controller,
 314   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 315   );
 316
 317 /**
 318   Stop this driver on ControllerHandle. Support stoping any child handles
 319   created by this driver.
 320
 321   @param  This              Protocol instance pointer.
 322   @param  ControllerHandle  Handle of device to stop driver on.
 323   @param  NumberOfChildren  Number of Handles in ChildHandleBuffer. If number of
 324                             children is zero stop the entire bus driver.
 325   @param  ChildHandleBuffer List of Child Handles to Stop.
 326
 327   @retval EFI_SUCCESS       This driver is removed ControllerHandle.
 328   @retval other             This driver was not removed from this device.
 329
 330 **/
 331 EFI_STATUS
 332 EFIAPI
 333 PciBusDriverBindingStop (
 334   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
 335   IN  EFI_HANDLE                    Controller,
 336   IN  UINTN                         NumberOfChildren,
 337   IN  EFI_HANDLE                    *ChildHandleBuffer
 338   );
 339
 340 #define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
 341
 342 #endif