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1 /** @file
2 Implements all interfaces for EFI_PCI_IO_PROTOCOL.
3
4 Copyright (c) 2006 - 2008, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14
15
16 #include "PciBus.h"
17
18 //
19 // Pci Io Protocol Interface
20 //
21 EFI_PCI_IO_PROTOCOL mPciIoInterface = {
22 PciIoPollMem,
23 PciIoPollIo,
24 {
25 PciIoMemRead,
26 PciIoMemWrite
27 },
28 {
29 PciIoIoRead,
30 PciIoIoWrite
31 },
32 {
33 PciIoConfigRead,
34 PciIoConfigWrite
35 },
36 PciIoCopyMem,
37 PciIoMap,
38 PciIoUnmap,
39 PciIoAllocateBuffer,
40 PciIoFreeBuffer,
41 PciIoFlush,
42 PciIoGetLocation,
43 PciIoAttributes,
44 PciIoGetBarAttributes,
45 PciIoSetBarAttributes,
46 0,
47 NULL
48 };
49
50 /**
51 report a error Status code of PCI bus driver controller.
52
53 @param PciIoDevice Pci device instance.
54 @param Code status code.
55
56 **/
57 EFI_STATUS
58 ReportErrorStatusCode (
59 IN PCI_IO_DEVICE *PciIoDevice,
60 IN EFI_STATUS_CODE_VALUE Code
61 );
62
63 //
64 // PCI I/O Support Function Prototypes
65 //
66 //
67
68 /**
69 report a error Status code of PCI bus driver controller.
70
71 @param PciIoDevice Pci device instance.
72 @param Code status code.
73 **/
74 EFI_STATUS
75 ReportErrorStatusCode (
76 IN PCI_IO_DEVICE *PciIoDevice,
77 IN EFI_STATUS_CODE_VALUE Code
78 )
79 {
80 return REPORT_STATUS_CODE_WITH_DEVICE_PATH (
81 EFI_ERROR_CODE | EFI_ERROR_MINOR,
82 Code,
83 PciIoDevice->DevicePath
84 );
85 }
86
87 /**
88 Initializes a PCI I/O Instance.
89
90 @param PciIoDevice Pci device instance.
91
92 **/
93 VOID
94 InitializePciIoInstance (
95 PCI_IO_DEVICE *PciIoDevice
96 )
97 {
98 CopyMem (&PciIoDevice->PciIo, &mPciIoInterface, sizeof (EFI_PCI_IO_PROTOCOL));
99 }
100
101 /**
102 Verifies access to a PCI Base Address Register (BAR)
103
104 @param PciIoDevice Pci device instance
105 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
106 base address for the memory or I/O operation to perform.
107 @param Type Operation type could be memory or I/O
108 @param Width Signifies the width of the memory or I/O operations.
109 @param Count The number of memory or I/O operations to perform.
110 @param Offset The offset within the PCI configuration space for the PCI controller.
111
112 @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.
113 @retval EFI_SUCCESS Success Operation.
114 **/
115 EFI_STATUS
116 PciIoVerifyBarAccess (
117 PCI_IO_DEVICE *PciIoDevice,
118 UINT8 BarIndex,
119 PCI_BAR_TYPE Type,
120 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
121 IN UINTN Count,
122 UINT64 *Offset
123 )
124 {
125 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
126 return EFI_INVALID_PARAMETER;
127 }
128
129 if (BarIndex == EFI_PCI_IO_PASS_THROUGH_BAR) {
130 return EFI_SUCCESS;
131 }
132
133 //
134 // BarIndex 0-5 is legal
135 //
136 if (BarIndex >= PCI_MAX_BAR) {
137 return EFI_INVALID_PARAMETER;
138 }
139
140 if (!CheckBarType (PciIoDevice, BarIndex, Type)) {
141 return EFI_INVALID_PARAMETER;
142 }
143
144 //
145 // If Width is EfiPciIoWidthFifoUintX then convert to EfiPciIoWidthUintX
146 // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX
147 //
148 if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
149 Count = 1;
150 }
151
152 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);
153
154 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PciIoDevice->PciBar[BarIndex].Length) {
155 return EFI_INVALID_PARAMETER;
156 }
157
158 *Offset = *Offset + PciIoDevice->PciBar[BarIndex].BaseAddress;
159
160 return EFI_SUCCESS;
161 }
162
163 /**
164 Verifies access to a PCI Config Header
165
166 @param PciIoDevice Pci device instance
167 @param Width Signifies the width of the memory or I/O operations.
168 @param Count The number of memory or I/O operations to perform.
169 @param Offset The offset within the PCI configuration space for the PCI controller.
170
171 @retval EFI_INVALID_PARAMETER Invalid Width
172 @retval EFI_UNSUPPORTED Offset overflow
173 @retval EFI_SUCCESS Success operation
174 **/
175 EFI_STATUS
176 PciIoVerifyConfigAccess (
177 PCI_IO_DEVICE *PciIoDevice,
178 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
179 IN UINTN Count,
180 IN UINT64 *Offset
181 )
182 {
183 UINT64 ExtendOffset;
184
185 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
186 return EFI_INVALID_PARAMETER;
187 }
188
189 //
190 // If Width is EfiPciIoWidthFillUintX then convert to EfiPciIoWidthUintX
191 //
192 Width = (EFI_PCI_IO_PROTOCOL_WIDTH) (Width & 0x03);
193
194 if (PciIoDevice->IsPciExp) {
195 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_EXP_MAX_CONFIG_OFFSET) {
196 return EFI_UNSUPPORTED;
197 }
198
199 ExtendOffset = LShiftU64 (*Offset, 32);
200 *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, 0);
201 *Offset = (*Offset) | ExtendOffset;
202
203 } else {
204 if ((*Offset + Count * (UINTN)(1 << Width)) - 1 >= PCI_MAX_CONFIG_OFFSET) {
205 return EFI_UNSUPPORTED;
206 }
207
208 *Offset = EFI_PCI_ADDRESS (PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice->FunctionNumber, *Offset);
209 }
210
211 return EFI_SUCCESS;
212 }
213
214 /**
215 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
216 satisfied or after a defined duration.
217
218 @param This Pointer to protocol instance of EFI_PCI_IO_PROTOCOL
219 @param Width Signifies the width of the memory or I/O operations.
220 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
221 base address for the memory or I/O operation to perform.
222 @param Offset The offset within the PCI configuration space for the PCI controller.
223 @param Mask Mask used for the polling criteria.
224 @param Value The comparison value used for the polling exit criteria.
225 @param Delay The number of 100 ns units to poll.
226 @param Result Pointer to the last value read from the memory location.
227
228 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
229 @retval EFI_TIMEOUT Delay expired before a match occurred.
230 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
231 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
232 **/
233 EFI_STATUS
234 EFIAPI
235 PciIoPollMem (
236 IN EFI_PCI_IO_PROTOCOL *This,
237 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
238 IN UINT8 BarIndex,
239 IN UINT64 Offset,
240 IN UINT64 Mask,
241 IN UINT64 Value,
242 IN UINT64 Delay,
243 OUT UINT64 *Result
244 )
245 {
246 EFI_STATUS Status;
247 PCI_IO_DEVICE *PciIoDevice;
248
249 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
250
251 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
252 return EFI_INVALID_PARAMETER;
253 }
254
255 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, 1, &Offset);
256 if (EFI_ERROR (Status)) {
257 return EFI_UNSUPPORTED;
258 }
259
260 if (Width > EfiPciIoWidthUint64) {
261 return EFI_INVALID_PARAMETER;
262 }
263
264 Status = PciIoDevice->PciRootBridgeIo->PollMem (
265 PciIoDevice->PciRootBridgeIo,
266 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
267 Offset,
268 Mask,
269 Value,
270 Delay,
271 Result
272 );
273
274 if (EFI_ERROR (Status)) {
275 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
276 }
277
278 return Status;
279 }
280
281 /**
282 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
283 satisfied or after a defined duration.
284
285 @param This A pointer to the EFI_PCI_IO_PROTOCOL.
286 @param Width Signifies the width of the memory or I/O operations.
287 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
288 base address for the memory or I/O operation to perform.
289 @param Offset The offset within the selected BAR to start the memory or I/O operation.
290 @param Mask Mask used for the polling criteria.
291 @param Value The comparison value used for the polling exit criteria.
292 @param Delay The number of 100 ns units to poll.
293 @param Result Pointer to the last value read from the memory location.
294
295 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
296 @retval EFI_TIMEOUT Delay expired before a match occurred.
297 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
298 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
299
300 **/
301 EFI_STATUS
302 EFIAPI
303 PciIoPollIo (
304 IN EFI_PCI_IO_PROTOCOL *This,
305 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
306 IN UINT8 BarIndex,
307 IN UINT64 Offset,
308 IN UINT64 Mask,
309 IN UINT64 Value,
310 IN UINT64 Delay,
311 OUT UINT64 *Result
312 )
313 {
314 EFI_STATUS Status;
315 PCI_IO_DEVICE *PciIoDevice;
316
317 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
318
319 if (Width < 0 || Width > EfiPciIoWidthUint64) {
320 return EFI_INVALID_PARAMETER;
321 }
322
323 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, 1, &Offset);
324 if (EFI_ERROR (Status)) {
325 return EFI_UNSUPPORTED;
326 }
327
328 Status = PciIoDevice->PciRootBridgeIo->PollIo (
329 PciIoDevice->PciRootBridgeIo,
330 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
331 Offset,
332 Mask,
333 Value,
334 Delay,
335 Result
336 );
337
338 if (EFI_ERROR (Status)) {
339 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
340 }
341
342 return Status;
343 }
344
345 /**
346 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
347
348 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
349 @param Width Signifies the width of the memory or I/O operations.
350 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
351 base address for the memory or I/O operation to perform.
352 @param Offset The offset within the selected BAR to start the memory or I/O operation.
353 @param Count The number of memory or I/O operations to perform.
354 @param Buffer For read operations, the destination buffer to store the results. For write
355 operations, the source buffer to write data from.
356
357 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
358 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
359 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
360 valid for the PCI BAR specified by BarIndex.
361 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
362 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
363
364 **/
365 EFI_STATUS
366 EFIAPI
367 PciIoMemRead (
368 IN EFI_PCI_IO_PROTOCOL *This,
369 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
370 IN UINT8 BarIndex,
371 IN UINT64 Offset,
372 IN UINTN Count,
373 IN OUT VOID *Buffer
374 )
375 {
376 EFI_STATUS Status;
377 PCI_IO_DEVICE *PciIoDevice;
378
379 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
380
381 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
382 return EFI_INVALID_PARAMETER;
383 }
384
385 if (Buffer == NULL) {
386 return EFI_INVALID_PARAMETER;
387 }
388
389 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);
390 if (EFI_ERROR (Status)) {
391 return EFI_UNSUPPORTED;
392 }
393
394 Status = PciIoDevice->PciRootBridgeIo->Mem.Read (
395 PciIoDevice->PciRootBridgeIo,
396 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
397 Offset,
398 Count,
399 Buffer
400 );
401
402 if (EFI_ERROR (Status)) {
403 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);
404 }
405
406 return Status;
407 }
408
409 /**
410 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
411
412 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
413 @param Width Signifies the width of the memory or I/O operations.
414 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
415 base address for the memory or I/O operation to perform.
416 @param Offset The offset within the selected BAR to start the memory or I/O operation.
417 @param Count The number of memory or I/O operations to perform.
418 @param Buffer For read operations, the destination buffer to store the results. For write
419 operations, the source buffer to write data from.
420
421 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
422 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
423 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
424 valid for the PCI BAR specified by BarIndex.
425 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
426 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
427
428 **/
429 EFI_STATUS
430 EFIAPI
431 PciIoMemWrite (
432 IN EFI_PCI_IO_PROTOCOL *This,
433 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
434 IN UINT8 BarIndex,
435 IN UINT64 Offset,
436 IN UINTN Count,
437 IN OUT VOID *Buffer
438 )
439 {
440 EFI_STATUS Status;
441 PCI_IO_DEVICE *PciIoDevice;
442
443 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
444
445 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
446 return EFI_INVALID_PARAMETER;
447 }
448
449 if (Buffer == NULL) {
450 return EFI_INVALID_PARAMETER;
451 }
452
453 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeMem, Width, Count, &Offset);
454 if (EFI_ERROR (Status)) {
455 return EFI_UNSUPPORTED;
456 }
457
458 Status = PciIoDevice->PciRootBridgeIo->Mem.Write (
459 PciIoDevice->PciRootBridgeIo,
460 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
461 Offset,
462 Count,
463 Buffer
464 );
465
466 if (EFI_ERROR (Status)) {
467 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);
468 }
469
470 return Status;
471 }
472
473 /**
474 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
475
476 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
477 @param Width Signifies the width of the memory or I/O operations.
478 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
479 base address for the memory or I/O operation to perform.
480 @param Offset The offset within the selected BAR to start the memory or I/O operation.
481 @param Count The number of memory or I/O operations to perform.
482 @param Buffer For read operations, the destination buffer to store the results. For write
483 operations, the source buffer to write data from.
484
485 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
486 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
487 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
488 valid for the PCI BAR specified by BarIndex.
489 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
490 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
491
492 **/
493 EFI_STATUS
494 EFIAPI
495 PciIoIoRead (
496 IN EFI_PCI_IO_PROTOCOL *This,
497 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
498 IN UINT8 BarIndex,
499 IN UINT64 Offset,
500 IN UINTN Count,
501 IN OUT VOID *Buffer
502 )
503 {
504 EFI_STATUS Status;
505 PCI_IO_DEVICE *PciIoDevice;
506
507 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
508
509 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
510 return EFI_INVALID_PARAMETER;
511 }
512
513 if (Buffer == NULL) {
514 return EFI_INVALID_PARAMETER;
515 }
516
517 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);
518 if (EFI_ERROR (Status)) {
519 return EFI_UNSUPPORTED;
520 }
521
522 Status = PciIoDevice->PciRootBridgeIo->Io.Read (
523 PciIoDevice->PciRootBridgeIo,
524 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
525 Offset,
526 Count,
527 Buffer
528 );
529
530 if (EFI_ERROR (Status)) {
531 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);
532 }
533
534 return Status;
535 }
536
537 /**
538 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
539
540 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
541 @param Width Signifies the width of the memory or I/O operations.
542 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
543 base address for the memory or I/O operation to perform.
544 @param Offset The offset within the selected BAR to start the memory or I/O operation.
545 @param Count The number of memory or I/O operations to perform.
546 @param Buffer For read operations, the destination buffer to store the results. For write
547 operations, the source buffer to write data from.
548
549 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
550 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
551 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
552 valid for the PCI BAR specified by BarIndex.
553 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
554 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
555
556 **/
557 EFI_STATUS
558 EFIAPI
559 PciIoIoWrite (
560 IN EFI_PCI_IO_PROTOCOL *This,
561 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
562 IN UINT8 BarIndex,
563 IN UINT64 Offset,
564 IN UINTN Count,
565 IN OUT VOID *Buffer
566 )
567 {
568 EFI_STATUS Status;
569 PCI_IO_DEVICE *PciIoDevice;
570
571 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
572
573 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
574 return EFI_INVALID_PARAMETER;
575 }
576
577 if (Buffer == NULL) {
578 return EFI_INVALID_PARAMETER;
579 }
580
581 Status = PciIoVerifyBarAccess (PciIoDevice, BarIndex, PciBarTypeIo, Width, Count, &Offset);
582 if (EFI_ERROR (Status)) {
583 return EFI_UNSUPPORTED;
584 }
585
586 Status = PciIoDevice->PciRootBridgeIo->Io.Write (
587 PciIoDevice->PciRootBridgeIo,
588 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
589 Offset,
590 Count,
591 Buffer
592 );
593
594 if (EFI_ERROR (Status)) {
595 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);
596 }
597
598 return Status;
599 }
600
601 /**
602 Enable a PCI driver to access PCI controller registers in PCI configuration space.
603
604 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
605 @param Width Signifies the width of the memory operations.
606 @param Offset The offset within the PCI configuration space for the PCI controller.
607 @param Count The number of PCI configuration operations to perform.
608 @param Buffer For read operations, the destination buffer to store the results. For write
609 operations, the source buffer to write data from.
610
611
612 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
613 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
614 valid for the PCI configuration header of the PCI controller.
615 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
616 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
617
618 **/
619 EFI_STATUS
620 EFIAPI
621 PciIoConfigRead (
622 IN EFI_PCI_IO_PROTOCOL *This,
623 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
624 IN UINT32 Offset,
625 IN UINTN Count,
626 IN OUT VOID *Buffer
627 )
628 {
629 EFI_STATUS Status;
630 PCI_IO_DEVICE *PciIoDevice;
631 UINT64 Address;
632
633 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
634
635 Address = Offset;
636 Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);
637 if (EFI_ERROR (Status)) {
638 return Status;
639 }
640
641 Status = PciIoDevice->PciRootBridgeIo->Pci.Read (
642 PciIoDevice->PciRootBridgeIo,
643 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
644 Address,
645 Count,
646 Buffer
647 );
648
649 if (EFI_ERROR (Status)) {
650 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_READ_ERROR);
651 }
652
653 return Status;
654 }
655
656 /**
657 Enable a PCI driver to access PCI controller registers in PCI configuration space.
658
659 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
660 @param Width Signifies the width of the memory operations.
661 @param Offset The offset within the PCI configuration space for the PCI controller.
662 @param Count The number of PCI configuration operations to perform.
663 @param Buffer For read operations, the destination buffer to store the results. For write
664 operations, the source buffer to write data from.
665
666
667 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
668 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
669 valid for the PCI configuration header of the PCI controller.
670 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
671 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
672
673 **/
674 EFI_STATUS
675 EFIAPI
676 PciIoConfigWrite (
677 IN EFI_PCI_IO_PROTOCOL *This,
678 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
679 IN UINT32 Offset,
680 IN UINTN Count,
681 IN OUT VOID *Buffer
682 )
683 {
684 EFI_STATUS Status;
685 PCI_IO_DEVICE *PciIoDevice;
686 UINT64 Address;
687
688 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
689
690 Address = Offset;
691 Status = PciIoVerifyConfigAccess (PciIoDevice, Width, Count, &Address);
692 if (EFI_ERROR (Status)) {
693 return Status;
694 }
695
696 Status = PciIoDevice->PciRootBridgeIo->Pci.Write (
697 PciIoDevice->PciRootBridgeIo,
698 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
699 Address,
700 Count,
701 Buffer
702 );
703
704 if (EFI_ERROR (Status)) {
705 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_WRITE_ERROR);
706 }
707
708 return Status;
709 }
710
711 /**
712 Enables a PCI driver to copy one region of PCI memory space to another region of PCI
713 memory space.
714
715 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
716 @param Width Signifies the width of the memory operations.
717 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the
718 base address for the memory operation to perform.
719 @param DestOffset The destination offset within the BAR specified by DestBarIndex to
720 start the memory writes for the copy operation.
721 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the
722 base address for the memory operation to perform.
723 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start
724 the memory reads for the copy operation.
725 @param Count The number of memory operations to perform. Bytes moved is Width
726 size * Count, starting at DestOffset and SrcOffset.
727
728 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
729 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.
730 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.
731 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count
732 is not valid for the PCI BAR specified by DestBarIndex.
733 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is
734 not valid for the PCI BAR specified by SrcBarIndex.
735 @retval EFI_INVALID_PARAMETER Width is invalid.
736 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
737
738 **/
739 EFI_STATUS
740 EFIAPI
741 PciIoCopyMem (
742 IN EFI_PCI_IO_PROTOCOL *This,
743 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
744 IN UINT8 DestBarIndex,
745 IN UINT64 DestOffset,
746 IN UINT8 SrcBarIndex,
747 IN UINT64 SrcOffset,
748 IN UINTN Count
749 )
750 {
751 EFI_STATUS Status;
752 PCI_IO_DEVICE *PciIoDevice;
753
754 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
755
756 if (Width < 0 || Width >= EfiPciIoWidthMaximum) {
757 return EFI_INVALID_PARAMETER;
758 }
759
760 if (Width == EfiPciIoWidthFifoUint8 ||
761 Width == EfiPciIoWidthFifoUint16 ||
762 Width == EfiPciIoWidthFifoUint32 ||
763 Width == EfiPciIoWidthFifoUint64 ||
764 Width == EfiPciIoWidthFillUint8 ||
765 Width == EfiPciIoWidthFillUint16 ||
766 Width == EfiPciIoWidthFillUint32 ||
767 Width == EfiPciIoWidthFillUint64) {
768 return EFI_INVALID_PARAMETER;
769 }
770
771 Status = PciIoVerifyBarAccess (PciIoDevice, DestBarIndex, PciBarTypeMem, Width, Count, &DestOffset);
772 if (EFI_ERROR (Status)) {
773 return EFI_UNSUPPORTED;
774 }
775
776 Status = PciIoVerifyBarAccess (PciIoDevice, SrcBarIndex, PciBarTypeMem, Width, Count, &SrcOffset);
777 if (EFI_ERROR (Status)) {
778 return EFI_UNSUPPORTED;
779 }
780
781 Status = PciIoDevice->PciRootBridgeIo->CopyMem (
782 PciIoDevice->PciRootBridgeIo,
783 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,
784 DestOffset,
785 SrcOffset,
786 Count
787 );
788
789 if (EFI_ERROR (Status)) {
790 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
791 }
792
793 return Status;
794 }
795
796 /**
797 Provides the PCI controller-Cspecific addresses needed to access system memory.
798
799 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
800 @param Operation Indicates if the bus master is going to read or write to system memory.
801 @param HostAddress The system memory address to map to the PCI controller.
802 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
803 that were mapped.
804 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
805 access the hosts HostAddress.
806 @param Mapping A resulting value to pass to Unmap().
807
808 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
809 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
810 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
811 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
812 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
813
814 **/
815 EFI_STATUS
816 EFIAPI
817 PciIoMap (
818 IN EFI_PCI_IO_PROTOCOL *This,
819 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
820 IN VOID *HostAddress,
821 IN OUT UINTN *NumberOfBytes,
822 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
823 OUT VOID **Mapping
824 )
825 {
826 EFI_STATUS Status;
827 PCI_IO_DEVICE *PciIoDevice;
828
829 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
830
831 if (Operation < 0 || Operation >= EfiPciIoOperationMaximum) {
832 return EFI_INVALID_PARAMETER;
833 }
834
835 if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {
836 return EFI_INVALID_PARAMETER;
837 }
838
839 if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {
840 Operation = (EFI_PCI_IO_PROTOCOL_OPERATION) (Operation + EfiPciOperationBusMasterRead64);
841 }
842
843 Status = PciIoDevice->PciRootBridgeIo->Map (
844 PciIoDevice->PciRootBridgeIo,
845 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION) Operation,
846 HostAddress,
847 NumberOfBytes,
848 DeviceAddress,
849 Mapping
850 );
851
852 if (EFI_ERROR (Status)) {
853 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
854 }
855
856 return Status;
857 }
858
859 /**
860 Completes the Map() operation and releases any corresponding resources.
861
862 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
863 @param Mapping The mapping value returned from Map().
864
865 @retval EFI_SUCCESS The range was unmapped.
866 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
867
868 **/
869 EFI_STATUS
870 EFIAPI
871 PciIoUnmap (
872 IN EFI_PCI_IO_PROTOCOL *This,
873 IN VOID *Mapping
874 )
875 {
876 EFI_STATUS Status;
877 PCI_IO_DEVICE *PciIoDevice;
878
879 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
880
881 Status = PciIoDevice->PciRootBridgeIo->Unmap (
882 PciIoDevice->PciRootBridgeIo,
883 Mapping
884 );
885
886 if (EFI_ERROR (Status)) {
887 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
888 }
889
890 return Status;
891 }
892
893 /**
894 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer
895 mapping.
896
897 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
898 @param Type This parameter is not used and must be ignored.
899 @param MemoryType The type of memory to allocate, EfiBootServicesData or
900 EfiRuntimeServicesData.
901 @param Pages The number of pages to allocate.
902 @param HostAddress A pointer to store the base system memory address of the
903 allocated range.
904 @param Attributes The requested bit mask of attributes for the allocated range.
905
906 @retval EFI_SUCCESS The requested memory pages were allocated.
907 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
908 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
909 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
910 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
911
912 **/
913 EFI_STATUS
914 EFIAPI
915 PciIoAllocateBuffer (
916 IN EFI_PCI_IO_PROTOCOL *This,
917 IN EFI_ALLOCATE_TYPE Type,
918 IN EFI_MEMORY_TYPE MemoryType,
919 IN UINTN Pages,
920 OUT VOID **HostAddress,
921 IN UINT64 Attributes
922 )
923 {
924 EFI_STATUS Status;
925 PCI_IO_DEVICE *PciIoDevice;
926
927 if ((Attributes &
928 (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED))) != 0){
929 return EFI_UNSUPPORTED;
930 }
931
932 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
933
934 if ((PciIoDevice->Attributes & EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE) != 0) {
935 Attributes |= EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE;
936 }
937
938 Status = PciIoDevice->PciRootBridgeIo->AllocateBuffer (
939 PciIoDevice->PciRootBridgeIo,
940 Type,
941 MemoryType,
942 Pages,
943 HostAddress,
944 Attributes
945 );
946
947 if (EFI_ERROR (Status)) {
948 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
949 }
950
951 return Status;
952 }
953
954 /**
955 Frees memory that was allocated with AllocateBuffer().
956
957 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
958 @param Pages The number of pages to free.
959 @param HostAddress The base system memory address of the allocated range.
960
961 @retval EFI_SUCCESS The requested memory pages were freed.
962 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
963 was not allocated with AllocateBuffer().
964
965 **/
966 EFI_STATUS
967 EFIAPI
968 PciIoFreeBuffer (
969 IN EFI_PCI_IO_PROTOCOL *This,
970 IN UINTN Pages,
971 IN VOID *HostAddress
972 )
973 {
974 EFI_STATUS Status;
975 PCI_IO_DEVICE *PciIoDevice;
976
977 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
978
979 Status = PciIoDevice->PciRootBridgeIo->FreeBuffer (
980 PciIoDevice->PciRootBridgeIo,
981 Pages,
982 HostAddress
983 );
984
985 if (EFI_ERROR (Status)) {
986 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
987 }
988
989 return Status;
990 }
991
992 /**
993 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
994
995 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
996
997 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
998 bridge to system memory.
999 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
1000 host bridge due to a hardware error.
1001
1002 **/
1003 EFI_STATUS
1004 EFIAPI
1005 PciIoFlush (
1006 IN EFI_PCI_IO_PROTOCOL *This
1007 )
1008 {
1009 EFI_STATUS Status;
1010 PCI_IO_DEVICE *PciIoDevice;
1011
1012 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1013
1014 Status = PciIoDevice->PciRootBridgeIo->Flush (
1015 PciIoDevice->PciRootBridgeIo
1016 );
1017 if (EFI_ERROR (Status)) {
1018 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
1019 }
1020
1021 return Status;
1022 }
1023
1024 /**
1025 Retrieves this PCI controller's current PCI bus number, device number, and function number.
1026
1027 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1028 @param SegmentNumber The PCI controller's current PCI segment number.
1029 @param BusNumber The PCI controller's current PCI bus number.
1030 @param DeviceNumber The PCI controller's current PCI device number.
1031 @param FunctionNumber The PCI controller's current PCI function number.
1032
1033 @retval EFI_SUCCESS The PCI controller location was returned.
1034 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1035
1036 **/
1037 EFI_STATUS
1038 EFIAPI
1039 PciIoGetLocation (
1040 IN EFI_PCI_IO_PROTOCOL *This,
1041 OUT UINTN *Segment,
1042 OUT UINTN *Bus,
1043 OUT UINTN *Device,
1044 OUT UINTN *Function
1045 )
1046 {
1047 PCI_IO_DEVICE *PciIoDevice;
1048
1049 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1050
1051 if (Segment == NULL || Bus == NULL || Device == NULL || Function == NULL) {
1052 return EFI_INVALID_PARAMETER;
1053 }
1054
1055 *Segment = PciIoDevice->PciRootBridgeIo->SegmentNumber;
1056 *Bus = PciIoDevice->BusNumber;
1057 *Device = PciIoDevice->DeviceNumber;
1058 *Function = PciIoDevice->FunctionNumber;
1059
1060 return EFI_SUCCESS;
1061 }
1062
1063 /**
1064 Check BAR type for PCI resource.
1065
1066 @param PciIoDevice PCI device instance
1067 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
1068 base address for the memory or I/O operation to perform.
1069 @param BarType Memory or I/O
1070
1071 @return whether Pci device's bar type is same with input BarType.
1072 **/
1073 BOOLEAN
1074 CheckBarType (
1075 IN PCI_IO_DEVICE *PciIoDevice,
1076 UINT8 BarIndex,
1077 PCI_BAR_TYPE BarType
1078 )
1079 {
1080 switch (BarType) {
1081
1082 case PciBarTypeMem:
1083
1084 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem32 &&
1085 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem32 &&
1086 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypePMem64 &&
1087 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeMem64 ) {
1088 return FALSE;
1089 }
1090
1091 return TRUE;
1092
1093 case PciBarTypeIo:
1094 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo32 &&
1095 PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeIo16){
1096 return FALSE;
1097 }
1098
1099 return TRUE;
1100
1101 default:
1102 break;
1103 }
1104
1105 return FALSE;
1106 }
1107
1108 /**
1109 Set/Disable new attributes to a Root Bridge
1110
1111 @param PciIoDevice Pci device instance
1112 @param Attributes New attribute want to be set
1113 @param Operation Set or Disable
1114
1115 @retval EFI_UNSUPPORTED If root bridge does not support change attribute
1116 @retval EFI_SUCCESS Success operation.
1117 **/
1118 EFI_STATUS
1119 ModifyRootBridgeAttributes (
1120 IN PCI_IO_DEVICE *PciIoDevice,
1121 IN UINT64 Attributes,
1122 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation
1123 )
1124 {
1125 UINT64 PciRootBridgeSupports;
1126 UINT64 PciRootBridgeAttributes;
1127 UINT64 NewPciRootBridgeAttributes;
1128 EFI_STATUS Status;
1129
1130 //
1131 // Get the current attributes of this PCI device's PCI Root Bridge
1132 //
1133 Status = PciIoDevice->PciRootBridgeIo->GetAttributes (
1134 PciIoDevice->PciRootBridgeIo,
1135 &PciRootBridgeSupports,
1136 &PciRootBridgeAttributes
1137 );
1138 if (EFI_ERROR (Status)) {
1139 return EFI_UNSUPPORTED;
1140 }
1141
1142 //
1143 // Record the new attribute of the Root Bridge
1144 //
1145 if (Operation == EfiPciIoAttributeOperationEnable) {
1146 NewPciRootBridgeAttributes = PciRootBridgeAttributes | Attributes;
1147 } else {
1148 NewPciRootBridgeAttributes = PciRootBridgeAttributes & (~Attributes);
1149 }
1150
1151 //
1152 // Call the PCI Root Bridge to attempt to modify the attributes
1153 //
1154 if ((NewPciRootBridgeAttributes ^ PciRootBridgeAttributes) != 0) {
1155
1156 Status = PciIoDevice->PciRootBridgeIo->SetAttributes (
1157 PciIoDevice->PciRootBridgeIo,
1158 NewPciRootBridgeAttributes,
1159 NULL,
1160 NULL
1161 );
1162 if (EFI_ERROR (Status)) {
1163 //
1164 // The PCI Root Bridge could not modify the attributes, so return the error.
1165 //
1166 return EFI_UNSUPPORTED;
1167 }
1168 }
1169
1170 //
1171 // Also update the attributes for this Root Bridge structure
1172 //
1173 PciIoDevice->Attributes = NewPciRootBridgeAttributes;
1174 return EFI_SUCCESS;
1175
1176 }
1177
1178 /**
1179 Check whether this device can be enable/disable to snoop
1180
1181 @param PciIoDevice Pci device instance
1182 @param Operation Enable/Disable
1183
1184 @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop
1185 @retval EFI_SUCCESS Snoop can be supported.
1186 **/
1187 EFI_STATUS
1188 SupportPaletteSnoopAttributes (
1189 IN PCI_IO_DEVICE *PciIoDevice,
1190 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation
1191 )
1192 {
1193 PCI_IO_DEVICE *Temp;
1194 UINT16 VGACommand;
1195
1196 //
1197 // Snoop attribute can be only modified by GFX
1198 //
1199 if (!IS_PCI_GFX (&PciIoDevice->Pci)) {
1200 return EFI_UNSUPPORTED;
1201 }
1202
1203 //
1204 // Get the boot VGA on the same segement
1205 //
1206 Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);
1207
1208 if (Temp == NULL) {
1209 //
1210 // If there is no VGA device on the segement, set
1211 // this graphics card to decode the palette range
1212 //
1213 return EFI_SUCCESS;
1214 }
1215
1216 //
1217 // Check these two agents are on the same path
1218 //
1219 if (!PciDevicesOnTheSamePath (Temp, PciIoDevice)) {
1220 //
1221 // they are not on the same path, so snoop can be enabled or disabled
1222 //
1223 return EFI_SUCCESS;
1224 }
1225 //
1226 // Check if they are on the same bus
1227 //
1228 if (Temp->Parent == PciIoDevice->Parent) {
1229
1230 PCI_READ_COMMAND_REGISTER (Temp, &VGACommand);
1231
1232 //
1233 // If they are on the same bus, either one can
1234 // be set to snoop, the other set to decode
1235 //
1236 if ((VGACommand & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {
1237 //
1238 // VGA has set to snoop, so GFX can be only set to disable snoop
1239 //
1240 if (Operation == EfiPciIoAttributeOperationEnable) {
1241 return EFI_UNSUPPORTED;
1242 }
1243 } else {
1244 //
1245 // VGA has disabled to snoop, so GFX can be only enabled
1246 //
1247 if (Operation == EfiPciIoAttributeOperationDisable) {
1248 return EFI_UNSUPPORTED;
1249 }
1250 }
1251
1252 return EFI_SUCCESS;
1253 }
1254
1255 //
1256 // If they are on the same path but on the different bus
1257 // The first agent is set to snoop, the second one set to
1258 // decode
1259 //
1260
1261 if (Temp->BusNumber < PciIoDevice->BusNumber) {
1262 //
1263 // GFX should be set to decode
1264 //
1265 if (Operation == EfiPciIoAttributeOperationDisable) {
1266 PCI_ENABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
1267 Temp->Attributes |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;
1268 } else {
1269 return EFI_UNSUPPORTED;
1270 }
1271
1272 } else {
1273 //
1274 // GFX should be set to snoop
1275 //
1276 if (Operation == EfiPciIoAttributeOperationEnable) {
1277 PCI_DISABLE_COMMAND_REGISTER (Temp, EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
1278 Temp->Attributes &= (~EFI_PCI_COMMAND_VGA_PALETTE_SNOOP);
1279 } else {
1280 return EFI_UNSUPPORTED;
1281 }
1282
1283 }
1284
1285 return EFI_SUCCESS;
1286 }
1287
1288 /**
1289 Performs an operation on the attributes that this PCI controller supports. The operations include
1290 getting the set of supported attributes, retrieving the current attributes, setting the current
1291 attributes, enabling attributes, and disabling attributes.
1292
1293 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1294 @param Operation The operation to perform on the attributes for this PCI controller.
1295 @param Attributes The mask of attributes that are used for Set, Enable, and Disable
1296 operations.
1297 @param Result A pointer to the result mask of attributes that are returned for the Get
1298 and Supported operations.
1299
1300 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.
1301 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1302 @retval EFI_UNSUPPORTED one or more of the bits set in
1303 Attributes are not supported by this PCI controller or one of
1304 its parent bridges when Operation is Set, Enable or Disable.
1305
1306 **/
1307 EFI_STATUS
1308 EFIAPI
1309 PciIoAttributes (
1310 IN EFI_PCI_IO_PROTOCOL * This,
1311 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
1312 IN UINT64 Attributes,
1313 OUT UINT64 *Result OPTIONAL
1314 )
1315 {
1316 EFI_STATUS Status;
1317
1318 PCI_IO_DEVICE *PciIoDevice;
1319 PCI_IO_DEVICE *UpStreamBridge;
1320 PCI_IO_DEVICE *Temp;
1321
1322 UINT64 Supports;
1323 UINT64 UpStreamAttributes;
1324 UINT16 BridgeControl;
1325 UINT16 Command;
1326
1327 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1328
1329 switch (Operation) {
1330 case EfiPciIoAttributeOperationGet:
1331 if (Result == NULL) {
1332 return EFI_INVALID_PARAMETER;
1333 }
1334
1335 *Result = PciIoDevice->Attributes;
1336 return EFI_SUCCESS;
1337
1338 case EfiPciIoAttributeOperationSupported:
1339 if (Result == NULL) {
1340 return EFI_INVALID_PARAMETER;
1341 }
1342
1343 *Result = PciIoDevice->Supports;
1344 return EFI_SUCCESS;
1345
1346 case EfiPciIoAttributeOperationSet:
1347 Status = PciIoDevice->PciIo.Attributes (
1348 &(PciIoDevice->PciIo),
1349 EfiPciIoAttributeOperationEnable,
1350 Attributes,
1351 NULL
1352 );
1353 if (EFI_ERROR (Status)) {
1354 return EFI_UNSUPPORTED;
1355 }
1356
1357 Status = PciIoDevice->PciIo.Attributes (
1358 &(PciIoDevice->PciIo),
1359 EfiPciIoAttributeOperationDisable,
1360 (~Attributes) & (PciIoDevice->Supports),
1361 NULL
1362 );
1363 if (EFI_ERROR (Status)) {
1364 return EFI_UNSUPPORTED;
1365 }
1366
1367 return EFI_SUCCESS;
1368
1369 case EfiPciIoAttributeOperationEnable:
1370 case EfiPciIoAttributeOperationDisable:
1371 break;
1372
1373 default:
1374 return EFI_INVALID_PARAMETER;
1375 }
1376 //
1377 // Just a trick for ENABLE attribute
1378 // EFI_PCI_DEVICE_ENABLE is not defined in UEFI spec, which is the internal usage.
1379 // So, this logic doesn't confrom to UEFI spec, which should be removed.
1380 // But this trick logic is still kept for some binary drivers that depend on it.
1381 //
1382 if ((Attributes & EFI_PCI_DEVICE_ENABLE) == EFI_PCI_DEVICE_ENABLE) {
1383 Attributes &= (PciIoDevice->Supports);
1384
1385 //
1386 // Raise the EFI_P_PC_ENABLE Status code
1387 //
1388 REPORT_STATUS_CODE_WITH_DEVICE_PATH (
1389 EFI_PROGRESS_CODE,
1390 EFI_IO_BUS_PCI | EFI_P_PC_ENABLE,
1391 PciIoDevice->DevicePath
1392 );
1393 }
1394
1395 //
1396 // If no attributes can be supported, then return.
1397 // Otherwise, set the attributes that it can support.
1398 //
1399 Supports = (PciIoDevice->Supports) & Attributes;
1400 if (Supports != Attributes) {
1401 return EFI_UNSUPPORTED;
1402 }
1403
1404 //
1405 // For Root Bridge, just call RootBridgeIo to set attributes;
1406 //
1407 if (PciIoDevice->Parent == NULL) {
1408 Status = ModifyRootBridgeAttributes (PciIoDevice, Attributes, Operation);
1409 return Status;
1410 }
1411
1412 Command = 0;
1413 BridgeControl = 0;
1414
1415 //
1416 // Check VGA and VGA16, they can not be set at the same time
1417 //
1418 if (((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&
1419 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||
1420 ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO) != 0 &&
1421 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ||
1422 ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&
1423 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_IO_16) != 0) ||
1424 ((Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO) != 0 &&
1425 (Attributes & EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16) != 0) ) {
1426 return EFI_UNSUPPORTED;
1427 }
1428
1429 //
1430 // For PPB & P2C, set relevant attribute bits
1431 //
1432 if (IS_PCI_BRIDGE (&PciIoDevice->Pci) || IS_CARDBUS_BRIDGE (&PciIoDevice->Pci)) {
1433
1434 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {
1435 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA;
1436 }
1437
1438 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_ISA_IO) != 0) {
1439 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_ISA;
1440 }
1441
1442 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {
1443 Command |= EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO;
1444 }
1445
1446 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16)) != 0) {
1447 BridgeControl |= EFI_PCI_BRIDGE_CONTROL_VGA_16;
1448 }
1449
1450 } else {
1451 //
1452 // Do with the attributes on VGA
1453 // Only for VGA's legacy resource, we just can enable once.
1454 //
1455 if ((Attributes &
1456 (EFI_PCI_IO_ATTRIBUTE_VGA_IO |
1457 EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 |
1458 EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY)) != 0) {
1459 //
1460 // Check if a VGA has been enabled before enabling a new one
1461 //
1462 if (Operation == EfiPciIoAttributeOperationEnable) {
1463 //
1464 // Check if there have been an active VGA device on the same segment
1465 //
1466 Temp = ActiveVGADeviceOnTheSameSegment (PciIoDevice);
1467 if (Temp != NULL && Temp != PciIoDevice) {
1468 //
1469 // An active VGA has been detected, so can not enable another
1470 //
1471 return EFI_UNSUPPORTED;
1472 }
1473 }
1474 }
1475
1476 //
1477 // Do with the attributes on GFX
1478 //
1479 if ((Attributes & (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16)) != 0) {
1480
1481 if (Operation == EfiPciIoAttributeOperationEnable) {
1482 //
1483 // Check if snoop can be enabled in current configuration
1484 //
1485 Status = SupportPaletteSnoopAttributes (PciIoDevice, Operation);
1486
1487 if (EFI_ERROR (Status)) {
1488
1489 //
1490 // Enable operation is forbidden, so mask the bit in attributes
1491 // so as to keep consistent with the actual Status
1492 //
1493 // Attributes &= (~EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO);
1494 //
1495 //
1496 //
1497 return EFI_UNSUPPORTED;
1498
1499 }
1500 }
1501
1502 //
1503 // It can be supported, so get ready to set the bit
1504 //
1505 Command |= EFI_PCI_COMMAND_VGA_PALETTE_SNOOP;
1506 }
1507 }
1508
1509 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_IO) != 0) {
1510 Command |= EFI_PCI_COMMAND_IO_SPACE;
1511 }
1512
1513 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_MEMORY) != 0) {
1514 Command |= EFI_PCI_COMMAND_MEMORY_SPACE;
1515 }
1516
1517 if ((Attributes & EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) != 0) {
1518 Command |= EFI_PCI_COMMAND_BUS_MASTER;
1519 }
1520 //
1521 // The upstream bridge should be also set to revelant attribute
1522 // expect for IO, Mem and BusMaster
1523 //
1524 UpStreamAttributes = Attributes &
1525 (~(EFI_PCI_IO_ATTRIBUTE_IO |
1526 EFI_PCI_IO_ATTRIBUTE_MEMORY |
1527 EFI_PCI_IO_ATTRIBUTE_BUS_MASTER
1528 )
1529 );
1530 UpStreamBridge = PciIoDevice->Parent;
1531
1532 if (Operation == EfiPciIoAttributeOperationEnable) {
1533 //
1534 // Enable relevant attributes to command register and bridge control register
1535 //
1536 Status = PCI_ENABLE_COMMAND_REGISTER (PciIoDevice, Command);
1537 if (BridgeControl != 0) {
1538 Status = PCI_ENABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);
1539 }
1540
1541 PciIoDevice->Attributes |= Attributes;
1542
1543 //
1544 // Enable attributes of the upstream bridge
1545 //
1546 Status = UpStreamBridge->PciIo.Attributes (
1547 &(UpStreamBridge->PciIo),
1548 EfiPciIoAttributeOperationEnable,
1549 UpStreamAttributes,
1550 NULL
1551 );
1552 } else {
1553
1554 //
1555 // Disable relevant attributes to command register and bridge control register
1556 //
1557 Status = PCI_DISABLE_COMMAND_REGISTER (PciIoDevice, Command);
1558 if (BridgeControl != 0) {
1559 Status = PCI_DISABLE_BRIDGE_CONTROL_REGISTER (PciIoDevice, BridgeControl);
1560 }
1561
1562 PciIoDevice->Attributes &= (~Attributes);
1563 Status = EFI_SUCCESS;
1564
1565 }
1566
1567 if (EFI_ERROR (Status)) {
1568 ReportErrorStatusCode (PciIoDevice, EFI_IO_BUS_PCI | EFI_IOB_EC_CONTROLLER_ERROR);
1569 }
1570
1571 return Status;
1572 }
1573
1574 /**
1575 Gets the attributes that this PCI controller supports setting on a BAR using
1576 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.
1577
1578 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1579 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
1580 base address for resource range. The legal range for this field is 0..5.
1581 @param Supports A pointer to the mask of attributes that this PCI controller supports
1582 setting for this BAR with SetBarAttributes().
1583 @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current
1584 configuration of this BAR of the PCI controller.
1585
1586 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI
1587 controller supports are returned in Supports. If Resources
1588 is not NULL, then the ACPI 2.0 resource descriptors that the PCI
1589 controller is currently using are returned in Resources.
1590 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
1591 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
1592 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate
1593 Resources.
1594
1595 **/
1596 EFI_STATUS
1597 EFIAPI
1598 PciIoGetBarAttributes (
1599 IN EFI_PCI_IO_PROTOCOL * This,
1600 IN UINT8 BarIndex,
1601 OUT UINT64 *Supports, OPTIONAL
1602 OUT VOID **Resources OPTIONAL
1603 )
1604 {
1605
1606 UINT8 *Configuration;
1607 UINT8 NumConfig;
1608 PCI_IO_DEVICE *PciIoDevice;
1609 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
1610 EFI_ACPI_END_TAG_DESCRIPTOR *PtrEnd;
1611
1612 NumConfig = 0;
1613
1614 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1615
1616 if (Supports == NULL && Resources == NULL) {
1617 return EFI_INVALID_PARAMETER;
1618 }
1619
1620 if (BarIndex >= PCI_MAX_BAR) {
1621 return EFI_UNSUPPORTED;
1622 }
1623
1624 //
1625 // This driver does not support modifications to the WRITE_COMBINE or
1626 // CACHED attributes for BAR ranges.
1627 //
1628 if (Supports != NULL) {
1629 *Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;
1630 }
1631
1632 if (Resources != NULL) {
1633
1634 if (PciIoDevice->PciBar[BarIndex].BarType != PciBarTypeUnknown) {
1635 NumConfig = 1;
1636 }
1637
1638 Configuration = AllocatePool (sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
1639 if (Configuration == NULL) {
1640 return EFI_OUT_OF_RESOURCES;
1641 }
1642
1643 ZeroMem (
1644 Configuration,
1645 sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) * NumConfig + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)
1646 );
1647
1648 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
1649
1650 if (NumConfig == 1) {
1651 Ptr->Desc = ACPI_ADDRESS_SPACE_DESCRIPTOR;
1652 Ptr->Len = sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) - 3;
1653
1654 Ptr->AddrRangeMin = PciIoDevice->PciBar[BarIndex].BaseAddress;
1655 Ptr->AddrLen = PciIoDevice->PciBar[BarIndex].Length;
1656 Ptr->AddrRangeMax = PciIoDevice->PciBar[BarIndex].Alignment;
1657
1658 switch (PciIoDevice->PciBar[BarIndex].BarType) {
1659 case PciBarTypeIo16:
1660 case PciBarTypeIo32:
1661 //
1662 // Io
1663 //
1664 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
1665 break;
1666
1667 case PciBarTypeMem32:
1668 //
1669 // Mem
1670 //
1671 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1672 //
1673 // 32 bit
1674 //
1675 Ptr->AddrSpaceGranularity = 32;
1676 break;
1677
1678 case PciBarTypePMem32:
1679 //
1680 // Mem
1681 //
1682 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1683 //
1684 // prefechable
1685 //
1686 Ptr->SpecificFlag = 0x6;
1687 //
1688 // 32 bit
1689 //
1690 Ptr->AddrSpaceGranularity = 32;
1691 break;
1692
1693 case PciBarTypeMem64:
1694 //
1695 // Mem
1696 //
1697 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1698 //
1699 // 64 bit
1700 //
1701 Ptr->AddrSpaceGranularity = 64;
1702 break;
1703
1704 case PciBarTypePMem64:
1705 //
1706 // Mem
1707 //
1708 Ptr->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
1709 //
1710 // prefechable
1711 //
1712 Ptr->SpecificFlag = 0x6;
1713 //
1714 // 64 bit
1715 //
1716 Ptr->AddrSpaceGranularity = 64;
1717 break;
1718
1719 default:
1720 break;
1721 }
1722
1723 Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) ((UINT8 *) Ptr + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR));
1724 }
1725
1726 //
1727 // put the checksum
1728 //
1729 PtrEnd = (EFI_ACPI_END_TAG_DESCRIPTOR *) ((UINT8 *) Ptr);
1730 PtrEnd->Desc = ACPI_END_TAG_DESCRIPTOR;
1731 PtrEnd->Checksum = 0;
1732
1733 *Resources = Configuration;
1734 }
1735
1736 return EFI_SUCCESS;
1737 }
1738
1739 /**
1740 Sets the attributes for a range of a BAR on a PCI controller.
1741
1742 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
1743 @param Attributes The mask of attributes to set for the resource range specified by
1744 BarIndex, Offset, and Length.
1745 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
1746 base address for resource range. The legal range for this field is 0..5.
1747 @param Offset A pointer to the BAR relative base address of the resource range to be
1748 modified by the attributes specified by Attributes.
1749 @param Length A pointer to the length of the resource range to be modified by the
1750 attributes specified by Attributes.
1751
1752 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource
1753 range specified by BarIndex, Offset, and Length were
1754 set on the PCI controller, and the actual resource range is returned
1755 in Offset and Length.
1756 @retval EFI_INVALID_PARAMETER Offset or Length is NULL.
1757 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
1758 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the
1759 resource range specified by BarIndex, Offset, and
1760 Length.
1761
1762 **/
1763 EFI_STATUS
1764 EFIAPI
1765 PciIoSetBarAttributes (
1766 IN EFI_PCI_IO_PROTOCOL *This,
1767 IN UINT64 Attributes,
1768 IN UINT8 BarIndex,
1769 IN OUT UINT64 *Offset,
1770 IN OUT UINT64 *Length
1771 )
1772 {
1773 EFI_STATUS Status;
1774 PCI_IO_DEVICE *PciIoDevice;
1775 UINT64 NonRelativeOffset;
1776 UINT64 Supports;
1777
1778 PciIoDevice = PCI_IO_DEVICE_FROM_PCI_IO_THIS (This);
1779
1780 //
1781 // Make sure Offset and Length are not NULL
1782 //
1783 if (Offset == NULL || Length == NULL) {
1784 return EFI_INVALID_PARAMETER;
1785 }
1786
1787 if (PciIoDevice->PciBar[BarIndex].BarType == PciBarTypeUnknown) {
1788 return EFI_UNSUPPORTED;
1789 }
1790 //
1791 // This driver does not support setting the WRITE_COMBINE or the CACHED attributes.
1792 // If Attributes is not 0, then return EFI_UNSUPPORTED.
1793 //
1794 Supports = PciIoDevice->Supports & EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED & EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE;
1795
1796 if (Attributes != (Attributes & Supports)) {
1797 return EFI_UNSUPPORTED;
1798 }
1799 //
1800 // Attributes must be supported. Make sure the BAR range describd by BarIndex, Offset, and
1801 // Length are valid for this PCI device.
1802 //
1803 NonRelativeOffset = *Offset;
1804 Status = PciIoVerifyBarAccess (
1805 PciIoDevice,
1806 BarIndex,
1807 PciBarTypeMem,
1808 EfiPciIoWidthUint8,
1809 (UINT32) *Length,
1810 &NonRelativeOffset
1811 );
1812 if (EFI_ERROR (Status)) {
1813 return EFI_UNSUPPORTED;
1814 }
1815
1816 return EFI_SUCCESS;
1817 }
1818
1819 /**
1820 Program parent bridge's attribute recurrently.
1821
1822 @param PciIoDevice Child Pci device instance
1823 @param Operation The operation to perform on the attributes for this PCI controller.
1824 @param Attributes The mask of attributes that are used for Set, Enable, and Disable
1825 operations.
1826
1827 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.
1828 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
1829 @retval EFI_UNSUPPORTED one or more of the bits set in
1830 Attributes are not supported by this PCI controller or one of
1831 its parent bridges when Operation is Set, Enable or Disable.
1832
1833 **/
1834 EFI_STATUS
1835 UpStreamBridgesAttributes (
1836 IN PCI_IO_DEVICE *PciIoDevice,
1837 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
1838 IN UINT64 Attributes
1839 )
1840 {
1841 PCI_IO_DEVICE *Parent;
1842 EFI_PCI_IO_PROTOCOL *PciIo;
1843
1844 Parent = PciIoDevice->Parent;
1845
1846 while (Parent != NULL && IS_PCI_BRIDGE (&Parent->Pci)) {
1847
1848 //
1849 // Get the PciIo Protocol
1850 //
1851 PciIo = &Parent->PciIo;
1852
1853 PciIo->Attributes (PciIo, Operation, Attributes, NULL);
1854
1855 Parent = Parent->Parent;
1856 }
1857
1858 return EFI_SUCCESS;
1859 }
1860
1861 /**
1862 Test whether two Pci device has same parent bridge.
1863
1864 @param PciDevice1 the frist pci device for testing
1865 @param PciDevice2 the second pci device for testing
1866
1867 @return whether two Pci device has same parent bridge.
1868 **/
1869 BOOLEAN
1870 PciDevicesOnTheSamePath (
1871 IN PCI_IO_DEVICE *PciDevice1,
1872 IN PCI_IO_DEVICE *PciDevice2
1873 )
1874 {
1875 BOOLEAN Existed1;
1876 BOOLEAN Existed2;
1877
1878 if (PciDevice1->Parent == PciDevice2->Parent) {
1879 return TRUE;
1880 }
1881
1882 Existed1 = PciDeviceExisted (PciDevice1->Parent, PciDevice2);
1883 Existed2 = PciDeviceExisted (PciDevice2->Parent, PciDevice1);
1884
1885 return (BOOLEAN) (Existed1 || Existed2);
1886 }
1887
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