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1 /**@file
2
3 Copyright (c) 2006, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 **/
13
14
15 #ifndef _EFI_PCI_IO_PROTOCOL_H
16 #define _EFI_PCI_IO_PROTOCOL_H
17
18 /**
19 Initializes a PCI I/O Instance
20
21 @param PciIoDevice Pci device instance
22
23 @retval EFI_SUCCESS Success operation
24 **/
25 EFI_STATUS
26 InitializePciIoInstance (
27 PCI_IO_DEVICE *PciIoDevice
28 )
29 ;
30
31 /**
32 Verifies access to a PCI Base Address Register (BAR)
33
34 @param PciIoDevice Pci device instance
35 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
36 base address for the memory or I/O operation to perform.
37 @param Type Operation type could be memory or I/O
38 @param Width Signifies the width of the memory or I/O operations.
39 @param Count The number of memory or I/O operations to perform.
40 @param Offset The offset within the PCI configuration space for the PCI controller.
41
42 @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.
43 @retval EFI_SUCCESS Success Operation.
44 **/
45 EFI_STATUS
46 PciIoVerifyBarAccess (
47 PCI_IO_DEVICE *PciIoDevice,
48 UINT8 BarIndex,
49 PCI_BAR_TYPE Type,
50 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
51 IN UINTN Count,
52 UINT64 *Offset
53 )
54 ;
55
56 /**
57 Verifies access to a PCI Config Header
58
59 @param PciIoDevice Pci device instance
60 @param Width Signifies the width of the memory or I/O operations.
61 @param Count The number of memory or I/O operations to perform.
62 @param Offset The offset within the PCI configuration space for the PCI controller.
63
64 @retval EFI_INVALID_PARAMETER Invalid Width
65 @retval EFI_UNSUPPORTED Offset overflow
66 @retval EFI_SUCCESS Success operation
67 **/
68 EFI_STATUS
69 PciIoVerifyConfigAccess (
70 PCI_IO_DEVICE *PciIoDevice,
71 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
72 IN UINTN Count,
73 IN UINT64 *Offset
74 )
75 ;
76
77 /**
78 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
79 satisfied or after a defined duration.
80
81 @param This Pointer to protocol instance of EFI_PCI_IO_PROTOCOL
82 @param Width Signifies the width of the memory or I/O operations.
83 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
84 base address for the memory or I/O operation to perform.
85 @param Offset The offset within the PCI configuration space for the PCI controller.
86 @param Mask Mask used for the polling criteria.
87 @param Value The comparison value used for the polling exit criteria.
88 @param Delay The number of 100 ns units to poll.
89 @param Result Pointer to the last value read from the memory location.
90
91 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
92 @retval EFI_TIMEOUT Delay expired before a match occurred.
93 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
94 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
95 **/
96 EFI_STATUS
97 EFIAPI
98 PciIoPollMem (
99 IN EFI_PCI_IO_PROTOCOL *This,
100 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
101 IN UINT8 BarIndex,
102 IN UINT64 Offset,
103 IN UINT64 Mask,
104 IN UINT64 Value,
105 IN UINT64 Delay,
106 OUT UINT64 *Result
107 )
108 ;
109
110 /**
111 Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
112 satisfied or after a defined duration.
113
114 @param This A pointer to the EFI_PCI_IO_PROTOCOL.
115 @param Width Signifies the width of the memory or I/O operations.
116 @param Address The base address of the memory or I/O operations.
117 @param Mask Mask used for the polling criteria.
118 @param Value The comparison value used for the polling exit criteria.
119 @param Delay The number of 100 ns units to poll.
120 @param Result Pointer to the last value read from the memory location.
121
122 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
123 @retval EFI_TIMEOUT Delay expired before a match occurred.
124 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
125 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
126
127 **/
128 EFI_STATUS
129 EFIAPI
130 PciIoPollIo (
131 IN EFI_PCI_IO_PROTOCOL *This,
132 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
133 IN UINT8 BarIndex,
134 IN UINT64 Offset,
135 IN UINT64 Mask,
136 IN UINT64 Value,
137 IN UINT64 Delay,
138 OUT UINT64 *Result
139 )
140 ;
141
142 /**
143 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
144
145 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
146 @param Width Signifies the width of the memory or I/O operations.
147 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
148 base address for the memory or I/O operation to perform.
149 @param Offset The offset within the selected BAR to start the memory or I/O operation.
150 @param Count The number of memory or I/O operations to perform.
151 @param Buffer For read operations, the destination buffer to store the results. For write
152 operations, the source buffer to write data from.
153
154 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
155 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
156 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
157 valid for the PCI BAR specified by BarIndex.
158 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
159 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
160
161 **/
162 EFI_STATUS
163 EFIAPI
164 PciIoMemRead (
165 IN EFI_PCI_IO_PROTOCOL *This,
166 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
167 IN UINT8 BarIndex,
168 IN UINT64 Offset,
169 IN UINTN Count,
170 IN OUT VOID *Buffer
171 )
172 ;
173
174 /**
175 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
176
177 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
178 @param Width Signifies the width of the memory or I/O operations.
179 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
180 base address for the memory or I/O operation to perform.
181 @param Offset The offset within the selected BAR to start the memory or I/O operation.
182 @param Count The number of memory or I/O operations to perform.
183 @param Buffer For read operations, the destination buffer to store the results. For write
184 operations, the source buffer to write data from.
185
186 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
187 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
188 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
189 valid for the PCI BAR specified by BarIndex.
190 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
191 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
192
193 **/
194 EFI_STATUS
195 EFIAPI
196 PciIoMemWrite (
197 IN EFI_PCI_IO_PROTOCOL *This,
198 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
199 IN UINT8 BarIndex,
200 IN UINT64 Offset,
201 IN UINTN Count,
202 IN OUT VOID *Buffer
203 )
204 ;
205
206 /**
207 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
208
209 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
210 @param Width Signifies the width of the memory or I/O operations.
211 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
212 base address for the memory or I/O operation to perform.
213 @param Offset The offset within the selected BAR to start the memory or I/O operation.
214 @param Count The number of memory or I/O operations to perform.
215 @param Buffer For read operations, the destination buffer to store the results. For write
216 operations, the source buffer to write data from.
217
218 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
219 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
220 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
221 valid for the PCI BAR specified by BarIndex.
222 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
223 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
224
225 **/
226 EFI_STATUS
227 EFIAPI
228 PciIoIoRead (
229 IN EFI_PCI_IO_PROTOCOL *This,
230 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
231 IN UINT8 BarIndex,
232 IN UINT64 Offset,
233 IN UINTN Count,
234 IN OUT VOID *Buffer
235 )
236 ;
237
238 /**
239 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
240
241 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
242 @param Width Signifies the width of the memory or I/O operations.
243 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
244 base address for the memory or I/O operation to perform.
245 @param Offset The offset within the selected BAR to start the memory or I/O operation.
246 @param Count The number of memory or I/O operations to perform.
247 @param Buffer For read operations, the destination buffer to store the results. For write
248 operations, the source buffer to write data from.
249
250 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
251 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
252 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
253 valid for the PCI BAR specified by BarIndex.
254 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
255 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
256
257 **/
258 EFI_STATUS
259 EFIAPI
260 PciIoIoWrite (
261 IN EFI_PCI_IO_PROTOCOL *This,
262 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
263 IN UINT8 BarIndex,
264 IN UINT64 Offset,
265 IN UINTN Count,
266 IN OUT VOID *Buffer
267 )
268 ;
269
270 /**
271 Enable a PCI driver to access PCI controller registers in PCI configuration space.
272
273 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
274 @param Width Signifies the width of the memory operations.
275 @param Offset The offset within the PCI configuration space for the PCI controller.
276 @param Count The number of PCI configuration operations to perform.
277 @param Buffer For read operations, the destination buffer to store the results. For write
278 operations, the source buffer to write data from.
279
280
281 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
282 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
283 valid for the PCI configuration header of the PCI controller.
284 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
285 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
286
287 **/
288 EFI_STATUS
289 EFIAPI
290 PciIoConfigRead (
291 IN EFI_PCI_IO_PROTOCOL *This,
292 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
293 IN UINT32 Offset,
294 IN UINTN Count,
295 IN OUT VOID *Buffer
296 )
297 ;
298
299 /**
300 Enable a PCI driver to access PCI controller registers in PCI configuration space.
301
302 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
303 @param Width Signifies the width of the memory operations.
304 @param Offset The offset within the PCI configuration space for the PCI controller.
305 @param Count The number of PCI configuration operations to perform.
306 @param Buffer For read operations, the destination buffer to store the results. For write
307 operations, the source buffer to write data from.
308
309
310 @retval EFI_SUCCESS The data was read from or written to the PCI controller.
311 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not
312 valid for the PCI configuration header of the PCI controller.
313 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
314 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
315
316 **/
317 EFI_STATUS
318 EFIAPI
319 PciIoConfigWrite (
320 IN EFI_PCI_IO_PROTOCOL *This,
321 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
322 IN UINT32 Offset,
323 IN UINTN Count,
324 IN OUT VOID *Buffer
325 )
326 ;
327
328 /**
329 Enables a PCI driver to copy one region of PCI memory space to another region of PCI
330 memory space.
331
332 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
333 @param Width Signifies the width of the memory operations.
334 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the
335 base address for the memory operation to perform.
336 @param DestOffset The destination offset within the BAR specified by DestBarIndex to
337 start the memory writes for the copy operation.
338 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the
339 base address for the memory operation to perform.
340 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start
341 the memory reads for the copy operation.
342 @param Count The number of memory operations to perform. Bytes moved is Width
343 size * Count, starting at DestOffset and SrcOffset.
344
345 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
346 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.
347 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.
348 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count
349 is not valid for the PCI BAR specified by DestBarIndex.
350 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is
351 not valid for the PCI BAR specified by SrcBarIndex.
352 @retval EFI_INVALID_PARAMETER Width is invalid.
353 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
354
355 **/
356 EFI_STATUS
357 EFIAPI
358 PciIoCopyMem (
359 IN EFI_PCI_IO_PROTOCOL *This,
360 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,
361 IN UINT8 DestBarIndex,
362 IN UINT64 DestOffset,
363 IN UINT8 SrcBarIndex,
364 IN UINT64 SrcOffset,
365 IN UINTN Count
366 )
367 ;
368
369 /**
370 Provides the PCI controller-Cspecific addresses needed to access system memory.
371
372 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
373 @param Operation Indicates if the bus master is going to read or write to system memory.
374 @param HostAddress The system memory address to map to the PCI controller.
375 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes
376 that were mapped.
377 @param DeviceAddress The resulting map address for the bus master PCI controller to use to
378 access the hosts HostAddress.
379 @param Mapping A resulting value to pass to Unmap().
380
381 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
382 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
383 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
384 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
385 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
386
387 **/
388 EFI_STATUS
389 EFIAPI
390 PciIoMap (
391 IN EFI_PCI_IO_PROTOCOL *This,
392 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,
393 IN VOID *HostAddress,
394 IN OUT UINTN *NumberOfBytes,
395 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
396 OUT VOID **Mapping
397 )
398 ;
399
400 /**
401 Completes the Map() operation and releases any corresponding resources.
402
403 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
404 @param Mapping The mapping value returned from Map().
405
406 @retval EFI_SUCCESS The range was unmapped.
407 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
408
409 **/
410 EFI_STATUS
411 EFIAPI
412 PciIoUnmap (
413 IN EFI_PCI_IO_PROTOCOL *This,
414 IN VOID *Mapping
415 )
416 ;
417
418 /**
419 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer
420 mapping.
421
422 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
423 @param Type This parameter is not used and must be ignored.
424 @param MemoryType The type of memory to allocate, EfiBootServicesData or
425 EfiRuntimeServicesData.
426 @param Pages The number of pages to allocate.
427 @param HostAddress A pointer to store the base system memory address of the
428 allocated range.
429 @param Attributes The requested bit mask of attributes for the allocated range.
430
431 @retval EFI_SUCCESS The requested memory pages were allocated.
432 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
433 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
434 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
435 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
436
437 **/
438 EFI_STATUS
439 EFIAPI
440 PciIoAllocateBuffer (
441 IN EFI_PCI_IO_PROTOCOL *This,
442 IN EFI_ALLOCATE_TYPE Type,
443 IN EFI_MEMORY_TYPE MemoryType,
444 IN UINTN Pages,
445 OUT VOID **HostAddress,
446 IN UINT64 Attributes
447 )
448 ;
449
450 /**
451 Frees memory that was allocated with AllocateBuffer().
452
453 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
454 @param Pages The number of pages to free.
455 @param HostAddress The base system memory address of the allocated range.
456
457 @retval EFI_SUCCESS The requested memory pages were freed.
458 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
459 was not allocated with AllocateBuffer().
460
461 **/
462 EFI_STATUS
463 EFIAPI
464 PciIoFreeBuffer (
465 IN EFI_PCI_IO_PROTOCOL *This,
466 IN UINTN Pages,
467 IN VOID *HostAddress
468 )
469 ;
470
471 /**
472 Flushes all PCI posted write transactions from a PCI host bridge to system memory.
473
474 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
475
476 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
477 bridge to system memory.
478 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
479 host bridge due to a hardware error.
480
481 **/
482 EFI_STATUS
483 EFIAPI
484 PciIoFlush (
485 IN EFI_PCI_IO_PROTOCOL *This
486 )
487 ;
488
489 /**
490 Retrieves this PCI controller's current PCI bus number, device number, and function number.
491
492 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
493 @param SegmentNumber The PCI controller's current PCI segment number.
494 @param BusNumber The PCI controller's current PCI bus number.
495 @param DeviceNumber The PCI controller's current PCI device number.
496 @param FunctionNumber The PCI controller's current PCI function number.
497
498 @retval EFI_SUCCESS The PCI controller location was returned.
499 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
500
501 **/
502 EFI_STATUS
503 EFIAPI
504 PciIoGetLocation (
505 IN EFI_PCI_IO_PROTOCOL *This,
506 OUT UINTN *Segment,
507 OUT UINTN *Bus,
508 OUT UINTN *Device,
509 OUT UINTN *Function
510 )
511 ;
512
513 /**
514 Check BAR type for PCI resource.
515
516 @param PciIoDevice PCI device instance
517 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
518 base address for the memory or I/O operation to perform.
519 @param BarType Memory or I/O
520
521 @return whether Pci device's bar type is same with input BarType.
522 **/
523 BOOLEAN
524 CheckBarType (
525 IN PCI_IO_DEVICE *PciIoDevice,
526 UINT8 BarIndex,
527 PCI_BAR_TYPE BarType
528 )
529 ;
530
531 /**
532 Set/Disable new attributes to a Root Bridge
533
534 @param PciIoDevice Pci device instance
535 @param Attributes New attribute want to be set
536 @param Operation Set or Disable
537
538 @retval EFI_UNSUPPORTED If root bridge does not support change attribute
539 @retval EFI_SUCCESS Success operation.
540 **/
541 EFI_STATUS
542 ModifyRootBridgeAttributes (
543 IN PCI_IO_DEVICE *PciIoDevice,
544 IN UINT64 Attributes,
545 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation
546 )
547 ;
548
549 /**
550 Check whether this device can be enable/disable to snoop
551
552 @param PciIoDevice Pci device instance
553 @param Operation Enable/Disable
554
555 @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop
556 @retval EFI_SUCCESS Snoop can be supported.
557 **/
558 EFI_STATUS
559 SupportPaletteSnoopAttributes (
560 IN PCI_IO_DEVICE *PciIoDevice,
561 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation
562 )
563 ;
564
565 /**
566 Performs an operation on the attributes that this PCI controller supports. The operations include
567 getting the set of supported attributes, retrieving the current attributes, setting the current
568 attributes, enabling attributes, and disabling attributes.
569
570 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
571 @param Operation The operation to perform on the attributes for this PCI controller.
572 @param Attributes The mask of attributes that are used for Set, Enable, and Disable
573 operations.
574 @param Result A pointer to the result mask of attributes that are returned for the Get
575 and Supported operations.
576
577 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.
578 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
579 @retval EFI_UNSUPPORTED one or more of the bits set in
580 Attributes are not supported by this PCI controller or one of
581 its parent bridges when Operation is Set, Enable or Disable.
582
583 **/
584 EFI_STATUS
585 EFIAPI
586 PciIoAttributes (
587 IN EFI_PCI_IO_PROTOCOL * This,
588 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
589 IN UINT64 Attributes,
590 OUT UINT64 *Result OPTIONAL
591 )
592 ;
593
594 /**
595 Gets the attributes that this PCI controller supports setting on a BAR using
596 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.
597
598 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
599 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
600 base address for resource range. The legal range for this field is 0..5.
601 @param Supports A pointer to the mask of attributes that this PCI controller supports
602 setting for this BAR with SetBarAttributes().
603 @param Resources A pointer to the ACPI 2.0 resource descriptors that describe the current
604 configuration of this BAR of the PCI controller.
605
606 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI
607 controller supports are returned in Supports. If Resources
608 is not NULL, then the ACPI 2.0 resource descriptors that the PCI
609 controller is currently using are returned in Resources.
610 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
611 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
612 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate
613 Resources.
614
615 **/
616 EFI_STATUS
617 EFIAPI
618 PciIoGetBarAttributes (
619 IN EFI_PCI_IO_PROTOCOL * This,
620 IN UINT8 BarIndex,
621 OUT UINT64 *Supports, OPTIONAL
622 OUT VOID **Resources OPTIONAL
623 )
624 ;
625
626 /**
627 Sets the attributes for a range of a BAR on a PCI controller.
628
629 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.
630 @param Attributes The mask of attributes to set for the resource range specified by
631 BarIndex, Offset, and Length.
632 @param BarIndex The BAR index of the standard PCI Configuration header to use as the
633 base address for resource range. The legal range for this field is 0..5.
634 @param Offset A pointer to the BAR relative base address of the resource range to be
635 modified by the attributes specified by Attributes.
636 @param Length A pointer to the length of the resource range to be modified by the
637 attributes specified by Attributes.
638
639 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource
640 range specified by BarIndex, Offset, and Length were
641 set on the PCI controller, and the actual resource range is returned
642 in Offset and Length.
643 @retval EFI_INVALID_PARAMETER Offset or Length is NULL.
644 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.
645 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the
646 resource range specified by BarIndex, Offset, and
647 Length.
648
649 **/
650 EFI_STATUS
651 EFIAPI
652 PciIoSetBarAttributes (
653 IN EFI_PCI_IO_PROTOCOL *This,
654 IN UINT64 Attributes,
655 IN UINT8 BarIndex,
656 IN OUT UINT64 *Offset,
657 IN OUT UINT64 *Length
658 )
659 ;
660
661 /**
662 Program parent bridge's attribute recurrently.
663
664 @param PciIoDevice Child Pci device instance
665 @param Operation The operation to perform on the attributes for this PCI controller.
666 @param Attributes The mask of attributes that are used for Set, Enable, and Disable
667 operations.
668
669 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.
670 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
671 @retval EFI_UNSUPPORTED one or more of the bits set in
672 Attributes are not supported by this PCI controller or one of
673 its parent bridges when Operation is Set, Enable or Disable.
674
675 **/
676 EFI_STATUS
677 UpStreamBridgesAttributes (
678 IN PCI_IO_DEVICE *PciIoDevice,
679 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,
680 IN UINT64 Attributes
681 )
682 ;
683
684 /**
685 Test whether two Pci device has same parent bridge.
686
687 @param PciDevice1 the frist pci device for testing
688 @param PciDevice2 the second pci device for testing
689
690 @return whether two Pci device has same parent bridge.
691 **/
692 BOOLEAN
693 PciDevicesOnTheSamePath (
694 IN PCI_IO_DEVICE *PciDevice1,
695 IN PCI_IO_DEVICE *PciDevice2
696 )
697 ;
698
699 #endif
EFI Development Kit II mirror for PVE