IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciIo.h

   1 /**@file
   2
   3 Copyright (c) 2006, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 **/
  13
  14
  15 #ifndef _EFI_PCI_IO_PROTOCOL_H
  16 #define _EFI_PCI_IO_PROTOCOL_H
  17
  18 /**
  19   Initializes a PCI I/O Instance
  20
  21   @param PciIoDevice  Pci device instance
  22
  23   @retval EFI_SUCCESS  Success operation
  24 **/
  25 EFI_STATUS
  26 InitializePciIoInstance (
  27   PCI_IO_DEVICE  *PciIoDevice
  28   );
  29
  30 /**
  31   Verifies access to a PCI Base Address Register (BAR)
  32
  33   @param PciIoDevice  Pci device instance
  34   @param BarIndex     The BAR index of the standard PCI Configuration header to use as the
  35                       base address for the memory or I/O operation to perform.
  36   @param Type         Operation type could be memory or I/O
  37   @param Width        Signifies the width of the memory or I/O operations.
  38   @param Count        The number of memory or I/O operations to perform.
  39   @param Offset       The offset within the PCI configuration space for the PCI controller.
  40
  41   @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.
  42   @retval EFI_SUCCESS           Success Operation.
  43 **/
  44 EFI_STATUS
  45 PciIoVerifyBarAccess (
  46   PCI_IO_DEVICE                   *PciIoDevice,
  47   UINT8                           BarIndex,
  48   PCI_BAR_TYPE                    Type,
  49   IN EFI_PCI_IO_PROTOCOL_WIDTH    Width,
  50   IN UINTN                        Count,
  51   UINT64                          *Offset
  52   );
  53
  54 /**
  55   Verifies access to a PCI Config Header
  56
  57   @param PciIoDevice  Pci device instance
  58   @param Width        Signifies the width of the memory or I/O operations.
  59   @param Count        The number of memory or I/O operations to perform.
  60   @param Offset       The offset within the PCI configuration space for the PCI controller.
  61
  62   @retval EFI_INVALID_PARAMETER  Invalid Width
  63   @retval EFI_UNSUPPORTED        Offset overflow
  64   @retval EFI_SUCCESS            Success operation
  65 **/
  66 EFI_STATUS
  67 PciIoVerifyConfigAccess (
  68   PCI_IO_DEVICE                 *PciIoDevice,
  69   IN EFI_PCI_IO_PROTOCOL_WIDTH  Width,
  70   IN UINTN                      Count,
  71   IN UINT64                     *Offset
  72   );
  73
  74 /**
  75   Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
  76   satisfied or after a defined duration.
  77
  78   @param This       Pointer to protocol instance of EFI_PCI_IO_PROTOCOL
  79   @param Width      Signifies the width of the memory or I/O operations.
  80   @param BarIndex   The BAR index of the standard PCI Configuration header to use as the
  81                     base address for the memory or I/O operation to perform.
  82   @param Offset     The offset within the PCI configuration space for the PCI controller.
  83   @param Mask       Mask used for the polling criteria.
  84   @param Value      The comparison value used for the polling exit criteria.
  85   @param Delay      The number of 100 ns units to poll.
  86   @param Result     Pointer to the last value read from the memory location.
  87
  88   @retval EFI_SUCCESS           The last data returned from the access matched the poll exit criteria.
  89   @retval EFI_TIMEOUT           Delay expired before a match occurred.
  90   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
  91   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
  92 **/
  93 EFI_STATUS
  94 EFIAPI
  95 PciIoPollMem (
  96   IN  EFI_PCI_IO_PROTOCOL        *This,
  97   IN  EFI_PCI_IO_PROTOCOL_WIDTH  Width,
  98   IN  UINT8                      BarIndex,
  99   IN  UINT64                     Offset,
 100   IN  UINT64                     Mask,
 101   IN  UINT64                     Value,
 102   IN  UINT64                     Delay,
 103   OUT UINT64                     *Result
 104   );
 105
 106 /**
 107   Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
 108   satisfied or after a defined duration.
 109
 110   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL.
 111   @param  Width                 Signifies the width of the memory or I/O operations.
 112   @param  Address               The base address of the memory or I/O operations.
 113   @param  Mask                  Mask used for the polling criteria.
 114   @param  Value                 The comparison value used for the polling exit criteria.
 115   @param  Delay                 The number of 100 ns units to poll.
 116   @param  Result                Pointer to the last value read from the memory location.
 117
 118   @retval EFI_SUCCESS           The last data returned from the access matched the poll exit criteria.
 119   @retval EFI_TIMEOUT           Delay expired before a match occurred.
 120   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 121   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 122
 123 **/
 124 EFI_STATUS
 125 EFIAPI
 126 PciIoPollIo (
 127   IN  EFI_PCI_IO_PROTOCOL        *This,
 128   IN  EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 129   IN  UINT8                      BarIndex,
 130   IN  UINT64                     Offset,
 131   IN  UINT64                     Mask,
 132   IN  UINT64                     Value,
 133   IN  UINT64                     Delay,
 134   OUT UINT64                     *Result
 135   );
 136
 137 /**
 138   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
 139
 140   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 141   @param  Width                 Signifies the width of the memory or I/O operations.
 142   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 143                                 base address for the memory or I/O operation to perform.
 144   @param  Offset                The offset within the selected BAR to start the memory or I/O operation.
 145   @param  Count                 The number of memory or I/O operations to perform.
 146   @param  Buffer                For read operations, the destination buffer to store the results. For write
 147                                 operations, the source buffer to write data from.
 148
 149   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 150   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 151   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 152                                 valid for the PCI BAR specified by BarIndex.
 153   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 154   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 155
 156 **/
 157 EFI_STATUS
 158 EFIAPI
 159 PciIoMemRead (
 160   IN     EFI_PCI_IO_PROTOCOL        *This,
 161   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 162   IN     UINT8                      BarIndex,
 163   IN     UINT64                     Offset,
 164   IN     UINTN                      Count,
 165   IN OUT VOID                       *Buffer
 166   );
 167
 168 /**
 169   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
 170
 171   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 172   @param  Width                 Signifies the width of the memory or I/O operations.
 173   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 174                                 base address for the memory or I/O operation to perform.
 175   @param  Offset                The offset within the selected BAR to start the memory or I/O operation.
 176   @param  Count                 The number of memory or I/O operations to perform.
 177   @param  Buffer                For read operations, the destination buffer to store the results. For write
 178                                 operations, the source buffer to write data from.
 179
 180   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 181   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 182   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 183                                 valid for the PCI BAR specified by BarIndex.
 184   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 185   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 186
 187 **/
 188 EFI_STATUS
 189 EFIAPI
 190 PciIoMemWrite (
 191   IN     EFI_PCI_IO_PROTOCOL        *This,
 192   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 193   IN     UINT8                      BarIndex,
 194   IN     UINT64                     Offset,
 195   IN     UINTN                      Count,
 196   IN OUT VOID                       *Buffer
 197   );
 198
 199 /**
 200   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
 201
 202   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 203   @param  Width                 Signifies the width of the memory or I/O operations.
 204   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 205                                 base address for the memory or I/O operation to perform.
 206   @param  Offset                The offset within the selected BAR to start the memory or I/O operation.
 207   @param  Count                 The number of memory or I/O operations to perform.
 208   @param  Buffer                For read operations, the destination buffer to store the results. For write
 209                                 operations, the source buffer to write data from.
 210
 211   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 212   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 213   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 214                                 valid for the PCI BAR specified by BarIndex.
 215   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 216   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 217
 218 **/
 219 EFI_STATUS
 220 EFIAPI
 221 PciIoIoRead (
 222   IN     EFI_PCI_IO_PROTOCOL        *This,
 223   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 224   IN     UINT8                      BarIndex,
 225   IN     UINT64                     Offset,
 226   IN     UINTN                      Count,
 227   IN OUT VOID                       *Buffer
 228   );
 229
 230 /**
 231   Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.
 232
 233   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 234   @param  Width                 Signifies the width of the memory or I/O operations.
 235   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 236                                 base address for the memory or I/O operation to perform.
 237   @param  Offset                The offset within the selected BAR to start the memory or I/O operation.
 238   @param  Count                 The number of memory or I/O operations to perform.
 239   @param  Buffer                For read operations, the destination buffer to store the results. For write
 240                                 operations, the source buffer to write data from.
 241
 242   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 243   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 244   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 245                                 valid for the PCI BAR specified by BarIndex.
 246   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 247   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 248
 249 **/
 250 EFI_STATUS
 251 EFIAPI
 252 PciIoIoWrite (
 253   IN     EFI_PCI_IO_PROTOCOL        *This,
 254   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 255   IN     UINT8                      BarIndex,
 256   IN     UINT64                     Offset,
 257   IN     UINTN                      Count,
 258   IN OUT VOID                       *Buffer
 259   );
 260
 261 /**
 262   Enable a PCI driver to access PCI controller registers in PCI configuration space.
 263
 264   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 265   @param  Width                 Signifies the width of the memory operations.
 266   @param  Offset                The offset within the PCI configuration space for the PCI controller.
 267   @param  Count                 The number of PCI configuration operations to perform.
 268   @param  Buffer                For read operations, the destination buffer to store the results. For write
 269                                 operations, the source buffer to write data from.
 270
 271
 272   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 273   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 274                                 valid for the PCI configuration header of the PCI controller.
 275   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 276   @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
 277
 278 **/
 279 EFI_STATUS
 280 EFIAPI
 281 PciIoConfigRead (
 282   IN     EFI_PCI_IO_PROTOCOL        *This,
 283   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 284   IN     UINT32                     Offset,
 285   IN     UINTN                      Count,
 286   IN OUT VOID                       *Buffer
 287   );
 288
 289 /**
 290   Enable a PCI driver to access PCI controller registers in PCI configuration space.
 291
 292   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 293   @param  Width                 Signifies the width of the memory operations.
 294   @param  Offset                The offset within the PCI configuration space for the PCI controller.
 295   @param  Count                 The number of PCI configuration operations to perform.
 296   @param  Buffer                For read operations, the destination buffer to store the results. For write
 297                                 operations, the source buffer to write data from.
 298
 299
 300   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 301   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 302                                 valid for the PCI configuration header of the PCI controller.
 303   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 304   @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
 305
 306 **/
 307 EFI_STATUS
 308 EFIAPI
 309 PciIoConfigWrite (
 310   IN     EFI_PCI_IO_PROTOCOL        *This,
 311   IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,
 312   IN     UINT32                     Offset,
 313   IN     UINTN                      Count,
 314   IN OUT VOID                       *Buffer
 315   );
 316
 317 /**
 318   Enables a PCI driver to copy one region of PCI memory space to another region of PCI
 319   memory space.
 320
 321   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 322   @param  Width                 Signifies the width of the memory operations.
 323   @param  DestBarIndex          The BAR index in the standard PCI Configuration header to use as the
 324                                 base address for the memory operation to perform.
 325   @param  DestOffset            The destination offset within the BAR specified by DestBarIndex to
 326                                 start the memory writes for the copy operation.
 327   @param  SrcBarIndex           The BAR index in the standard PCI Configuration header to use as the
 328                                 base address for the memory operation to perform.
 329   @param  SrcOffset             The source offset within the BAR specified by SrcBarIndex to start
 330                                 the memory reads for the copy operation.
 331   @param  Count                 The number of memory operations to perform. Bytes moved is Width
 332                                 size * Count, starting at DestOffset and SrcOffset.
 333
 334   @retval EFI_SUCCESS           The data was copied from one memory region to another memory region.
 335   @retval EFI_UNSUPPORTED       DestBarIndex not valid for this PCI controller.
 336   @retval EFI_UNSUPPORTED       SrcBarIndex not valid for this PCI controller.
 337   @retval EFI_UNSUPPORTED       The address range specified by DestOffset, Width, and Count
 338                                 is not valid for the PCI BAR specified by DestBarIndex.
 339   @retval EFI_UNSUPPORTED       The address range specified by SrcOffset, Width, and Count is
 340                                 not valid for the PCI BAR specified by SrcBarIndex.
 341   @retval EFI_INVALID_PARAMETER Width is invalid.
 342   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 343
 344 **/
 345 EFI_STATUS
 346 EFIAPI
 347 PciIoCopyMem (
 348   IN EFI_PCI_IO_PROTOCOL              *This,
 349   IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,
 350   IN     UINT8                        DestBarIndex,
 351   IN     UINT64                       DestOffset,
 352   IN     UINT8                        SrcBarIndex,
 353   IN     UINT64                       SrcOffset,
 354   IN     UINTN                        Count
 355   );
 356
 357 /**
 358   Provides the PCI controller-Cspecific addresses needed to access system memory.
 359
 360   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 361   @param  Operation             Indicates if the bus master is going to read or write to system memory.
 362   @param  HostAddress           The system memory address to map to the PCI controller.
 363   @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes
 364                                 that were mapped.
 365   @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to
 366                                 access the hosts HostAddress.
 367   @param  Mapping               A resulting value to pass to Unmap().
 368
 369   @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
 370   @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.
 371   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 372   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 373   @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
 374
 375 **/
 376 EFI_STATUS
 377 EFIAPI
 378 PciIoMap (
 379   IN     EFI_PCI_IO_PROTOCOL            *This,
 380   IN     EFI_PCI_IO_PROTOCOL_OPERATION  Operation,
 381   IN     VOID                           *HostAddress,
 382   IN OUT UINTN                          *NumberOfBytes,
 383   OUT    EFI_PHYSICAL_ADDRESS           *DeviceAddress,
 384   OUT    VOID                           **Mapping
 385   );
 386
 387 /**
 388   Completes the Map() operation and releases any corresponding resources.
 389
 390   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 391   @param  Mapping               The mapping value returned from Map().
 392
 393   @retval EFI_SUCCESS           The range was unmapped.
 394   @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.
 395
 396 **/
 397 EFI_STATUS
 398 EFIAPI
 399 PciIoUnmap (
 400   IN  EFI_PCI_IO_PROTOCOL  *This,
 401   IN  VOID                 *Mapping
 402   );
 403
 404 /**
 405   Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer
 406   mapping.
 407
 408   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 409   @param  Type                  This parameter is not used and must be ignored.
 410   @param  MemoryType            The type of memory to allocate, EfiBootServicesData or
 411                                 EfiRuntimeServicesData.
 412   @param  Pages                 The number of pages to allocate.
 413   @param  HostAddress           A pointer to store the base system memory address of the
 414                                 allocated range.
 415   @param  Attributes            The requested bit mask of attributes for the allocated range.
 416
 417   @retval EFI_SUCCESS           The requested memory pages were allocated.
 418   @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are
 419                                 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
 420   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 421   @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
 422
 423 **/
 424 EFI_STATUS
 425 EFIAPI
 426 PciIoAllocateBuffer (
 427   IN  EFI_PCI_IO_PROTOCOL   *This,
 428   IN  EFI_ALLOCATE_TYPE     Type,
 429   IN  EFI_MEMORY_TYPE       MemoryType,
 430   IN  UINTN                 Pages,
 431   OUT VOID                  **HostAddress,
 432   IN  UINT64                Attributes
 433   );
 434
 435 /**
 436   Frees memory that was allocated with AllocateBuffer().
 437
 438   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 439   @param  Pages                 The number of pages to free.
 440   @param  HostAddress           The base system memory address of the allocated range.
 441
 442   @retval EFI_SUCCESS           The requested memory pages were freed.
 443   @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
 444                                 was not allocated with AllocateBuffer().
 445
 446 **/
 447 EFI_STATUS
 448 EFIAPI
 449 PciIoFreeBuffer (
 450   IN  EFI_PCI_IO_PROTOCOL   *This,
 451   IN  UINTN                 Pages,
 452   IN  VOID                  *HostAddress
 453   );
 454
 455 /**
 456   Flushes all PCI posted write transactions from a PCI host bridge to system memory.
 457
 458   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 459
 460   @retval EFI_SUCCESS           The PCI posted write transactions were flushed from the PCI host
 461                                 bridge to system memory.
 462   @retval EFI_DEVICE_ERROR      The PCI posted write transactions were not flushed from the PCI
 463                                 host bridge due to a hardware error.
 464
 465 **/
 466 EFI_STATUS
 467 EFIAPI
 468 PciIoFlush (
 469   IN  EFI_PCI_IO_PROTOCOL  *This
 470   );
 471
 472 /**
 473   Retrieves this PCI controller's current PCI bus number, device number, and function number.
 474
 475   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 476   @param  SegmentNumber         The PCI controller's current PCI segment number.
 477   @param  BusNumber             The PCI controller's current PCI bus number.
 478   @param  DeviceNumber          The PCI controller's current PCI device number.
 479   @param  FunctionNumber        The PCI controller's current PCI function number.
 480
 481   @retval EFI_SUCCESS           The PCI controller location was returned.
 482   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 483
 484 **/
 485 EFI_STATUS
 486 EFIAPI
 487 PciIoGetLocation (
 488   IN  EFI_PCI_IO_PROTOCOL  *This,
 489   OUT UINTN                *Segment,
 490   OUT UINTN                *Bus,
 491   OUT UINTN                *Device,
 492   OUT UINTN                *Function
 493   );
 494
 495 /**
 496   Check BAR type for PCI resource.
 497
 498   @param PciIoDevice   PCI device instance
 499   @param BarIndex      The BAR index of the standard PCI Configuration header to use as the
 500                        base address for the memory or I/O operation to perform.
 501   @param BarType       Memory or I/O
 502
 503   @return whether Pci device's bar type is same with input BarType.
 504 **/
 505 BOOLEAN
 506 CheckBarType (
 507   IN PCI_IO_DEVICE       *PciIoDevice,
 508   UINT8                  BarIndex,
 509   PCI_BAR_TYPE           BarType
 510   );
 511
 512 /**
 513   Set/Disable new attributes to a Root Bridge
 514
 515   @param  PciIoDevice  Pci device instance
 516   @param  Attributes   New attribute want to be set
 517   @param  Operation    Set or Disable
 518
 519   @retval  EFI_UNSUPPORTED  If root bridge does not support change attribute
 520   @retval  EFI_SUCCESS      Success operation.
 521 **/
 522 EFI_STATUS
 523 ModifyRootBridgeAttributes (
 524   IN  PCI_IO_DEVICE                            *PciIoDevice,
 525   IN  UINT64                                   Attributes,
 526   IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation
 527   );
 528
 529 /**
 530   Check whether this device can be enable/disable to snoop
 531
 532   @param PciIoDevice  Pci device instance
 533   @param Operation    Enable/Disable
 534
 535   @retval EFI_UNSUPPORTED  Pci device is not GFX device or not support snoop
 536   @retval EFI_SUCCESS      Snoop can be supported.
 537 **/
 538 EFI_STATUS
 539 SupportPaletteSnoopAttributes (
 540   IN  PCI_IO_DEVICE                            *PciIoDevice,
 541   IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation
 542   );
 543
 544 /**
 545   Performs an operation on the attributes that this PCI controller supports. The operations include
 546   getting the set of supported attributes, retrieving the current attributes, setting the current
 547   attributes, enabling attributes, and disabling attributes.
 548
 549   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 550   @param  Operation             The operation to perform on the attributes for this PCI controller.
 551   @param  Attributes            The mask of attributes that are used for Set, Enable, and Disable
 552                                 operations.
 553   @param  Result                A pointer to the result mask of attributes that are returned for the Get
 554                                 and Supported operations.
 555
 556   @retval EFI_SUCCESS           The operation on the PCI controller's attributes was completed.
 557   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 558   @retval EFI_UNSUPPORTED       one or more of the bits set in
 559                                 Attributes are not supported by this PCI controller or one of
 560                                 its parent bridges when Operation is Set, Enable or Disable.
 561
 562 **/
 563 EFI_STATUS
 564 EFIAPI
 565 PciIoAttributes (
 566   IN EFI_PCI_IO_PROTOCOL                       * This,
 567   IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation,
 568   IN  UINT64                                   Attributes,
 569   OUT UINT64                                   *Result OPTIONAL
 570   );
 571
 572 /**
 573   Gets the attributes that this PCI controller supports setting on a BAR using
 574   SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.
 575
 576   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 577   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 578                                 base address for resource range. The legal range for this field is 0..5.
 579   @param  Supports              A pointer to the mask of attributes that this PCI controller supports
 580                                 setting for this BAR with SetBarAttributes().
 581   @param  Resources             A pointer to the ACPI 2.0 resource descriptors that describe the current
 582                                 configuration of this BAR of the PCI controller.
 583
 584   @retval EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI
 585                                 controller supports are returned in Supports. If Resources
 586                                 is not NULL, then the ACPI 2.0 resource descriptors that the PCI
 587                                 controller is currently using are returned in Resources.
 588   @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
 589   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 590   @retval EFI_OUT_OF_RESOURCES  There are not enough resources available to allocate
 591                                 Resources.
 592
 593 **/
 594 EFI_STATUS
 595 EFIAPI
 596 PciIoGetBarAttributes (
 597   IN EFI_PCI_IO_PROTOCOL             * This,
 598   IN  UINT8                          BarIndex,
 599   OUT UINT64                         *Supports, OPTIONAL
 600   OUT VOID                           **Resources OPTIONAL
 601   );
 602
 603 /**
 604   Sets the attributes for a range of a BAR on a PCI controller.
 605
 606   @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.
 607   @param  Attributes            The mask of attributes to set for the resource range specified by
 608                                 BarIndex, Offset, and Length.
 609   @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the
 610                                 base address for resource range. The legal range for this field is 0..5.
 611   @param  Offset                A pointer to the BAR relative base address of the resource range to be
 612                                 modified by the attributes specified by Attributes.
 613   @param  Length                A pointer to the length of the resource range to be modified by the
 614                                 attributes specified by Attributes.
 615
 616   @retval EFI_SUCCESS           The set of attributes specified by Attributes for the resource
 617                                 range specified by BarIndex, Offset, and Length were
 618                                 set on the PCI controller, and the actual resource range is returned
 619                                 in Offset and Length.
 620   @retval EFI_INVALID_PARAMETER Offset or Length is NULL.
 621   @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.
 622   @retval EFI_OUT_OF_RESOURCES  There are not enough resources to set the attributes on the
 623                                 resource range specified by BarIndex, Offset, and
 624                                 Length.
 625
 626 **/
 627 EFI_STATUS
 628 EFIAPI
 629 PciIoSetBarAttributes (
 630   IN EFI_PCI_IO_PROTOCOL              *This,
 631   IN     UINT64                       Attributes,
 632   IN     UINT8                        BarIndex,
 633   IN OUT UINT64                       *Offset,
 634   IN OUT UINT64                       *Length
 635   );
 636
 637 /**
 638   Program parent bridge's attribute recurrently.
 639
 640   @param PciIoDevice  Child Pci device instance
 641   @param Operation    The operation to perform on the attributes for this PCI controller.
 642   @param Attributes   The mask of attributes that are used for Set, Enable, and Disable
 643                       operations.
 644
 645   @retval EFI_SUCCESS           The operation on the PCI controller's attributes was completed.
 646   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 647   @retval EFI_UNSUPPORTED       one or more of the bits set in
 648                                 Attributes are not supported by this PCI controller or one of
 649                                 its parent bridges when Operation is Set, Enable or Disable.
 650
 651 **/
 652 EFI_STATUS
 653 UpStreamBridgesAttributes (
 654   IN  PCI_IO_DEVICE                            *PciIoDevice,
 655   IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation,
 656   IN  UINT64                                   Attributes
 657   );
 658
 659 /**
 660   Test whether two Pci device has same parent bridge.
 661
 662   @param PciDevice1  the frist pci device for testing
 663   @param PciDevice2  the second pci device for testing
 664
 665   @return whether two Pci device has same parent bridge.
 666 **/
 667 BOOLEAN
 668 PciDevicesOnTheSamePath (
 669   IN PCI_IO_DEVICE        *PciDevice1,
 670   IN PCI_IO_DEVICE        *PciDevice2
 671   );
 672
 673 #endif