IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciLib.h

   1 /** @file
   2   Internal library declaration for PCI Bus module.
   3
   4 Copyright (c) 2006 - 2009, Intel Corporation
   5 All rights reserved. This program and the accompanying materials
   6 are licensed and made available under the terms and conditions of the BSD License
   7 which accompanies this distribution.  The full text of the license may be found at
   8 http://opensource.org/licenses/bsd-license.php
   9
  10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #ifndef _EFI_PCI_LIB_H_
  16 #define _EFI_PCI_LIB_H_
  17
  18 //
  19 // Mask definistions for PCD PcdPciIncompatibleDeviceSupportMask
  20 //
  21 #define PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT         0x01
  22 #define PCI_INCOMPATIBLE_READ_SUPPORT                  0x02
  23 #define PCI_INCOMPATIBLE_WRITE_SUPPORT                 0x04
  24 #define PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT       0x08
  25 #define PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT          0x0a
  26
  27 typedef struct {
  28   EFI_HANDLE            Handle;
  29 } EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD;
  30
  31 typedef struct {
  32   UINT32                             Bar;
  33   UINT16                             DevicePathSize;
  34   UINT16                             ReqResSize;
  35   UINT16                             AllocResSize;
  36   UINT8                              *DevicePath;
  37   UINT8                              *ReqRes;
  38   UINT8                              *AllocRes;
  39 } EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD;
  40
  41
  42 /**
  43   Retrieve the PCI Card device BAR information via PciIo interface.
  44
  45   @param PciIoDevice        PCI Card device instance.
  46
  47 **/
  48 VOID
  49 GetBackPcCardBar (
  50   IN  PCI_IO_DEVICE                  *PciIoDevice
  51   );
  52
  53 /**
  54   Remove rejected pci device from specific root bridge
  55   handle.
  56
  57   @param RootBridgeHandle  Specific parent root bridge handle.
  58   @param Bridge            Bridge device instance.
  59
  60 **/
  61 VOID
  62 RemoveRejectedPciDevices (
  63   IN EFI_HANDLE        RootBridgeHandle,
  64   IN PCI_IO_DEVICE     *Bridge
  65   );
  66
  67 /**
  68   Submits the I/O and memory resource requirements for the specified PCI Host Bridge.
  69
  70   @param PciResAlloc  Point to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
  71
  72   @retval EFI_SUCCESS           Successfully finished resource allocation.
  73   @retval EFI_NOT_FOUND         Cannot get root bridge instance.
  74   @retval EFI_OUT_OF_RESOURCES  Platform failed to program the resources if no hot plug supported.
  75   @retval other                 Some error occurred when allocating resources for the PCI Host Bridge.
  76
  77   @note   Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.
  78
  79 **/
  80 EFI_STATUS
  81 PciHostBridgeResourceAllocator (
  82   IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
  83   );
  84
  85 /**
  86   Scan pci bus and assign bus number to the given PCI bus system.
  87
  88   @param  Bridge           Bridge device instance.
  89   @param  StartBusNumber   start point.
  90   @param  SubBusNumber     Point to sub bus number.
  91   @param  PaddedBusRange   Customized bus number.
  92
  93   @retval EFI_SUCCESS      Successfully scanned and assigned bus number.
  94   @retval other            Some error occurred when scanning pci bus.
  95
  96   @note   Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.
  97
  98 **/
  99 EFI_STATUS
 100 PciScanBus (
 101   IN PCI_IO_DEVICE                      *Bridge,
 102   IN UINT8                              StartBusNumber,
 103   OUT UINT8                             *SubBusNumber,
 104   OUT UINT8                             *PaddedBusRange
 105   );
 106
 107 /**
 108   Process Option Rom on the specified root bridge.
 109
 110   @param Bridge  Pci root bridge device instance.
 111
 112   @retval EFI_SUCCESS   Success process.
 113   @retval other         Some error occurred when processing Option Rom on the root bridge.
 114
 115 **/
 116 EFI_STATUS
 117 PciRootBridgeP2CProcess (
 118   IN PCI_IO_DEVICE *Bridge
 119   );
 120
 121 /**
 122   Process Option Rom on the specified host bridge.
 123
 124   @param PciResAlloc    Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.
 125
 126   @retval EFI_SUCCESS   Success process.
 127   @retval EFI_NOT_FOUND Can not find the root bridge instance.
 128   @retval other         Some error occurred when processing Option Rom on the host bridge.
 129
 130 **/
 131 EFI_STATUS
 132 PciHostBridgeP2CProcess (
 133   IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc
 134   );
 135
 136 /**
 137   This function is used to enumerate the entire host bridge
 138   in a given platform.
 139
 140   @param PciResAlloc   A pointer to the PCI Host Resource Allocation protocol.
 141
 142   @retval EFI_SUCCESS            Successfully enumerated the host bridge.
 143   @retval EFI_OUT_OF_RESOURCES   No enough memory available.
 144   @retval other                  Some error occurred when enumerating the host bridge.
 145
 146 **/
 147 EFI_STATUS
 148 PciHostBridgeEnumerator (
 149   EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL  *PciResAlloc
 150   );
 151
 152 /**
 153   Read PCI configuration space through EFI_PCI_IO_PROTOCOL.
 154
 155   @param  PciIo               A pointer to the EFI_PCI_O_PROTOCOL.
 156   @param  Width               Signifies the width of the memory operations.
 157   @param  Address             The address within the PCI configuration space for the PCI controller.
 158   @param  Count               The number of unit to be read.
 159   @param  Buffer              For read operations, the destination buffer to store the results. For
 160                               write operations, the source buffer to write data from.
 161
 162   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 163   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 164                                 valid for the PCI configuration header of the PCI controller.
 165   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 166   @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
 167
 168 **/
 169 EFI_STATUS
 170 PciIoRead (
 171   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,
 172   IN       EFI_PCI_IO_PROTOCOL_WIDTH              Width,
 173   IN       UINT32                                 Address,
 174   IN       UINTN                                  Count,
 175   IN OUT   VOID                                   *Buffer
 176   );
 177
 178 /**
 179   Write PCI configuration space through EFI_PCI_IO_PROTOCOL.
 180
 181   If PCI incompatibility check is enabled, do incompatibility check.
 182
 183   @param  PciIo                 A pointer to the EFI_PCI_IO_PROTOCOL instance.
 184   @param  Width                 Signifies the width of the memory operations.
 185   @param  Offset                The offset within the PCI configuration space for the PCI controller.
 186   @param  Count                 The number of PCI configuration operations to perform.
 187   @param  Buffer                For read operations, the destination buffer to store the results. For write
 188                                 operations, the source buffer to write data from.
 189
 190   @retval EFI_SUCCESS           The data was read from or written to the PCI controller.
 191   @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not
 192                                 valid for the PCI configuration header of the PCI controller.
 193   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 194   @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.
 195
 196 **/
 197 EFI_STATUS
 198 PciIoWrite (
 199   IN       EFI_PCI_IO_PROTOCOL                    *PciIo,
 200   IN       EFI_PCI_IO_PROTOCOL_WIDTH              Width,
 201   IN       UINT32                                 Address,
 202   IN       UINTN                                  Count,
 203   IN OUT   VOID                                   *Buffer
 204   );
 205
 206 /**
 207   Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 208
 209   @param  PciRootBridgeIo     A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 210   @param  Pci                 A pointer to PCI_TYPE00.
 211   @param  Width               Signifies the width of the memory operations.
 212   @param  Address             The address within the PCI configuration space for the PCI controller.
 213   @param  Count               The number of unit to be read.
 214   @param  Buffer              For read operations, the destination buffer to store the results. For
 215                               write operations, the source buffer to write data from.
 216
 217   @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.
 218   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 219   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 220
 221 **/
 222 EFI_STATUS
 223 PciRootBridgeIoWrite (
 224   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *PciRootBridgeIo,
 225   IN       PCI_TYPE00                             *Pci,
 226   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 227   IN       UINT64                                 Address,
 228   IN       UINTN                                  Count,
 229   IN OUT   VOID                                   *Buffer
 230   );
 231
 232 /**
 233   Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 234
 235   @param  PciRootBridgeIo     A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
 236   @param  Pci                 A pointer to PCI_TYPE00.
 237   @param  Width               Signifies the width of the memory operations.
 238   @param  Address             The address within the PCI configuration space for the PCI controller.
 239   @param  Count               The number of unit to be read.
 240   @param  Buffer              For read operations, the destination buffer to store the results. For
 241                               write operations, the source buffer to write data from.
 242
 243   @retval EFI_SUCCESS           The data was read from or written to the PCI root bridge.
 244   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 245   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 246
 247 **/
 248 EFI_STATUS
 249 PciRootBridgeIoRead (
 250   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *PciRootBridgeIo,
 251   IN       PCI_TYPE00                             *Pci,            OPTIONAL
 252   IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,
 253   IN       UINT64                                 Address,
 254   IN       UINTN                                  Count,
 255   IN OUT   VOID                                   *Buffer
 256   );
 257 #endif