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1 /**@file
2
3 Copyright (c) 2006 - 2007, Intel Corporation
4 All rights reserved. This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 **/
13
14 #include "pcibus.h"
15 #include "PciResourceSupport.h"
16
17 #include <IndustryStandard/Pci23.h>
18
19 //
20 // Module global for a template of the PCI option ROM Image Device Path Node
21 //
22 MEMMAP_DEVICE_PATH mPciOptionRomImageDevicePathNodeTemplate = {
23 {
24 HARDWARE_DEVICE_PATH,
25 HW_MEMMAP_DP,
26 sizeof (MEMMAP_DEVICE_PATH)
27 },
28 EfiMemoryMappedIO,
29 0,
30 0
31 };
32
33 EFI_STATUS
34 GetOpRomInfo (
35 IN PCI_IO_DEVICE *PciIoDevice
36 )
37 /**
38
39 Routine Description:
40
41 Arguments:
42
43 Returns:
44
45 **/
46 // TODO: PciIoDevice - add argument and description to function comment
47 // TODO: EFI_NOT_FOUND - add return value to function comment
48 // TODO: EFI_SUCCESS - add return value to function comment
49 {
50 UINT8 RomBarIndex;
51 UINT32 AllOnes;
52 UINT64 Address;
53 EFI_STATUS Status;
54 UINT8 Bus;
55 UINT8 Device;
56 UINT8 Function;
57 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;
58
59 Bus = PciIoDevice->BusNumber;
60 Device = PciIoDevice->DeviceNumber;
61 Function = PciIoDevice->FunctionNumber;
62
63 PciRootBridgeIo = PciIoDevice->PciRootBridgeIo;
64
65 //
66 // offset is 0x30 if is not ppb
67 //
68
69 //
70 // 0x30
71 //
72 RomBarIndex = PCI_DEVICE_ROMBAR;
73
74 if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) {
75 //
76 // if is ppb
77 //
78
79 //
80 // 0x38
81 //
82 RomBarIndex = PCI_BRIDGE_ROMBAR;
83 }
84 //
85 // the bit0 is 0 to prevent the enabling of the Rom address decoder
86 //
87 AllOnes = 0xfffffffe;
88 Address = EFI_PCI_ADDRESS (Bus, Device, Function, RomBarIndex);
89
90 Status = PciRootBridgeIoWrite (
91 PciRootBridgeIo,
92 &PciIoDevice->Pci,
93 EfiPciWidthUint32,
94 Address,
95 1,
96 &AllOnes
97 );
98 if (EFI_ERROR (Status)) {
99 return Status;
100 }
101
102 //
103 // read back
104 //
105 Status = PciRootBridgeIoRead (
106 PciRootBridgeIo,
107 &PciIoDevice->Pci,
108 EfiPciWidthUint32,
109 Address,
110 1,
111 &AllOnes
112 );
113 if (EFI_ERROR (Status)) {
114 return Status;
115 }
116 //
117 // Bits [1, 10] are reserved
118 //
119 AllOnes &= 0xFFFFF800;
120 if ((AllOnes == 0) || (AllOnes == 0xFFFFF800)) {
121 return EFI_NOT_FOUND;
122 }
123
124 PciIoDevice->RomSize = (UINT64) ((~AllOnes) + 1);
125 return EFI_SUCCESS;
126 }
127
128 EFI_STATUS
129 LoadOpRomImage (
130 IN PCI_IO_DEVICE *PciDevice,
131 IN UINT64 RomBase
132 )
133 /**
134
135 Routine Description:
136
137 Load option rom image for specified PCI device
138
139 Arguments:
140
141 Returns:
142
143 **/
144 // TODO: PciDevice - add argument and description to function comment
145 // TODO: RomBase - add argument and description to function comment
146 // TODO: EFI_OUT_OF_RESOURCES - add return value to function comment
147 // TODO: EFI_OUT_OF_RESOURCES - add return value to function comment
148 // TODO: EFI_OUT_OF_RESOURCES - add return value to function comment
149 {
150 UINT8 RomBarIndex;
151 UINT8 Indicator;
152 UINT16 OffsetPcir;
153 UINT32 RomBarOffset;
154 UINT32 RomBar;
155 EFI_STATUS retStatus;
156 BOOLEAN FirstCheck;
157 UINT8 *Image;
158 PCI_EXPANSION_ROM_HEADER *RomHeader;
159 PCI_DATA_STRUCTURE *RomPcir;
160 UINT64 RomSize;
161 UINT64 RomImageSize;
162 UINT8 *RomInMemory;
163 UINT8 CodeType;
164
165 RomSize = PciDevice->RomSize;
166
167 Indicator = 0;
168 RomImageSize = 0;
169 RomInMemory = NULL;
170 CodeType = 0xFF;
171
172 //
173 // Get the RomBarIndex
174 //
175
176 //
177 // 0x30
178 //
179 RomBarIndex = PCI_DEVICE_ROMBAR;
180 if (IS_PCI_BRIDGE (&(PciDevice->Pci))) {
181 //
182 // if is ppb
183 //
184
185 //
186 // 0x38
187 //
188 RomBarIndex = PCI_BRIDGE_ROMBAR;
189 }
190 //
191 // Allocate memory for Rom header and PCIR
192 //
193 RomHeader = AllocatePool (sizeof (PCI_EXPANSION_ROM_HEADER));
194 if (RomHeader == NULL) {
195 return EFI_OUT_OF_RESOURCES;
196 }
197
198 RomPcir = AllocatePool (sizeof (PCI_DATA_STRUCTURE));
199 if (RomPcir == NULL) {
200 gBS->FreePool (RomHeader);
201 return EFI_OUT_OF_RESOURCES;
202 }
203
204 RomBar = (UINT32) RomBase;
205
206 //
207 // Enable RomBar
208 //
209 RomDecode (PciDevice, RomBarIndex, RomBar, TRUE);
210
211 RomBarOffset = RomBar;
212 retStatus = EFI_NOT_FOUND;
213 FirstCheck = TRUE;
214
215 do {
216 PciDevice->PciRootBridgeIo->Mem.Read (
217 PciDevice->PciRootBridgeIo,
218 EfiPciWidthUint8,
219 RomBarOffset,
220 sizeof (PCI_EXPANSION_ROM_HEADER),
221 (UINT8 *) RomHeader
222 );
223
224 if (RomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
225 RomBarOffset = RomBarOffset + 512;
226 if (FirstCheck) {
227 break;
228 } else {
229 RomImageSize = RomImageSize + 512;
230 continue;
231 }
232 }
233
234 FirstCheck = FALSE;
235 OffsetPcir = RomHeader->PcirOffset;
236 PciDevice->PciRootBridgeIo->Mem.Read (
237 PciDevice->PciRootBridgeIo,
238 EfiPciWidthUint8,
239 RomBarOffset + OffsetPcir,
240 sizeof (PCI_DATA_STRUCTURE),
241 (UINT8 *) RomPcir
242 );
243 if (RomPcir->CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {
244 CodeType = PCI_CODE_TYPE_PCAT_IMAGE;
245 }
246 Indicator = RomPcir->Indicator;
247 RomImageSize = RomImageSize + RomPcir->ImageLength * 512;
248 RomBarOffset = RomBarOffset + RomPcir->ImageLength * 512;
249 } while (((Indicator & 0x80) == 0x00) && ((RomBarOffset - RomBar) < RomSize));
250
251 //
252 // Some Legacy Cards do not report the correct ImageLength so used the maximum
253 // of the legacy length and the PCIR Image Length
254 //
255 if (CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {
256 RomImageSize = MAX(RomImageSize, (((EFI_LEGACY_EXPANSION_ROM_HEADER *)RomHeader)->Size512 * 512));
257 }
258
259 if (RomImageSize > 0) {
260 retStatus = EFI_SUCCESS;
261 Image = AllocatePool ((UINT32) RomImageSize);
262 if (Image == NULL) {
263 RomDecode (PciDevice, RomBarIndex, RomBar, FALSE);
264 gBS->FreePool (RomHeader);
265 gBS->FreePool (RomPcir);
266 return EFI_OUT_OF_RESOURCES;
267 }
268
269 //
270 // Copy Rom image into memory
271 //
272 PciDevice->PciRootBridgeIo->Mem.Read (
273 PciDevice->PciRootBridgeIo,
274 EfiPciWidthUint8,
275 RomBar,
276 (UINT32) RomImageSize,
277 Image
278 );
279 RomInMemory = Image;
280 }
281
282 RomDecode (PciDevice, RomBarIndex, RomBar, FALSE);
283
284 PciDevice->PciIo.RomSize = RomImageSize;
285 PciDevice->PciIo.RomImage = RomInMemory;
286
287 //
288 // For OpROM read from PCI device:
289 // Add the Rom Image to internal database for later PCI light enumeration
290 //
291 PciRomAddImageMapping (
292 NULL,
293 PciDevice->PciRootBridgeIo->SegmentNumber,
294 PciDevice->BusNumber,
295 PciDevice->DeviceNumber,
296 PciDevice->FunctionNumber,
297 (UINT64) (UINTN) PciDevice->PciIo.RomImage,
298 PciDevice->PciIo.RomSize
299 );
300
301 //
302 // Free allocated memory
303 //
304 gBS->FreePool (RomHeader);
305 gBS->FreePool (RomPcir);
306
307 return retStatus;
308 }
309
310 EFI_STATUS
311 RomDecode (
312 IN PCI_IO_DEVICE *PciDevice,
313 IN UINT8 RomBarIndex,
314 IN UINT32 RomBar,
315 IN BOOLEAN Enable
316 )
317 /**
318
319 Routine Description:
320
321 Arguments:
322
323 Returns:
324
325 **/
326 // TODO: PciDevice - add argument and description to function comment
327 // TODO: RomBarIndex - add argument and description to function comment
328 // TODO: RomBar - add argument and description to function comment
329 // TODO: Enable - add argument and description to function comment
330 // TODO: EFI_SUCCESS - add return value to function comment
331 {
332 UINT32 Value32;
333 UINT32 Offset;
334 EFI_PCI_IO_PROTOCOL *PciIo;
335
336 PciIo = &PciDevice->PciIo;
337 if (Enable) {
338 //
339 // Clear all bars
340 //
341 for (Offset = 0x10; Offset <= 0x24; Offset += sizeof (UINT32)) {
342 PciIoWrite (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllZero);
343 }
344
345 //
346 // set the Rom base address: now is hardcode
347 // enable its decoder
348 //
349 Value32 = RomBar | 0x1;
350 PciIoWrite (
351 PciIo,
352 (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
353 RomBarIndex,
354 1,
355 &Value32
356 );
357
358 //
359 // Programe all upstream bridge
360 //
361 ProgrameUpstreamBridgeForRom(PciDevice, RomBar, TRUE);
362
363 //
364 // Setting the memory space bit in the function's command register
365 //
366 PciEnableCommandRegister(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
367
368 } else {
369
370 //
371 // disable command register decode to memory
372 //
373 PciDisableCommandRegister(PciDevice, EFI_PCI_COMMAND_MEMORY_SPACE);
374
375 //
376 // Destroy the programmed bar in all the upstream bridge.
377 //
378 ProgrameUpstreamBridgeForRom(PciDevice, RomBar, FALSE);
379
380 //
381 // disable rom decode
382 //
383 Value32 = 0xFFFFFFFE;
384 PciIoWrite (
385 PciIo,
386 (EFI_PCI_IO_PROTOCOL_WIDTH) EfiPciWidthUint32,
387 RomBarIndex,
388 1,
389 &Value32
390 );
391
392 }
393
394 return EFI_SUCCESS;
395
396 }
397
398 EFI_STATUS
399 ProcessOpRomImage (
400 PCI_IO_DEVICE *PciDevice
401 )
402 /**
403
404 Routine Description:
405
406 Process the oprom image.
407
408 Arguments:
409 PciDevice A pointer to a pci device.
410
411 Returns:
412
413 EFI Status.
414
415 **/
416 {
417 UINT8 Indicator;
418 UINT32 ImageSize;
419 UINT16 ImageOffset;
420 VOID *RomBar;
421 UINT8 *RomBarOffset;
422 EFI_HANDLE ImageHandle;
423 EFI_STATUS Status;
424 EFI_STATUS retStatus;
425 BOOLEAN FirstCheck;
426 BOOLEAN SkipImage;
427 UINT32 DestinationSize;
428 UINT32 ScratchSize;
429 UINT8 *Scratch;
430 VOID *ImageBuffer;
431 VOID *DecompressedImageBuffer;
432 UINT32 ImageLength;
433 EFI_DECOMPRESS_PROTOCOL *Decompress;
434 EFI_PCI_EXPANSION_ROM_HEADER *EfiRomHeader;
435 PCI_DATA_STRUCTURE *Pcir;
436 EFI_DEVICE_PATH_PROTOCOL *PciOptionRomImageDevicePath;
437
438 Indicator = 0;
439
440 //
441 // Get the Address of the Rom image
442 //
443 RomBar = PciDevice->PciIo.RomImage;
444 RomBarOffset = (UINT8 *) RomBar;
445 retStatus = EFI_NOT_FOUND;
446 FirstCheck = TRUE;
447
448 do {
449 EfiRomHeader = (EFI_PCI_EXPANSION_ROM_HEADER *) RomBarOffset;
450 if (EfiRomHeader->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
451 RomBarOffset = RomBarOffset + 512;
452 if (FirstCheck) {
453 break;
454 } else {
455 continue;
456 }
457 }
458
459 FirstCheck = FALSE;
460 Pcir = (PCI_DATA_STRUCTURE *) (RomBarOffset + EfiRomHeader->PcirOffset);
461 ImageSize = (UINT32) (Pcir->ImageLength * 512);
462 Indicator = Pcir->Indicator;
463
464 if ((Pcir->CodeType == PCI_CODE_TYPE_EFI_IMAGE) &&
465 (EfiRomHeader->EfiSignature == EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE)) {
466
467 if ((EfiRomHeader->EfiSubsystem == EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER) ||
468 (EfiRomHeader->EfiSubsystem == EFI_IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER)) {
469
470 ImageOffset = EfiRomHeader->EfiImageHeaderOffset;
471 ImageSize = (UINT32) (EfiRomHeader->InitializationSize * 512);
472
473 ImageBuffer = (VOID *) (RomBarOffset + ImageOffset);
474 ImageLength = ImageSize - (UINT32)ImageOffset;
475 DecompressedImageBuffer = NULL;
476
477 //
478 // decompress here if needed
479 //
480 SkipImage = FALSE;
481 if (EfiRomHeader->CompressionType > EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED) {
482 SkipImage = TRUE;
483 }
484
485 if (EfiRomHeader->CompressionType == EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED) {
486 Status = gBS->LocateProtocol (&gEfiDecompressProtocolGuid, NULL, (VOID **) &Decompress);
487 if (EFI_ERROR (Status)) {
488 SkipImage = TRUE;
489 } else {
490 SkipImage = TRUE;
491 Status = Decompress->GetInfo (
492 Decompress,
493 ImageBuffer,
494 ImageLength,
495 &DestinationSize,
496 &ScratchSize
497 );
498 if (!EFI_ERROR (Status)) {
499 DecompressedImageBuffer = NULL;
500 DecompressedImageBuffer = AllocatePool (DestinationSize);
501 if (DecompressedImageBuffer != NULL) {
502 Scratch = AllocatePool (ScratchSize);
503 if (Scratch != NULL) {
504 Status = Decompress->Decompress (
505 Decompress,
506 ImageBuffer,
507 ImageLength,
508 DecompressedImageBuffer,
509 DestinationSize,
510 Scratch,
511 ScratchSize
512 );
513 if (!EFI_ERROR (Status)) {
514 ImageBuffer = DecompressedImageBuffer;
515 ImageLength = DestinationSize;
516 SkipImage = FALSE;
517 }
518
519 gBS->FreePool (Scratch);
520 }
521 }
522 }
523 }
524 }
525
526 if (!SkipImage) {
527 //
528 // Build Memory Mapped device path node to record the image offset into the PCI Option ROM
529 //
530 mPciOptionRomImageDevicePathNodeTemplate.StartingAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) (RomBarOffset - (UINT8 *) RomBar);
531 mPciOptionRomImageDevicePathNodeTemplate.EndingAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) (RomBarOffset + ImageSize - 1 - (UINT8 *) RomBar);
532 PciOptionRomImageDevicePath = AppendDevicePathNode (PciDevice->DevicePath, (const EFI_DEVICE_PATH_PROTOCOL *)&mPciOptionRomImageDevicePathNodeTemplate);
533 ASSERT (PciOptionRomImageDevicePath != NULL);
534
535 //
536 // load image and start image
537 //
538 Status = gBS->LoadImage (
539 FALSE,
540 gPciBusDriverBinding.DriverBindingHandle,
541 PciOptionRomImageDevicePath,
542 ImageBuffer,
543 ImageLength,
544 &ImageHandle
545 );
546
547 //
548 // Free the device path after it has been used by LoadImage
549 //
550 gBS->FreePool (PciOptionRomImageDevicePath);
551
552 if (!EFI_ERROR (Status)) {
553 Status = gBS->StartImage (ImageHandle, NULL, NULL);
554 if (!EFI_ERROR (Status)) {
555 AddDriver (PciDevice, ImageHandle);
556 PciRomAddImageMapping (
557 ImageHandle,
558 PciDevice->PciRootBridgeIo->SegmentNumber,
559 PciDevice->BusNumber,
560 PciDevice->DeviceNumber,
561 PciDevice->FunctionNumber,
562 (UINT64) (UINTN) PciDevice->PciIo.RomImage,
563 PciDevice->PciIo.RomSize
564 );
565 retStatus = EFI_SUCCESS;
566 }
567 }
568 }
569
570 RomBarOffset = RomBarOffset + ImageSize;
571 } else {
572 RomBarOffset = RomBarOffset + ImageSize;
573 }
574 } else {
575 RomBarOffset = RomBarOffset + ImageSize;
576 }
577
578 } while (((Indicator & 0x80) == 0x00) && ((UINTN) (RomBarOffset - (UINT8 *) RomBar) < PciDevice->RomSize));
579
580 return retStatus;
581
582 }