IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/pcibus.h

   1 /*++
   2
   3 Copyright (c) 2006 - 2007, Intel Corporation
   4 All rights reserved. This program and the accompanying materials
   5 are licensed and made available under the terms and conditions of the BSD License
   6 which accompanies this distribution.  The full text of the license may be found at
   7 http://opensource.org/licenses/bsd-license.php
   8
   9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11
  12 Module Name:
  13
  14   pcibus.h
  15
  16 Abstract:
  17
  18   PCI Bus Driver
  19
  20 Revision History
  21
  22 --*/
  23
  24 #ifndef _EFI_PCI_BUS_H
  25 #define _EFI_PCI_BUS_H
  26
  27
  28 #include <FrameworkDxe.h>
  29
  30
  31 #include <Protocol/LoadedImage.h>
  32 #include <Protocol/PciHostBridgeResourceAllocation.h>
  33 #include <Protocol/PciIo.h>
  34 #include <Guid/PciHotplugDevice.h>
  35 #include <Protocol/PciRootBridgeIo.h>
  36 #include <Protocol/PciHotPlugRequest.h>
  37 #include <Protocol/DevicePath.h>
  38 #include <Protocol/PciPlatform.h>
  39 #include <Protocol/PciHotPlugInit.h>
  40 #include <Protocol/Decompress.h>
  41 #include <Guid/PciOptionRomTable.h>
  42 #include <Protocol/BusSpecificDriverOverride.h>
  43 #include <Protocol/UgaIo.h>
  44
  45 #include <Library/DebugLib.h>
  46 #include <Library/UefiDriverEntryPoint.h>
  47 #include <Library/BaseLib.h>
  48 #include <Library/UefiLib.h>
  49 #include <Library/BaseMemoryLib.h>
  50 #include <Library/ReportStatusCodeLib.h>
  51 #include <Library/MemoryAllocationLib.h>
  52 #include <Library/UefiBootServicesTableLib.h>
  53 #include <Library/DevicePathLib.h>
  54 #include <Library/PcdLib.h>
  55 #include <Library/PciIncompatibleDeviceSupportLib.h>
  56
  57 #include <IndustryStandard/Pci23.h>
  58 #include <IndustryStandard/PeImage.h>
  59 #include <IndustryStandard/Acpi.h>
  60 #include "ComponentName.h"
  61
  62 //
  63 // Driver Produced Protocol Prototypes
  64 //
  65
  66 #define VGABASE1  0x3B0
  67 #define VGALIMIT1 0x3BB
  68
  69 #define VGABASE2  0x3C0
  70 #define VGALIMIT2 0x3DF
  71
  72 #define ISABASE   0x100
  73 #define ISALIMIT  0x3FF
  74
  75 typedef enum {
  76   PciBarTypeUnknown = 0,
  77   PciBarTypeIo16,
  78   PciBarTypeIo32,
  79   PciBarTypeMem32,
  80   PciBarTypePMem32,
  81   PciBarTypeMem64,
  82   PciBarTypePMem64,
  83   PciBarTypeIo,
  84   PciBarTypeMem,
  85   PciBarTypeMaxType
  86 } PCI_BAR_TYPE;
  87
  88 typedef struct {
  89   UINT64        BaseAddress;
  90   UINT64        Length;
  91   UINT64        Alignment;
  92   PCI_BAR_TYPE  BarType;
  93   BOOLEAN       Prefetchable;
  94   UINT8         MemType;
  95   UINT8         Offset;
  96 } PCI_BAR;
  97
  98 #define PPB_BAR_0                             0
  99 #define PPB_BAR_1                             1
 100 #define PPB_IO_RANGE                          2
 101 #define PPB_MEM32_RANGE                       3
 102 #define PPB_PMEM32_RANGE                      4
 103 #define PPB_PMEM64_RANGE                      5
 104 #define PPB_MEM64_RANGE                       0xFF
 105
 106 #define P2C_BAR_0                             0
 107 #define P2C_MEM_1                             1
 108 #define P2C_MEM_2                             2
 109 #define P2C_IO_1                              3
 110 #define P2C_IO_2                              4
 111
 112 #define PCI_IO_DEVICE_SIGNATURE               EFI_SIGNATURE_32 ('p', 'c', 'i', 'o')
 113
 114 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
 115 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
 116 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
 117 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
 118 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
 119 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
 120 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
 121
 122 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
 123 //
 124 // Define resource status constant
 125 //
 126 #define EFI_RESOURCE_NONEXISTENT  0xFFFFFFFFFFFFFFFFULL
 127 #define EFI_RESOURCE_LESS         0xFFFFFFFFFFFFFFFEULL
 128 #define EFI_RESOURCE_SATISFIED    0x0000000000000000ULL
 129
 130 //
 131 // Define option for attribute
 132 //
 133 #define EFI_SET_SUPPORTS    0
 134 #define EFI_SET_ATTRIBUTES  1
 135
 136 typedef struct _PCI_IO_DEVICE {
 137   UINT32                                    Signature;
 138   EFI_HANDLE                                Handle;
 139   EFI_PCI_IO_PROTOCOL                       PciIo;
 140   LIST_ENTRY                                Link;
 141
 142   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
 143   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
 144   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
 145
 146   //
 147   // PCI configuration space header type
 148   //
 149   PCI_TYPE00                                Pci;
 150
 151   //
 152   // Bus number, Device number, Function number
 153   //
 154   UINT8                                     BusNumber;
 155   UINT8                                     DeviceNumber;
 156   UINT8                                     FunctionNumber;
 157
 158   //
 159   // BAR for this PCI Device
 160   //
 161   PCI_BAR                                   PciBar[PCI_MAX_BAR];
 162
 163   //
 164   // The bridge device this pci device is subject to
 165   //
 166   struct _PCI_IO_DEVICE                     *Parent;
 167
 168   //
 169   // A linked list for children Pci Device if it is bridge device
 170   //
 171   LIST_ENTRY                                ChildList;
 172
 173   //
 174   // TURE if the PCI bus driver creates the handle for this PCI device
 175   //
 176   BOOLEAN                                   Registered;
 177
 178   //
 179   // TRUE if the PCI bus driver successfully allocates the resource required by
 180   // this PCI device
 181   //
 182   BOOLEAN                                   Allocated;
 183
 184   //
 185   // The attribute this PCI device currently set
 186   //
 187   UINT64                                    Attributes;
 188
 189   //
 190   // The attributes this PCI device actually supports
 191   //
 192   UINT64                                    Supports;
 193
 194   //
 195   // The resource decode the bridge supports
 196   //
 197   UINT32                                    Decodes;
 198
 199   //
 200   // The OptionRom Size
 201   //
 202   UINT64                                    RomSize;
 203
 204   //
 205   // The OptionRom Size
 206   //
 207   UINT64                                    RomBase;
 208
 209   //
 210   // TRUE if all OpROM (in device or in platform specific position) have been processed
 211   //
 212   BOOLEAN                                   AllOpRomProcessed;
 213
 214   //
 215   // TRUE if there is any EFI driver in the OptionRom
 216   //
 217   BOOLEAN                                   BusOverride;
 218
 219   //
 220   //  A list tracking reserved resource on a bridge device
 221   //
 222   LIST_ENTRY                                ReservedResourceList;
 223
 224   //
 225   // A list tracking image handle of platform specific overriding driver
 226   //
 227   LIST_ENTRY                                OptionRomDriverList;
 228
 229   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
 230   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
 231
 232   BOOLEAN                                   IsPciExp;
 233
 234 } PCI_IO_DEVICE;
 235
 236
 237 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
 238   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
 239
 240 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
 241   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
 242
 243 #define PCI_IO_DEVICE_FROM_LINK(a) \
 244   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
 245
 246 //
 247 // Global Variables
 248 //
 249 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
 250 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
 251 extern LIST_ENTRY                                   gPciDevicePool;
 252 extern BOOLEAN                                      gFullEnumeration;
 253 extern UINTN                                        gPciHostBridgeNumber;
 254 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
 255 extern UINT64                                       gAllOne;
 256 extern UINT64                                       gAllZero;
 257
 258 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
 259
 260 #include "PciIo.h"
 261 #include "PciCommand.h"
 262 #include "PciDeviceSupport.h"
 263 #include "PciEnumerator.h"
 264 #include "PciEnumeratorSupport.h"
 265 #include "PciDriverOverride.h"
 266 #include "PciRomTable.h"
 267 #include "PciOptionRomSupport.h"
 268 #include "PciPowerManagement.h"
 269 #include "PciHotPlugSupport.h"
 270 #include "PciLib.h"
 271
 272 //
 273 // PCI Bus Support Function Prototypes
 274 //
 275 EFI_STATUS
 276 EFIAPI
 277 PciBusDriverBindingSupported (
 278   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 279   IN EFI_HANDLE                     Controller,
 280   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 281   );
 282
 283 EFI_STATUS
 284 EFIAPI
 285 PciBusDriverBindingStart (
 286   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
 287   IN EFI_HANDLE                     Controller,
 288   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
 289   );
 290
 291 EFI_STATUS
 292 EFIAPI
 293 PciBusDriverBindingStop (
 294   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
 295   IN  EFI_HANDLE                    Controller,
 296   IN  UINTN                         NumberOfChildren,
 297   IN  EFI_HANDLE                    *ChildHandleBuffer
 298   );
 299
 300 #endif