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[mirror_edk2.git] / IntelFrameworkModulePkg / Csm / LegacyBiosDxe / LegacyPci.c
1 /** @file
2
3 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
4
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions
7 of the BSD License which accompanies this distribution. The
8 full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
10
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13
14 **/
15
16 #include "LegacyBiosInterface.h"
17 #include <IndustryStandard/Pci30.h>
18
19 #define PCI_START_ADDRESS(x) (((x) + 0x7ff) & ~0x7ff)
20
21 #define MAX_BRIDGE_INDEX 0x20
22 typedef struct {
23 UINTN PciSegment;
24 UINTN PciBus;
25 UINTN PciDevice;
26 UINTN PciFunction;
27 UINT8 PrimaryBus;
28 UINT8 SecondaryBus;
29 UINT8 SubordinateBus;
30 } BRIDGE_TABLE;
31
32 #define ROM_MAX_ENTRIES 24
33 BRIDGE_TABLE Bridges[MAX_BRIDGE_INDEX];
34 UINTN SortedBridgeIndex[MAX_BRIDGE_INDEX];
35 UINTN NumberOfBridges;
36 LEGACY_PNP_EXPANSION_HEADER *mBasePnpPtr;
37 UINT16 mBbsRomSegment;
38 UINTN mHandleCount;
39 EFI_HANDLE mVgaHandle;
40 BOOLEAN mIgnoreBbsUpdateFlag;
41 BOOLEAN mVgaInstallationInProgress = FALSE;
42 UINT32 mRomCount = 0x00;
43 ROM_INSTANCE_ENTRY mRomEntry[ROM_MAX_ENTRIES];
44
45
46 /**
47 Query shadowed legacy ROM parameters registered by RomShadow() previously.
48
49 @param PciHandle PCI device whos ROM has been shadowed
50 @param DiskStart DiskStart value from EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom
51 @param DiskEnd DiskEnd value from EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom
52 @param RomShadowAddress Address where ROM was shadowed
53 @param ShadowedSize Runtime size of ROM
54
55 @retval EFI_SUCCESS Query Logging successful.
56 @retval EFI_NOT_FOUND No logged data found about PciHandle.
57
58 **/
59 EFI_STATUS
60 GetShadowedRomParameters (
61 IN EFI_HANDLE PciHandle,
62 OUT UINT8 *DiskStart, OPTIONAL
63 OUT UINT8 *DiskEnd, OPTIONAL
64 OUT VOID **RomShadowAddress, OPTIONAL
65 OUT UINTN *ShadowedSize OPTIONAL
66 )
67 {
68 EFI_STATUS Status;
69 EFI_PCI_IO_PROTOCOL *PciIo;
70 UINTN Index;
71 UINTN PciSegment;
72 UINTN PciBus;
73 UINTN PciDevice;
74 UINTN PciFunction;
75
76 //
77 // Get the PCI I/O Protocol on PciHandle
78 //
79 Status = gBS->HandleProtocol (
80 PciHandle,
81 &gEfiPciIoProtocolGuid,
82 (VOID **) &PciIo
83 );
84 if (EFI_ERROR (Status)) {
85 return Status;
86 }
87
88 //
89 // Get the location of the PCI device
90 //
91 PciIo->GetLocation (
92 PciIo,
93 &PciSegment,
94 &PciBus,
95 &PciDevice,
96 &PciFunction
97 );
98
99 for(Index = 0; Index < mRomCount; Index++) {
100 if ((mRomEntry[Index].PciSegment == PciSegment) &&
101 (mRomEntry[Index].PciBus == PciBus) &&
102 (mRomEntry[Index].PciDevice == PciDevice) &&
103 (mRomEntry[Index].PciFunction == PciFunction)) {
104 break;
105 }
106 }
107
108 if (Index == mRomCount) {
109 return EFI_NOT_FOUND;
110 }
111
112 if (DiskStart != NULL) {
113 *DiskStart = mRomEntry[Index].DiskStart;
114 }
115
116 if (DiskEnd != NULL) {
117 *DiskEnd = mRomEntry[Index].DiskEnd;
118 }
119
120 if (RomShadowAddress != NULL) {
121 *RomShadowAddress = (VOID *)(UINTN)mRomEntry[Index].ShadowAddress;
122 }
123
124 if (ShadowedSize != NULL) {
125 *ShadowedSize = mRomEntry[Index].ShadowedSize;
126 }
127
128 return EFI_SUCCESS;
129 }
130
131 /**
132 Every legacy ROM that is shadowed by the Legacy BIOS driver will be
133 registered into this API so that the policy code can know what has
134 happend
135
136 @param PciHandle PCI device whos ROM is being shadowed
137 @param ShadowAddress Address that ROM was shadowed
138 @param ShadowedSize Runtime size of ROM
139 @param DiskStart DiskStart value from
140 EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom
141 @param DiskEnd DiskEnd value from
142 EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom
143
144 @retval EFI_SUCCESS Logging successful.
145 @retval EFI_OUT_OF_RESOURCES No remaining room for registering another option
146 ROM.
147
148 **/
149 EFI_STATUS
150 RomShadow (
151 IN EFI_HANDLE PciHandle,
152 IN UINT32 ShadowAddress,
153 IN UINT32 ShadowedSize,
154 IN UINT8 DiskStart,
155 IN UINT8 DiskEnd
156 )
157 {
158 EFI_STATUS Status;
159 EFI_PCI_IO_PROTOCOL *PciIo;
160
161 //
162 // See if there is room to register another option ROM
163 //
164 if (mRomCount >= ROM_MAX_ENTRIES) {
165 return EFI_OUT_OF_RESOURCES;
166 }
167 //
168 // Get the PCI I/O Protocol on PciHandle
169 //
170 Status = gBS->HandleProtocol (
171 PciHandle,
172 &gEfiPciIoProtocolGuid,
173 (VOID **) &PciIo
174 );
175 if (EFI_ERROR (Status)) {
176 return Status;
177 }
178 //
179 // Get the location of the PCI device
180 //
181 PciIo->GetLocation (
182 PciIo,
183 &mRomEntry[mRomCount].PciSegment,
184 &mRomEntry[mRomCount].PciBus,
185 &mRomEntry[mRomCount].PciDevice,
186 &mRomEntry[mRomCount].PciFunction
187 );
188 mRomEntry[mRomCount].ShadowAddress = ShadowAddress;
189 mRomEntry[mRomCount].ShadowedSize = ShadowedSize;
190 mRomEntry[mRomCount].DiskStart = DiskStart;
191 mRomEntry[mRomCount].DiskEnd = DiskEnd;
192
193 mRomCount++;
194
195 return EFI_SUCCESS;
196 }
197
198
199 /**
200 Return EFI_SUCCESS if PciHandle has had a legacy BIOS ROM shadowed. This
201 information represents every call to RomShadow ()
202
203 @param PciHandle PCI device to get status for
204
205 @retval EFI_SUCCESS Legacy ROM loaded for this device
206 @retval EFI_NOT_FOUND No Legacy ROM loaded for this device
207
208 **/
209 EFI_STATUS
210 IsLegacyRom (
211 IN EFI_HANDLE PciHandle
212 )
213 {
214 EFI_STATUS Status;
215 EFI_PCI_IO_PROTOCOL *PciIo;
216 UINTN Index;
217 UINTN Segment;
218 UINTN Bus;
219 UINTN Device;
220 UINTN Function;
221
222 //
223 // Get the PCI I/O Protocol on PciHandle
224 //
225 Status = gBS->HandleProtocol (
226 PciHandle,
227 &gEfiPciIoProtocolGuid,
228 (VOID **) &PciIo
229 );
230 if (EFI_ERROR (Status)) {
231 return Status;
232 }
233 //
234 // Get the location of the PCI device
235 //
236 PciIo->GetLocation (
237 PciIo,
238 &Segment,
239 &Bus,
240 &Device,
241 &Function
242 );
243
244 //
245 // See if the option ROM from PciHandle has been previously posted
246 //
247 for (Index = 0; Index < mRomCount; Index++) {
248 if (mRomEntry[Index].PciSegment == Segment &&
249 mRomEntry[Index].PciBus == Bus &&
250 mRomEntry[Index].PciDevice == Device &&
251 mRomEntry[Index].PciFunction == Function
252 ) {
253 return EFI_SUCCESS;
254 }
255 }
256
257 return EFI_NOT_FOUND;
258 }
259
260 /**
261 Find the PC-AT ROM Image in the raw PCI Option ROM. Also return the
262 related information from the header.
263
264 @param Csm16Revision The PCI interface version of underlying CSM16
265 @param VendorId Vendor ID of the PCI device
266 @param DeviceId Device ID of the PCI device
267 @param Rom On input pointing to beginning of the raw PCI OpROM
268 On output pointing to the first legacy PCI OpROM
269 @param ImageSize On input is the size of Raw PCI Rom
270 On output is the size of the first legacy PCI ROM
271 @param MaxRuntimeImageLength The max runtime image length only valid if OpRomRevision >= 3
272 @param OpRomRevision Revision of the PCI Rom
273 @param ConfigUtilityCodeHeader Pointer to Configuration Utility Code Header
274
275 @retval EFI_SUCCESS Successfully find the legacy PCI ROM
276 @retval EFI_NOT_FOUND Failed to find the legacy PCI ROM
277
278 **/
279 EFI_STATUS
280 GetPciLegacyRom (
281 IN UINT16 Csm16Revision,
282 IN UINT16 VendorId,
283 IN UINT16 DeviceId,
284 IN OUT VOID **Rom,
285 IN OUT UINTN *ImageSize,
286 OUT UINTN *MaxRuntimeImageLength, OPTIONAL
287 OUT UINT8 *OpRomRevision, OPTIONAL
288 OUT VOID **ConfigUtilityCodeHeader OPTIONAL
289 )
290 {
291 BOOLEAN Match;
292 UINT16 *DeviceIdList;
293 EFI_PCI_ROM_HEADER RomHeader;
294 PCI_3_0_DATA_STRUCTURE *Pcir;
295 VOID *BackupImage;
296 VOID *BestImage;
297
298
299 if (*ImageSize < sizeof (EFI_PCI_ROM_HEADER)) {
300 return EFI_NOT_FOUND;
301 }
302
303 BestImage = NULL;
304 BackupImage = NULL;
305 RomHeader.Raw = *Rom;
306 while (RomHeader.Generic->Signature == PCI_EXPANSION_ROM_HEADER_SIGNATURE) {
307 if (RomHeader.Generic->PcirOffset == 0 ||
308 (RomHeader.Generic->PcirOffset & 3) !=0 ||
309 *ImageSize < RomHeader.Raw - (UINT8 *) *Rom + RomHeader.Generic->PcirOffset + sizeof (PCI_DATA_STRUCTURE)) {
310 break;
311 }
312
313 Pcir = (PCI_3_0_DATA_STRUCTURE *) (RomHeader.Raw + RomHeader.Generic->PcirOffset);
314 //
315 // Check signature in the PCI Data Structure.
316 //
317 if (Pcir->Signature != PCI_DATA_STRUCTURE_SIGNATURE) {
318 break;
319 }
320
321 if ((UINTN)(RomHeader.Raw - (UINT8 *) *Rom) + Pcir->ImageLength * 512 > *ImageSize) {
322 break;
323 }
324
325 if (Pcir->CodeType == PCI_CODE_TYPE_PCAT_IMAGE) {
326 Match = FALSE;
327 if (Pcir->VendorId == VendorId) {
328 if (Pcir->DeviceId == DeviceId) {
329 Match = TRUE;
330 } else if ((Pcir->Revision >= 3) && (Pcir->DeviceListOffset != 0)) {
331 DeviceIdList = (UINT16 *)(((UINT8 *) Pcir) + Pcir->DeviceListOffset);
332 //
333 // Checking the device list
334 //
335 while (*DeviceIdList != 0) {
336 if (*DeviceIdList == DeviceId) {
337 Match = TRUE;
338 break;
339 }
340 DeviceIdList ++;
341 }
342 }
343 }
344
345 if (Match) {
346 if (Csm16Revision >= 0x0300) {
347 //
348 // Case 1: CSM16 3.0
349 //
350 if (Pcir->Revision >= 3) {
351 //
352 // case 1.1: meets OpRom 3.0
353 // Perfect!!!
354 //
355 BestImage = RomHeader.Raw;
356 break;
357 } else {
358 //
359 // case 1.2: meets OpRom 2.x
360 // Store it and try to find the OpRom 3.0
361 //
362 BackupImage = RomHeader.Raw;
363 }
364 } else {
365 //
366 // Case 2: CSM16 2.x
367 //
368 if (Pcir->Revision >= 3) {
369 //
370 // case 2.1: meets OpRom 3.0
371 // Store it and try to find the OpRom 2.x
372 //
373 BackupImage = RomHeader.Raw;
374 } else {
375 //
376 // case 2.2: meets OpRom 2.x
377 // Perfect!!!
378 //
379 BestImage = RomHeader.Raw;
380 break;
381 }
382 }
383 } else {
384 DEBUG ((EFI_D_ERROR, "GetPciLegacyRom - OpRom not match (%04x-%04x)\n", (UINTN)VendorId, (UINTN)DeviceId));
385 }
386 }
387
388 if ((Pcir->Indicator & 0x80) == 0x80) {
389 break;
390 } else {
391 RomHeader.Raw += 512 * Pcir->ImageLength;
392 }
393 }
394
395 if (BestImage == NULL) {
396 if (BackupImage == NULL) {
397 return EFI_NOT_FOUND;
398 }
399 //
400 // The versions of CSM16 and OpRom don't match exactly
401 //
402 BestImage = BackupImage;
403 }
404 RomHeader.Raw = BestImage;
405 Pcir = (PCI_3_0_DATA_STRUCTURE *) (RomHeader.Raw + RomHeader.Generic->PcirOffset);
406 *Rom = BestImage;
407 *ImageSize = Pcir->ImageLength * 512;
408
409 if (MaxRuntimeImageLength != NULL) {
410 if (Pcir->Revision < 3) {
411 *MaxRuntimeImageLength = 0;
412 } else {
413 *MaxRuntimeImageLength = Pcir->MaxRuntimeImageLength * 512;
414 }
415 }
416
417 if (OpRomRevision != NULL) {
418 //
419 // Optional return PCI Data Structure revision
420 //
421 if (Pcir->Length >= 0x1C) {
422 *OpRomRevision = Pcir->Revision;
423 } else {
424 *OpRomRevision = 0;
425 }
426 }
427
428 if (ConfigUtilityCodeHeader != NULL) {
429 //
430 // Optional return ConfigUtilityCodeHeaderOffset supported by the PC-AT ROM
431 //
432 if ((Pcir->Revision < 3) || (Pcir->ConfigUtilityCodeHeaderOffset == 0)) {
433 *ConfigUtilityCodeHeader = NULL;
434 } else {
435 *ConfigUtilityCodeHeader = RomHeader.Raw + Pcir->ConfigUtilityCodeHeaderOffset;
436 }
437 }
438
439 return EFI_SUCCESS;
440 }
441
442 /**
443 Build a table of bridge info for PIRQ translation.
444
445 @param RoutingTable RoutingTable obtained from Platform.
446 @param RoutingTableEntries Number of RoutingTable entries.
447
448 @retval EFI_SUCCESS New Subordinate bus.
449 @retval EFI_NOT_FOUND No more Subordinate busses.
450
451 **/
452 EFI_STATUS
453 CreateBridgeTable (
454 IN EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable,
455 IN UINTN RoutingTableEntries
456 )
457 {
458 EFI_STATUS Status;
459 UINTN HandleCount;
460 EFI_HANDLE *HandleBuffer;
461 UINTN BridgeIndex;
462 UINTN Index;
463 UINTN Index1;
464 EFI_PCI_IO_PROTOCOL *PciIo;
465 PCI_TYPE01 PciConfigHeader;
466 BRIDGE_TABLE SlotBridges[MAX_BRIDGE_INDEX];
467 UINTN SlotBridgeIndex;
468
469 BridgeIndex = 0x00;
470 SlotBridgeIndex = 0x00;
471
472 //
473 // Assumption is table is built from low bus to high bus numbers.
474 //
475 Status = gBS->LocateHandleBuffer (
476 ByProtocol,
477 &gEfiPciIoProtocolGuid,
478 NULL,
479 &HandleCount,
480 &HandleBuffer
481 );
482 if (EFI_ERROR (Status)) {
483 return EFI_NOT_FOUND;
484 }
485 for (Index = 0; Index < HandleCount; Index++) {
486 Status = gBS->HandleProtocol (
487 HandleBuffer[Index],
488 &gEfiPciIoProtocolGuid,
489 (VOID **) &PciIo
490 );
491 if (EFI_ERROR (Status)) {
492 continue;
493 }
494
495 PciIo->Pci.Read (
496 PciIo,
497 EfiPciIoWidthUint32,
498 0,
499 sizeof (PciConfigHeader) / sizeof (UINT32),
500 &PciConfigHeader
501 );
502
503 if (IS_PCI_P2P (&PciConfigHeader) && (BridgeIndex < MAX_BRIDGE_INDEX)) {
504 PciIo->GetLocation (
505 PciIo,
506 &Bridges[BridgeIndex].PciSegment,
507 &Bridges[BridgeIndex].PciBus,
508 &Bridges[BridgeIndex].PciDevice,
509 &Bridges[BridgeIndex].PciFunction
510 );
511
512 Bridges[BridgeIndex].PrimaryBus = PciConfigHeader.Bridge.PrimaryBus;
513
514 Bridges[BridgeIndex].SecondaryBus = PciConfigHeader.Bridge.SecondaryBus;
515
516 Bridges[BridgeIndex].SubordinateBus = PciConfigHeader.Bridge.SubordinateBus;
517
518 for (Index1 = 0; Index1 < RoutingTableEntries; Index1++){
519 //
520 // Test whether we have found the Bridge in the slot, must be the one that directly interfaced to the board
521 // Once we find one, store it in the SlotBridges[]
522 //
523 if ((RoutingTable[Index1].Slot != 0) && (Bridges[BridgeIndex].PrimaryBus == RoutingTable[Index1].Bus)
524 && ((Bridges[BridgeIndex].PciDevice << 3) == RoutingTable[Index1].Device)) {
525 CopyMem (&SlotBridges[SlotBridgeIndex], &Bridges[BridgeIndex], sizeof (BRIDGE_TABLE));
526 SlotBridgeIndex++;
527
528 break;
529 }
530 }
531
532 ++BridgeIndex;
533 }
534 }
535
536 //
537 // Pack up Bridges by removing those useless ones
538 //
539 for (Index = 0; Index < BridgeIndex;){
540 for (Index1 = 0; Index1 < SlotBridgeIndex; Index1++) {
541 if (((Bridges[Index].PciBus == SlotBridges[Index1].PrimaryBus) && (Bridges[Index].PciDevice == SlotBridges[Index1].PciDevice)) ||
542 ((Bridges[Index].PciBus >= SlotBridges[Index1].SecondaryBus) && (Bridges[Index].PciBus <= SlotBridges[Index1].SubordinateBus))) {
543 //
544 // We have found one that meets our criteria
545 //
546 Index++;
547 break;
548 }
549 }
550
551 //
552 // This one doesn't meet criteria, pack it
553 //
554 if (Index1 >= SlotBridgeIndex) {
555 for (Index1 = Index; BridgeIndex > 1 && Index1 < BridgeIndex - 1 ; Index1++) {
556 CopyMem (&Bridges[Index1], &Bridges[Index1 + 1], sizeof (BRIDGE_TABLE));
557 }
558
559 BridgeIndex--;
560 }
561 }
562
563 NumberOfBridges = BridgeIndex;
564
565 //
566 // Sort bridges low to high by Secondary bus followed by subordinate bus
567 //
568 if (NumberOfBridges > 1) {
569 Index = 0;
570 do {
571 SortedBridgeIndex[Index] = Index;
572 ++Index;
573 } while (Index < NumberOfBridges);
574
575 for (Index = 0; Index < NumberOfBridges - 1; Index++) {
576 for (Index1 = Index + 1; Index1 < NumberOfBridges; Index1++) {
577 if (Bridges[Index].SecondaryBus > Bridges[Index1].SecondaryBus) {
578 SortedBridgeIndex[Index] = Index1;
579 SortedBridgeIndex[Index1] = Index;
580 }
581
582 if ((Bridges[Index].SecondaryBus == Bridges[Index1].SecondaryBus) &&
583 (Bridges[Index].SubordinateBus > Bridges[Index1].SubordinateBus)
584 ) {
585 SortedBridgeIndex[Index] = Index1;
586 SortedBridgeIndex[Index1] = Index;
587 }
588 }
589 }
590 }
591 FreePool (HandleBuffer);
592 return EFI_SUCCESS;
593 }
594
595
596 /**
597 Find base Bridge for device.
598
599 @param Private Legacy BIOS Instance data
600 @param PciBus Input = Bus of device.
601 @param PciDevice Input = Device.
602 @param RoutingTable The platform specific routing table
603 @param RoutingTableEntries Number of entries in table
604
605 @retval EFI_SUCCESS At base bus.
606 @retval EFI_NOT_FOUND Behind a bridge.
607
608 **/
609 EFI_STATUS
610 GetBaseBus (
611 IN LEGACY_BIOS_INSTANCE *Private,
612 IN UINTN PciBus,
613 IN UINTN PciDevice,
614 IN EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable,
615 IN UINTN RoutingTableEntries
616 )
617 {
618 UINTN Index;
619 for (Index = 0; Index < RoutingTableEntries; Index++) {
620 if ((RoutingTable[Index].Bus == PciBus) && (RoutingTable[Index].Device == (PciDevice << 3))) {
621 return EFI_SUCCESS;
622 }
623 }
624
625 return EFI_NOT_FOUND;
626 }
627
628 /**
629 Translate PIRQ through busses
630
631 @param Private Legacy BIOS Instance data
632 @param PciBus Input = Bus of device. Output = Translated Bus
633 @param PciDevice Input = Device. Output = Translated Device
634 @param PciFunction Input = Function. Output = Translated Function
635 @param PirqIndex Input = Original PIRQ index. If single function
636 device then 0, otherwise 0-3.
637 Output = Translated Index
638
639 @retval EFI_SUCCESS Pirq successfully translated.
640 @retval EFI_NOT_FOUND The device is not behind any known bridge.
641
642 **/
643 EFI_STATUS
644 TranslateBusPirq (
645 IN LEGACY_BIOS_INSTANCE *Private,
646 IN OUT UINTN *PciBus,
647 IN OUT UINTN *PciDevice,
648 IN OUT UINTN *PciFunction,
649 IN OUT UINT8 *PirqIndex
650 )
651 {
652 /*
653 This routine traverses the PCI busses from base slot
654 and translates the PIRQ register to the appropriate one.
655
656 Example:
657
658 Bus 0, Device 1 is PCI-PCI bridge that all PCI slots reside on.
659 Primary bus# = 0
660 Secondary bus # = 1
661 Subordinate bus # is highest bus # behind this bus
662 Bus 1, Device 0 is Slot 0 and is not a bridge.
663 Bus 1, Device 1 is Slot 1 and is a bridge.
664 Slot PIRQ routing is A,B,C,D.
665 Primary bus # = 1
666 Secondary bus # = 2
667 Subordinate bus # = 5
668 Bus 2, Device 6 is a bridge. It has no bridges behind it.
669 Primary bus # = 2
670 Secondary bus # = 3
671 Subordinate bus # = 3
672 Bridge PIRQ routing is C,D,A,B
673 Bus 2, Device 7 is a bridge. It has 1 bridge behind it.
674 Primary bus # = 2
675 Secondary bus = 4 Device 6 takes bus 2.
676 Subordinate bus = 5.
677 Bridge PIRQ routing is D,A,B,C
678 Bus 4, Device 2 is a bridge. It has no bridges behind it.
679 Primary bus # = 4
680 Secondary bus # = 5
681 Subordinate bus = 5
682 Bridge PIRQ routing is B,C,D,A
683 Bus 5, Device 1 is to be programmed.
684 Device PIRQ routing is C,D,A,B
685
686
687 Search busses starting from slot bus for final bus >= Secondary bus and
688 final bus <= Suborninate bus. Assumption is bus entries increase in bus
689 number.
690 Starting PIRQ is A,B,C,D.
691 Bus 2, Device 7 satisfies search criteria. Rotate (A,B,C,D) left by device
692 7 modulo 4 giving (D,A,B,C).
693 Bus 4, Device 2 satisfies search criteria. Rotate (D,A,B,C) left by 2 giving
694 (B,C,D,A).
695 No other busses match criteria. Device to be programmed is Bus 5, Device 1.
696 Rotate (B,C,D,A) by 1 giving C,D,A,B. Translated PIRQ is C.
697
698 */
699 UINTN LocalBus;
700 UINTN LocalDevice;
701 UINTN BaseBus;
702 UINTN BaseDevice;
703 UINTN BaseFunction;
704 UINT8 LocalPirqIndex;
705 BOOLEAN BaseIndexFlag;
706 UINTN BridgeIndex;
707 UINTN SBridgeIndex;
708 BaseIndexFlag = FALSE;
709 BridgeIndex = 0x00;
710
711 LocalPirqIndex = *PirqIndex;
712 LocalBus = *PciBus;
713 LocalDevice = *PciDevice;
714 BaseBus = *PciBus;
715 BaseDevice = *PciDevice;
716 BaseFunction = *PciFunction;
717
718 //
719 // LocalPirqIndex list PIRQs in rotated fashion
720 // = 0 A,B,C,D
721 // = 1 B,C,D,A
722 // = 2 C,D,A,B
723 // = 3 D,A,B,C
724 //
725
726 for (BridgeIndex = 0; BridgeIndex < NumberOfBridges; BridgeIndex++) {
727 SBridgeIndex = SortedBridgeIndex[BridgeIndex];
728 //
729 // Check if device behind this bridge
730 //
731 if ((LocalBus >= Bridges[SBridgeIndex].SecondaryBus) && (LocalBus <= Bridges[SBridgeIndex].SubordinateBus)) {
732 //
733 // If BaseIndexFlag = FALSE then have found base bridge, i.e
734 // bridge in slot. Save info for use by IRQ routing table.
735 //
736 if (!BaseIndexFlag) {
737 BaseBus = Bridges[SBridgeIndex].PciBus;
738 BaseDevice = Bridges[SBridgeIndex].PciDevice;
739 BaseFunction = Bridges[SBridgeIndex].PciFunction;
740 BaseIndexFlag = TRUE;
741 } else {
742 LocalPirqIndex = (UINT8) ((LocalPirqIndex + (UINT8)Bridges[SBridgeIndex].PciDevice)%4);
743 }
744
745 //
746 // Check if at device. If not get new PCI location & PIRQ
747 //
748 if (Bridges[SBridgeIndex].SecondaryBus == (UINT8) LocalBus) {
749 //
750 // Translate PIRQ
751 //
752 LocalPirqIndex = (UINT8) ((LocalPirqIndex + (UINT8) (LocalDevice)) % 4);
753 break;
754 }
755 }
756 }
757
758 //
759 // In case we fail to find the Bridge just above us, this is some potential error and we want to warn the user
760 //
761 if(BridgeIndex >= NumberOfBridges){
762 DEBUG ((EFI_D_ERROR, "Cannot Find IRQ Routing for Bus %d, Device %d, Function %d\n", *PciBus, *PciDevice, *PciFunction));
763 }
764
765 *PirqIndex = LocalPirqIndex;
766 *PciBus = BaseBus;
767 *PciDevice = BaseDevice;
768 *PciFunction = BaseFunction;
769
770 return EFI_SUCCESS;
771 }
772
773
774 /**
775 Copy the $PIR table as required.
776
777 @param Private Legacy BIOS Instance data
778 @param RoutingTable Pointer to IRQ routing table
779 @param RoutingTableEntries IRQ routing table entries
780 @param PirqTable Pointer to $PIR table
781 @param PirqTableSize Length of table
782
783 **/
784 VOID
785 CopyPirqTable (
786 IN LEGACY_BIOS_INSTANCE *Private,
787 IN EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable,
788 IN UINTN RoutingTableEntries,
789 IN EFI_LEGACY_PIRQ_TABLE_HEADER *PirqTable,
790 IN UINTN PirqTableSize
791 )
792 {
793 EFI_IA32_REGISTER_SET Regs;
794 UINT32 Granularity;
795
796 //
797 // Copy $PIR table, if it exists.
798 //
799 if (PirqTable != NULL) {
800 Private->LegacyRegion->UnLock (
801 Private->LegacyRegion,
802 0xE0000,
803 0x20000,
804 &Granularity
805 );
806
807 Private->InternalIrqRoutingTable = RoutingTable;
808 Private->NumberIrqRoutingEntries = (UINT16) (RoutingTableEntries);
809 ZeroMem (&Regs, sizeof (EFI_IA32_REGISTER_SET));
810
811 Regs.X.AX = Legacy16GetTableAddress;
812 Regs.X.CX = (UINT16) PirqTableSize;
813 //
814 // Allocate at F segment according to PCI IRQ Routing Table Specification
815 //
816 Regs.X.BX = (UINT16) 0x1;
817 //
818 // 16-byte boundary alignment requirement according to
819 // PCI IRQ Routing Table Specification
820 //
821 Regs.X.DX = 0x10;
822 Private->LegacyBios.FarCall86 (
823 &Private->LegacyBios,
824 Private->Legacy16CallSegment,
825 Private->Legacy16CallOffset,
826 &Regs,
827 NULL,
828 0
829 );
830
831 Private->Legacy16Table->IrqRoutingTablePointer = (UINT32) (Regs.X.DS * 16 + Regs.X.BX);
832 if (Regs.X.AX != 0) {
833 DEBUG ((EFI_D_ERROR, "PIRQ table length insufficient - %x\n", PirqTableSize));
834 } else {
835 DEBUG ((EFI_D_INFO, "PIRQ table in legacy region - %x\n", Private->Legacy16Table->IrqRoutingTablePointer));
836 Private->Legacy16Table->IrqRoutingTableLength = (UINT32)PirqTableSize;
837 CopyMem (
838 (VOID *) (UINTN)Private->Legacy16Table->IrqRoutingTablePointer,
839 PirqTable,
840 PirqTableSize
841 );
842 }
843
844 Private->Cpu->FlushDataCache (Private->Cpu, 0xE0000, 0x20000, EfiCpuFlushTypeWriteBackInvalidate);
845 Private->LegacyRegion->Lock (
846 Private->LegacyRegion,
847 0xE0000,
848 0x20000,
849 &Granularity
850 );
851 }
852
853 Private->PciInterruptLine = TRUE;
854 mHandleCount = 0;
855 }
856
857 /**
858 Dump EFI_LEGACY_INSTALL_PCI_HANDLER structure information.
859
860 @param PciHandle The pointer to EFI_LEGACY_INSTALL_PCI_HANDLER structure
861
862 **/
863 VOID
864 DumpPciHandle (
865 IN EFI_LEGACY_INSTALL_PCI_HANDLER *PciHandle
866 )
867 {
868 DEBUG ((EFI_D_INFO, "PciBus - %02x\n", (UINTN)PciHandle->PciBus));
869 DEBUG ((EFI_D_INFO, "PciDeviceFun - %02x\n", (UINTN)PciHandle->PciDeviceFun));
870 DEBUG ((EFI_D_INFO, "PciSegment - %02x\n", (UINTN)PciHandle->PciSegment));
871 DEBUG ((EFI_D_INFO, "PciClass - %02x\n", (UINTN)PciHandle->PciClass));
872 DEBUG ((EFI_D_INFO, "PciSubclass - %02x\n", (UINTN)PciHandle->PciSubclass));
873 DEBUG ((EFI_D_INFO, "PciInterface - %02x\n", (UINTN)PciHandle->PciInterface));
874
875 DEBUG ((EFI_D_INFO, "PrimaryIrq - %02x\n", (UINTN)PciHandle->PrimaryIrq));
876 DEBUG ((EFI_D_INFO, "PrimaryReserved - %02x\n", (UINTN)PciHandle->PrimaryReserved));
877 DEBUG ((EFI_D_INFO, "PrimaryControl - %04x\n", (UINTN)PciHandle->PrimaryControl));
878 DEBUG ((EFI_D_INFO, "PrimaryBase - %04x\n", (UINTN)PciHandle->PrimaryBase));
879 DEBUG ((EFI_D_INFO, "PrimaryBusMaster - %04x\n", (UINTN)PciHandle->PrimaryBusMaster));
880
881 DEBUG ((EFI_D_INFO, "SecondaryIrq - %02x\n", (UINTN)PciHandle->SecondaryIrq));
882 DEBUG ((EFI_D_INFO, "SecondaryReserved - %02x\n", (UINTN)PciHandle->SecondaryReserved));
883 DEBUG ((EFI_D_INFO, "SecondaryControl - %04x\n", (UINTN)PciHandle->SecondaryControl));
884 DEBUG ((EFI_D_INFO, "SecondaryBase - %04x\n", (UINTN)PciHandle->SecondaryBase));
885 DEBUG ((EFI_D_INFO, "SecondaryBusMaster - %04x\n", (UINTN)PciHandle->SecondaryBusMaster));
886 return;
887 }
888
889 /**
890 Copy the $PIR table as required.
891
892 @param Private Legacy BIOS Instance data
893 @param PciIo Pointer to PCI_IO protocol
894 @param PciIrq Pci IRQ number
895 @param PciConfigHeader Type00 Pci configuration header
896
897 **/
898 VOID
899 InstallLegacyIrqHandler (
900 IN LEGACY_BIOS_INSTANCE *Private,
901 IN EFI_PCI_IO_PROTOCOL *PciIo,
902 IN UINT8 PciIrq,
903 IN PCI_TYPE00 *PciConfigHeader
904 )
905 {
906 EFI_IA32_REGISTER_SET Regs;
907 UINT16 LegMask;
908 UINTN PciSegment;
909 UINTN PciBus;
910 UINTN PciDevice;
911 UINTN PciFunction;
912 EFI_LEGACY_8259_PROTOCOL *Legacy8259;
913 UINT16 PrimaryMaster;
914 UINT16 SecondaryMaster;
915 UINTN TempData;
916 UINTN RegisterAddress;
917 UINT32 Granularity;
918
919 PrimaryMaster = 0;
920 SecondaryMaster = 0;
921 Legacy8259 = Private->Legacy8259;
922 //
923 // Disable interrupt in PIC, in case shared, to prevent an
924 // interrupt from occuring.
925 //
926 Legacy8259->GetMask (
927 Legacy8259,
928 &LegMask,
929 NULL,
930 NULL,
931 NULL
932 );
933
934 LegMask = (UINT16) (LegMask | (UINT16) (1 << PciIrq));
935
936 Legacy8259->SetMask (
937 Legacy8259,
938 &LegMask,
939 NULL,
940 NULL,
941 NULL
942 );
943
944 PciIo->GetLocation (
945 PciIo,
946 &PciSegment,
947 &PciBus,
948 &PciDevice,
949 &PciFunction
950 );
951 Private->IntThunk->PciHandler.PciBus = (UINT8) PciBus;
952 Private->IntThunk->PciHandler.PciDeviceFun = (UINT8) ((PciDevice << 3) + PciFunction);
953 Private->IntThunk->PciHandler.PciSegment = (UINT8) PciSegment;
954 Private->IntThunk->PciHandler.PciClass = PciConfigHeader->Hdr.ClassCode[2];
955 Private->IntThunk->PciHandler.PciSubclass = PciConfigHeader->Hdr.ClassCode[1];
956 Private->IntThunk->PciHandler.PciInterface = PciConfigHeader->Hdr.ClassCode[0];
957
958 //
959 // Use native mode base address registers in two cases:
960 // 1. Programming Interface (PI) register indicates Primary Controller is
961 // in native mode OR
962 // 2. PCI device Sub Class Code is not IDE
963 //
964 Private->IntThunk->PciHandler.PrimaryBusMaster = (UINT16)(PciConfigHeader->Device.Bar[4] & 0xfffc);
965 if (((PciConfigHeader->Hdr.ClassCode[0] & 0x01) != 0) || (PciConfigHeader->Hdr.ClassCode[1] != PCI_CLASS_MASS_STORAGE_IDE)) {
966 Private->IntThunk->PciHandler.PrimaryIrq = PciIrq;
967 Private->IntThunk->PciHandler.PrimaryBase = (UINT16) (PciConfigHeader->Device.Bar[0] & 0xfffc);
968 Private->IntThunk->PciHandler.PrimaryControl = (UINT16) ((PciConfigHeader->Device.Bar[1] & 0xfffc) + 2);
969 } else {
970 Private->IntThunk->PciHandler.PrimaryIrq = 14;
971 Private->IntThunk->PciHandler.PrimaryBase = 0x1f0;
972 Private->IntThunk->PciHandler.PrimaryControl = 0x3f6;
973 }
974 //
975 // Secondary controller data
976 //
977 if (Private->IntThunk->PciHandler.PrimaryBusMaster != 0) {
978 Private->IntThunk->PciHandler.SecondaryBusMaster = (UINT16) ((PciConfigHeader->Device.Bar[4] & 0xfffc) + 8);
979 PrimaryMaster = (UINT16) (Private->IntThunk->PciHandler.PrimaryBusMaster + 2);
980 SecondaryMaster = (UINT16) (Private->IntThunk->PciHandler.SecondaryBusMaster + 2);
981
982 //
983 // Clear pending interrupts in Bus Master registers
984 //
985 IoWrite16 (PrimaryMaster, 0x04);
986 IoWrite16 (SecondaryMaster, 0x04);
987
988 }
989
990 //
991 // Use native mode base address registers in two cases:
992 // 1. Programming Interface (PI) register indicates Secondary Controller is
993 // in native mode OR
994 // 2. PCI device Sub Class Code is not IDE
995 //
996 if (((PciConfigHeader->Hdr.ClassCode[0] & 0x04) != 0) || (PciConfigHeader->Hdr.ClassCode[1] != PCI_CLASS_MASS_STORAGE_IDE)) {
997 Private->IntThunk->PciHandler.SecondaryIrq = PciIrq;
998 Private->IntThunk->PciHandler.SecondaryBase = (UINT16) (PciConfigHeader->Device.Bar[2] & 0xfffc);
999 Private->IntThunk->PciHandler.SecondaryControl = (UINT16) ((PciConfigHeader->Device.Bar[3] & 0xfffc) + 2);
1000 } else {
1001
1002 Private->IntThunk->PciHandler.SecondaryIrq = 15;
1003 Private->IntThunk->PciHandler.SecondaryBase = 0x170;
1004 Private->IntThunk->PciHandler.SecondaryControl = 0x376;
1005 }
1006
1007 //
1008 // Clear pending interrupts in IDE Command Block Status reg before we
1009 // Thunk to CSM16 below. Don't want a pending Interrupt before we
1010 // install the handlers as wierd corruption would occur and hang system.
1011 //
1012 //
1013 // Read IDE CMD blk status reg to clear out any pending interrupts.
1014 // Do here for Primary and Secondary IDE channels
1015 //
1016 RegisterAddress = (UINT16)Private->IntThunk->PciHandler.PrimaryBase + 0x07;
1017 IoRead8 (RegisterAddress);
1018 RegisterAddress = (UINT16)Private->IntThunk->PciHandler.SecondaryBase + 0x07;
1019 IoRead8 (RegisterAddress);
1020
1021 Private->IntThunk->PciHandler.PrimaryReserved = 0;
1022 Private->IntThunk->PciHandler.SecondaryReserved = 0;
1023 Private->LegacyRegion->UnLock (
1024 Private->LegacyRegion,
1025 0xE0000,
1026 0x20000,
1027 &Granularity
1028 );
1029
1030 Regs.X.AX = Legacy16InstallPciHandler;
1031 TempData = (UINTN) &Private->IntThunk->PciHandler;
1032 Regs.X.ES = EFI_SEGMENT ((UINT32) TempData);
1033 Regs.X.BX = EFI_OFFSET ((UINT32) TempData);
1034
1035 DumpPciHandle (&Private->IntThunk->PciHandler);
1036
1037 Private->LegacyBios.FarCall86 (
1038 &Private->LegacyBios,
1039 Private->Legacy16CallSegment,
1040 Private->Legacy16CallOffset,
1041 &Regs,
1042 NULL,
1043 0
1044 );
1045
1046 Private->Cpu->FlushDataCache (Private->Cpu, 0xE0000, 0x20000, EfiCpuFlushTypeWriteBackInvalidate);
1047 Private->LegacyRegion->Lock (
1048 Private->LegacyRegion,
1049 0xE0000,
1050 0x20000,
1051 &Granularity
1052 );
1053
1054 }
1055
1056
1057 /**
1058 Program the interrupt routing register in all the PCI devices. On a PC AT system
1059 this register contains the 8259 IRQ vector that matches it's PCI interrupt.
1060
1061 @param Private Legacy BIOS Instance data
1062
1063 @retval EFI_SUCCESS Succeed.
1064 @retval EFI_ALREADY_STARTED All PCI devices have been processed.
1065
1066 **/
1067 EFI_STATUS
1068 PciProgramAllInterruptLineRegisters (
1069 IN LEGACY_BIOS_INSTANCE *Private
1070 )
1071 {
1072 EFI_STATUS Status;
1073 EFI_PCI_IO_PROTOCOL *PciIo;
1074 EFI_LEGACY_8259_PROTOCOL *Legacy8259;
1075 EFI_LEGACY_INTERRUPT_PROTOCOL *LegacyInterrupt;
1076 EFI_LEGACY_BIOS_PLATFORM_PROTOCOL *LegacyBiosPlatform;
1077 UINT8 InterruptPin;
1078 UINTN Index;
1079 UINTN HandleCount;
1080 EFI_HANDLE *HandleBuffer;
1081 UINTN MassStorageHandleCount;
1082 EFI_HANDLE *MassStorageHandleBuffer;
1083 UINTN MassStorageHandleIndex;
1084 UINT8 PciIrq;
1085 UINT16 Command;
1086 UINTN PciSegment;
1087 UINTN PciBus;
1088 UINTN PciDevice;
1089 UINTN PciFunction;
1090 EFI_LEGACY_IRQ_ROUTING_ENTRY *RoutingTable;
1091 UINTN RoutingTableEntries;
1092 UINT16 LegMask;
1093 UINT16 LegEdgeLevel;
1094 PCI_TYPE00 PciConfigHeader;
1095 EFI_LEGACY_PIRQ_TABLE_HEADER *PirqTable;
1096 UINTN PirqTableSize;
1097 UINTN Flags;
1098 HDD_INFO *HddInfo;
1099 UINT64 Supports;
1100
1101 //
1102 // Note - This routine use to return immediately if Private->PciInterruptLine
1103 // was true. Routine changed since resets etc can cause not all
1104 // PciIo protocols to be registered the first time through.
1105 // New algorithm is to do the copy $PIR table on first pass and save
1106 // HandleCount on first pass. If subsequent passes LocateHandleBuffer gives
1107 // a larger handle count then proceed with body of function else return
1108 // EFI_ALREADY_STARTED. In addition check if PCI device InterruptLine != 0.
1109 // If zero then function unprogrammed else skip function.
1110 //
1111 Legacy8259 = Private->Legacy8259;
1112 LegacyInterrupt = Private->LegacyInterrupt;
1113 LegacyBiosPlatform = Private->LegacyBiosPlatform;
1114
1115 LegacyBiosPlatform->GetRoutingTable (
1116 Private->LegacyBiosPlatform,
1117 (VOID *) &RoutingTable,
1118 &RoutingTableEntries,
1119 (VOID *) &PirqTable,
1120 &PirqTableSize,
1121 NULL,
1122 NULL
1123 );
1124 CreateBridgeTable (RoutingTable, RoutingTableEntries);
1125
1126 if (!Private->PciInterruptLine) {
1127 CopyPirqTable (
1128 Private,
1129 RoutingTable,
1130 RoutingTableEntries,
1131 PirqTable,
1132 PirqTableSize
1133 );
1134 }
1135
1136 Status = gBS->LocateHandleBuffer (
1137 ByProtocol,
1138 &gEfiPciIoProtocolGuid,
1139 NULL,
1140 &HandleCount,
1141 &HandleBuffer
1142 );
1143 if (EFI_ERROR (Status)) {
1144 return EFI_NOT_FOUND;
1145 }
1146 if (HandleCount == mHandleCount) {
1147 FreePool (HandleBuffer);
1148 return EFI_ALREADY_STARTED;
1149 }
1150
1151 if (mHandleCount == 0x00) {
1152 mHandleCount = HandleCount;
1153 }
1154
1155 for (Index = 0; Index < HandleCount; Index++) {
1156 //
1157 // If VGA then only do VGA to allow drives fore time to spin up
1158 // otherwise assign PCI IRQs to all potential devices.
1159 //
1160 if ((mVgaInstallationInProgress) && (HandleBuffer[Index] != mVgaHandle)) {
1161 continue;
1162 } else {
1163 //
1164 // Force code to go through all handles next time called if video.
1165 // This will catch case where HandleCount doesn't change but want
1166 // to get drive info etc.
1167 //
1168 mHandleCount = 0x00;
1169 }
1170
1171 Status = gBS->HandleProtocol (
1172 HandleBuffer[Index],
1173 &gEfiPciIoProtocolGuid,
1174 (VOID **) &PciIo
1175 );
1176 ASSERT_EFI_ERROR (Status);
1177
1178 //
1179 // Test whether the device can be enabled or not.
1180 // If it can't be enabled, then just skip it to avoid further operation.
1181 //
1182 PciIo->Pci.Read (
1183 PciIo,
1184 EfiPciIoWidthUint32,
1185 0,
1186 sizeof (PciConfigHeader) / sizeof (UINT32),
1187 &PciConfigHeader
1188 );
1189 Command = PciConfigHeader.Hdr.Command;
1190
1191 //
1192 // Note PciIo->Attributes does not program the PCI command register
1193 //
1194 Status = PciIo->Attributes (
1195 PciIo,
1196 EfiPciIoAttributeOperationSupported,
1197 0,
1198 &Supports
1199 );
1200 if (!EFI_ERROR (Status)) {
1201 Supports &= EFI_PCI_DEVICE_ENABLE;
1202 Status = PciIo->Attributes (
1203 PciIo,
1204 EfiPciIoAttributeOperationEnable,
1205 Supports,
1206 NULL
1207 );
1208 }
1209 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x04, 1, &Command);
1210
1211 if (EFI_ERROR (Status)) {
1212 continue;
1213 }
1214
1215 InterruptPin = PciConfigHeader.Device.InterruptPin;
1216
1217 if ((InterruptPin != 0) && (PciConfigHeader.Device.InterruptLine == PCI_INT_LINE_UNKNOWN)) {
1218 PciIo->GetLocation (
1219 PciIo,
1220 &PciSegment,
1221 &PciBus,
1222 &PciDevice,
1223 &PciFunction
1224 );
1225 //
1226 // Translate PIRQ index back thru busses to slot bus with InterruptPin
1227 // zero based
1228 //
1229 InterruptPin -= 1;
1230
1231 Status = GetBaseBus (
1232 Private,
1233 PciBus,
1234 PciDevice,
1235 RoutingTable,
1236 RoutingTableEntries
1237 );
1238
1239 if (Status == EFI_NOT_FOUND) {
1240 TranslateBusPirq (
1241 Private,
1242 &PciBus,
1243 &PciDevice,
1244 &PciFunction,
1245 &InterruptPin
1246 );
1247 }
1248 //
1249 // Translate InterruptPin(0-3) into PIRQ
1250 //
1251 Status = LegacyBiosPlatform->TranslatePirq (
1252 LegacyBiosPlatform,
1253 PciBus,
1254 (PciDevice << 3),
1255 PciFunction,
1256 &InterruptPin,
1257 &PciIrq
1258 );
1259 //
1260 // TranslatePirq() should never fail or we are in trouble
1261 // If it does return failure status, check your PIRQ routing table to see if some item is missing or incorrect
1262 //
1263 if (EFI_ERROR (Status)) {
1264 DEBUG ((EFI_D_ERROR, "Translate Pirq Failed - Status = %r\n ", Status));
1265 continue;
1266 }
1267
1268 LegacyInterrupt->WritePirq (
1269 LegacyInterrupt,
1270 InterruptPin,
1271 PciIrq
1272 );
1273
1274 //
1275 // Check if device has an OPROM associated with it.
1276 // If not invoke special 16-bit function, to allow 16-bit
1277 // code to install an interrupt handler.
1278 //
1279 Status = LegacyBiosCheckPciRom (
1280 &Private->LegacyBios,
1281 HandleBuffer[Index],
1282 NULL,
1283 NULL,
1284 &Flags
1285 );
1286 if ((EFI_ERROR (Status)) && (PciConfigHeader.Hdr.ClassCode[2] == PCI_CLASS_MASS_STORAGE)) {
1287 //
1288 // Device has no OPROM associated with it and is a mass storage
1289 // device. It needs to have an PCI IRQ handler installed. To
1290 // correctly install the handler we need to insure device is
1291 // connected. The device may just have register itself but not
1292 // been connected. Re-read PCI config space after as it can
1293 // change
1294 //
1295 //
1296 // Get IDE Handle. If matches handle then skip ConnectController
1297 // since ConnectController may force native mode and we don't
1298 // want that for primary IDE controller
1299 //
1300 MassStorageHandleCount = 0;
1301 MassStorageHandleBuffer = NULL;
1302 LegacyBiosPlatform->GetPlatformHandle (
1303 Private->LegacyBiosPlatform,
1304 EfiGetPlatformIdeHandle,
1305 0,
1306 &MassStorageHandleBuffer,
1307 &MassStorageHandleCount,
1308 NULL
1309 );
1310
1311 HddInfo = &Private->IntThunk->EfiToLegacy16BootTable.HddInfo[0];
1312
1313 LegacyBiosBuildIdeData (Private, &HddInfo, 0);
1314 PciIo->Pci.Read (
1315 PciIo,
1316 EfiPciIoWidthUint32,
1317 0,
1318 sizeof (PciConfigHeader) / sizeof (UINT32),
1319 &PciConfigHeader
1320 );
1321
1322 for (MassStorageHandleIndex = 0; MassStorageHandleIndex < MassStorageHandleCount; MassStorageHandleIndex++) {
1323 if (MassStorageHandleBuffer[MassStorageHandleIndex] == HandleBuffer[Index]) {
1324 //
1325 // InstallLegacyIrqHandler according to Platform requirement
1326 //
1327 InstallLegacyIrqHandler (
1328 Private,
1329 PciIo,
1330 PciIrq,
1331 &PciConfigHeader
1332 );
1333 break;
1334 }
1335 }
1336 }
1337 //
1338 // Write InterruptPin and enable 8259.
1339 //
1340 PciIo->Pci.Write (
1341 PciIo,
1342 EfiPciIoWidthUint8,
1343 0x3c,
1344 1,
1345 &PciIrq
1346 );
1347 Private->IntThunk->EfiToLegacy16BootTable.PciIrqMask = (UINT16) (Private->IntThunk->EfiToLegacy16BootTable.PciIrqMask | (UINT16) (1 << PciIrq));
1348
1349 Legacy8259->GetMask (
1350 Legacy8259,
1351 &LegMask,
1352 &LegEdgeLevel,
1353 NULL,
1354 NULL
1355 );
1356
1357 LegMask = (UINT16) (LegMask & (UINT16)~(1 << PciIrq));
1358 LegEdgeLevel = (UINT16) (LegEdgeLevel | (UINT16) (1 << PciIrq));
1359 Legacy8259->SetMask (
1360 Legacy8259,
1361 &LegMask,
1362 &LegEdgeLevel,
1363 NULL,
1364 NULL
1365 );
1366 }
1367 }
1368 FreePool (HandleBuffer);
1369 return EFI_SUCCESS;
1370 }
1371
1372
1373 /**
1374 Find & verify PnP Expansion header in ROM image
1375
1376 @param Private Protocol instance pointer.
1377 @param FirstHeader 1 = Find first header, 0 = Find successive headers
1378 @param PnpPtr Input Rom start if FirstHeader =1, Current Header
1379 otherwise Output Next header, if it exists
1380
1381 @retval EFI_SUCCESS Next Header found at BasePnpPtr
1382 @retval EFI_NOT_FOUND No more headers
1383
1384 **/
1385 EFI_STATUS
1386 FindNextPnpExpansionHeader (
1387 IN LEGACY_BIOS_INSTANCE *Private,
1388 IN BOOLEAN FirstHeader,
1389 IN OUT LEGACY_PNP_EXPANSION_HEADER **PnpPtr
1390
1391 )
1392 {
1393 UINTN TempData;
1394 LEGACY_PNP_EXPANSION_HEADER *LocalPnpPtr;
1395 LocalPnpPtr = *PnpPtr;
1396 if (FirstHeader == FIRST_INSTANCE) {
1397 mBasePnpPtr = LocalPnpPtr;
1398 mBbsRomSegment = (UINT16) ((UINTN) mBasePnpPtr >> 4);
1399 //
1400 // Offset 0x1a gives offset to PnP expansion header for the first
1401 // instance, there after the structure gives the offset to the next
1402 // structure
1403 //
1404 LocalPnpPtr = (LEGACY_PNP_EXPANSION_HEADER *) ((UINT8 *) LocalPnpPtr + 0x1a);
1405 TempData = (*((UINT16 *) LocalPnpPtr));
1406 } else {
1407 TempData = (UINT16) LocalPnpPtr->NextHeader;
1408 }
1409
1410 LocalPnpPtr = (LEGACY_PNP_EXPANSION_HEADER *) (((UINT8 *) mBasePnpPtr + TempData));
1411
1412 //
1413 // Search for PnP table in Shadowed ROM
1414 //
1415 *PnpPtr = LocalPnpPtr;
1416 if (*(UINT32 *) LocalPnpPtr == SIGNATURE_32 ('$', 'P', 'n', 'P')) {
1417 return EFI_SUCCESS;
1418 } else {
1419 return EFI_NOT_FOUND;
1420 }
1421 }
1422
1423
1424 /**
1425 Update list of Bev or BCV table entries.
1426
1427 @param Private Protocol instance pointer.
1428 @param RomStart Table of ROM start address in RAM/ROM. PciIo _
1429 Handle to PCI IO for this device
1430 @param PciIo Instance of PCI I/O Protocol
1431
1432 @retval EFI_SUCCESS Always should succeed.
1433
1434 **/
1435 EFI_STATUS
1436 UpdateBevBcvTable (
1437 IN LEGACY_BIOS_INSTANCE *Private,
1438 IN EFI_LEGACY_EXPANSION_ROM_HEADER *RomStart,
1439 IN EFI_PCI_IO_PROTOCOL *PciIo
1440 )
1441 {
1442 VOID *RomEnd;
1443 BBS_TABLE *BbsTable;
1444 UINTN BbsIndex;
1445 EFI_LEGACY_EXPANSION_ROM_HEADER *PciPtr;
1446 LEGACY_PNP_EXPANSION_HEADER *PnpPtr;
1447 BOOLEAN Instance;
1448 EFI_STATUS Status;
1449 UINTN Segment;
1450 UINTN Bus;
1451 UINTN Device;
1452 UINTN Function;
1453 UINT8 Class;
1454 UINT16 DeviceType;
1455 Segment = 0;
1456 Bus = 0;
1457 Device = 0;
1458 Function = 0;
1459 Class = 0;
1460 DeviceType = BBS_UNKNOWN;
1461
1462 //
1463 // Skip floppy and 2*onboard IDE controller entries(Master/Slave per
1464 // controller).
1465 //
1466 BbsIndex = Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries;
1467
1468 BbsTable = (BBS_TABLE*)(UINTN) Private->IntThunk->EfiToLegacy16BootTable.BbsTable;
1469 PnpPtr = (LEGACY_PNP_EXPANSION_HEADER *) RomStart;
1470 PciPtr = (EFI_LEGACY_EXPANSION_ROM_HEADER *) RomStart;
1471
1472 RomEnd = (VOID *) (PciPtr->Size512 * 512 + (UINTN) PciPtr);
1473 Instance = FIRST_INSTANCE;
1474 //
1475 // OPROMs like PXE may not be tied to a piece of hardware and thus
1476 // don't have a PciIo associated with them
1477 //
1478 if (PciIo != NULL) {
1479 PciIo->GetLocation (
1480 PciIo,
1481 &Segment,
1482 &Bus,
1483 &Device,
1484 &Function
1485 );
1486 PciIo->Pci.Read (
1487 PciIo,
1488 EfiPciIoWidthUint8,
1489 0x0b,
1490 1,
1491 &Class
1492 );
1493
1494 if (Class == PCI_CLASS_MASS_STORAGE) {
1495 DeviceType = BBS_HARDDISK;
1496 } else {
1497 if (Class == PCI_CLASS_NETWORK) {
1498 DeviceType = BBS_EMBED_NETWORK;
1499 }
1500 }
1501 }
1502
1503 if (PciPtr >= (EFI_LEGACY_EXPANSION_ROM_HEADER *) ((UINTN) 0xc8000)) {
1504 while (TRUE) {
1505 Status = FindNextPnpExpansionHeader (Private, Instance, &PnpPtr);
1506 Instance = NOT_FIRST_INSTANCE;
1507 if (EFI_ERROR (Status)) {
1508 break;
1509 }
1510 //
1511 // There can be additional $PnP headers within the OPROM.
1512 // Example: SCSI can have one per drive.
1513 //
1514 BbsTable[BbsIndex].BootPriority = BBS_UNPRIORITIZED_ENTRY;
1515 BbsTable[BbsIndex].DeviceType = DeviceType;
1516 BbsTable[BbsIndex].Bus = (UINT32) Bus;
1517 BbsTable[BbsIndex].Device = (UINT32) Device;
1518 BbsTable[BbsIndex].Function = (UINT32) Function;
1519 BbsTable[BbsIndex].StatusFlags.OldPosition = 0;
1520 BbsTable[BbsIndex].StatusFlags.Reserved1 = 0;
1521 BbsTable[BbsIndex].StatusFlags.Enabled = 0;
1522 BbsTable[BbsIndex].StatusFlags.Failed = 0;
1523 BbsTable[BbsIndex].StatusFlags.MediaPresent = 0;
1524 BbsTable[BbsIndex].StatusFlags.Reserved2 = 0;
1525 BbsTable[BbsIndex].Class = PnpPtr->Class;
1526 BbsTable[BbsIndex].SubClass = PnpPtr->SubClass;
1527 BbsTable[BbsIndex].DescStringOffset = PnpPtr->ProductNamePointer;
1528 BbsTable[BbsIndex].DescStringSegment = mBbsRomSegment;
1529 BbsTable[BbsIndex].MfgStringOffset = PnpPtr->MfgPointer;
1530 BbsTable[BbsIndex].MfgStringSegment = mBbsRomSegment;
1531 BbsTable[BbsIndex].BootHandlerSegment = mBbsRomSegment;
1532
1533 //
1534 // Have seen case where PXE base code have PnP expansion ROM
1535 // header but no Bcv or Bev vectors.
1536 //
1537 if (PnpPtr->Bcv != 0) {
1538 BbsTable[BbsIndex].BootHandlerOffset = PnpPtr->Bcv;
1539 ++BbsIndex;
1540 }
1541
1542 if (PnpPtr->Bev != 0) {
1543 BbsTable[BbsIndex].BootHandlerOffset = PnpPtr->Bev;
1544 BbsTable[BbsIndex].DeviceType = BBS_BEV_DEVICE;
1545 ++BbsIndex;
1546 }
1547
1548 if ((PnpPtr == (LEGACY_PNP_EXPANSION_HEADER *) PciPtr) || (PnpPtr > (LEGACY_PNP_EXPANSION_HEADER *) RomEnd)) {
1549 break;
1550 }
1551 }
1552 }
1553
1554 BbsTable[BbsIndex].BootPriority = BBS_IGNORE_ENTRY;
1555 Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries = (UINT32) BbsIndex;
1556 return EFI_SUCCESS;
1557 }
1558
1559
1560 /**
1561 Shadow all the PCI legacy ROMs. Use data from the Legacy BIOS Protocol
1562 to chose the order. Skip any devices that have already have legacy
1563 BIOS run.
1564
1565 @param Private Protocol instance pointer.
1566
1567 @retval EFI_SUCCESS Succeed.
1568 @retval EFI_UNSUPPORTED Cannot get VGA device handle.
1569
1570 **/
1571 EFI_STATUS
1572 PciShadowRoms (
1573 IN LEGACY_BIOS_INSTANCE *Private
1574 )
1575 {
1576 EFI_STATUS Status;
1577 EFI_PCI_IO_PROTOCOL *PciIo;
1578 PCI_TYPE00 Pci;
1579 UINTN Index;
1580 UINTN HandleCount;
1581 EFI_HANDLE *HandleBuffer;
1582 EFI_HANDLE VgaHandle;
1583 EFI_HANDLE FirstHandle;
1584 VOID **RomStart;
1585 UINTN Flags;
1586 PCI_TYPE00 PciConfigHeader;
1587 UINT16 *Command;
1588 UINT64 Supports;
1589
1590 //
1591 // Make the VGA device first
1592 //
1593 Status = Private->LegacyBiosPlatform->GetPlatformHandle (
1594 Private->LegacyBiosPlatform,
1595 EfiGetPlatformVgaHandle,
1596 0,
1597 &HandleBuffer,
1598 &HandleCount,
1599 NULL
1600 );
1601 if (EFI_ERROR (Status)) {
1602 return EFI_UNSUPPORTED;
1603 }
1604
1605 VgaHandle = HandleBuffer[0];
1606
1607 Status = gBS->LocateHandleBuffer (
1608 ByProtocol,
1609 &gEfiPciIoProtocolGuid,
1610 NULL,
1611 &HandleCount,
1612 &HandleBuffer
1613 );
1614
1615 if (EFI_ERROR (Status)) {
1616 return Status;
1617 }
1618 //
1619 // Place the VGA handle as first.
1620 //
1621 for (Index = 0; Index < HandleCount; Index++) {
1622 if (HandleBuffer[Index] == VgaHandle) {
1623 FirstHandle = HandleBuffer[0];
1624 HandleBuffer[0] = HandleBuffer[Index];
1625 HandleBuffer[Index] = FirstHandle;
1626 break;
1627 }
1628 }
1629 //
1630 // Allocate memory to save Command WORD from each device. We do this
1631 // to restore devices to same state as EFI after switching to legacy.
1632 //
1633 Command = (UINT16 *) AllocatePool (
1634 sizeof (UINT16) * (HandleCount + 1)
1635 );
1636 if (NULL == Command) {
1637 FreePool (HandleBuffer);
1638 return EFI_OUT_OF_RESOURCES;
1639 }
1640 //
1641 // Disconnect all EFI devices first. This covers cases where alegacy BIOS
1642 // may control multiple PCI devices.
1643 //
1644 for (Index = 0; Index < HandleCount; Index++) {
1645
1646 Status = gBS->HandleProtocol (
1647 HandleBuffer[Index],
1648 &gEfiPciIoProtocolGuid,
1649 (VOID **) &PciIo
1650 );
1651 ASSERT_EFI_ERROR (Status);
1652
1653 //
1654 // Save command register for "connect" loop
1655 //
1656 PciIo->Pci.Read (
1657 PciIo,
1658 EfiPciIoWidthUint32,
1659 0,
1660 sizeof (PciConfigHeader) / sizeof (UINT32),
1661 &PciConfigHeader
1662 );
1663 Command[Index] = PciConfigHeader.Hdr.Command;
1664 //
1665 // Skip any device that already has a legacy ROM run
1666 //
1667 Status = IsLegacyRom (HandleBuffer[Index]);
1668 if (!EFI_ERROR (Status)) {
1669 continue;
1670 }
1671 //
1672 // Stop EFI Drivers with oprom.
1673 //
1674 gBS->DisconnectController (
1675 HandleBuffer[Index],
1676 NULL,
1677 NULL
1678 );
1679 }
1680 //
1681 // For every device that has not had a legacy ROM started. Start a legacy ROM.
1682 //
1683 for (Index = 0; Index < HandleCount; Index++) {
1684
1685 Status = gBS->HandleProtocol (
1686 HandleBuffer[Index],
1687 &gEfiPciIoProtocolGuid,
1688 (VOID **) &PciIo
1689 );
1690
1691 ASSERT_EFI_ERROR (Status);
1692
1693 //
1694 // Here make sure if one VGA have been shadowed,
1695 // then wil not shadowed another one.
1696 //
1697 PciIo->Pci.Read (
1698 PciIo,
1699 EfiPciIoWidthUint32,
1700 0,
1701 sizeof (Pci) / sizeof (UINT32),
1702 &Pci
1703 );
1704
1705 //
1706 // Only one Video OPROM can be given control in BIOS phase. If there are multiple Video devices,
1707 // one will work in legacy mode (OPROM will be given control) and
1708 // other Video devices will work in native mode (OS driver will handle these devices).
1709 //
1710 if (IS_PCI_DISPLAY (&Pci) && Index != 0) {
1711 continue;
1712 }
1713 //
1714 // Skip any device that already has a legacy ROM run
1715 //
1716 Status = IsLegacyRom (HandleBuffer[Index]);
1717 if (!EFI_ERROR (Status)) {
1718 continue;
1719 }
1720 //
1721 // Install legacy ROM
1722 //
1723 Status = LegacyBiosInstallPciRom (
1724 &Private->LegacyBios,
1725 HandleBuffer[Index],
1726 NULL,
1727 &Flags,
1728 NULL,
1729 NULL,
1730 (VOID **) &RomStart,
1731 NULL
1732 );
1733 if (EFI_ERROR (Status)) {
1734 if (!((Status == EFI_UNSUPPORTED) && (Flags == NO_ROM))) {
1735 continue;
1736 }
1737 }
1738 //
1739 // Restore Command register so legacy has same devices enabled or disabled
1740 // as EFI.
1741 // If Flags = NO_ROM use command register as is. This covers the
1742 // following cases:
1743 // Device has no ROMs associated with it.
1744 // Device has ROM associated with it but was already
1745 // installed.
1746 // = ROM_FOUND but not VALID_LEGACY_ROM, disable it.
1747 // = ROM_FOUND and VALID_LEGACY_ROM, enable it.
1748 //
1749 if ((Flags & ROM_FOUND) == ROM_FOUND) {
1750 if ((Flags & VALID_LEGACY_ROM) == 0) {
1751 Command[Index] = 0;
1752 } else {
1753 //
1754 // For several VGAs, only one of them can be enabled.
1755 //
1756 Status = PciIo->Attributes (
1757 PciIo,
1758 EfiPciIoAttributeOperationSupported,
1759 0,
1760 &Supports
1761 );
1762 if (!EFI_ERROR (Status)) {
1763 Supports &= EFI_PCI_DEVICE_ENABLE;
1764 Status = PciIo->Attributes (
1765 PciIo,
1766 EfiPciIoAttributeOperationEnable,
1767 Supports,
1768 NULL
1769 );
1770 }
1771 if (!EFI_ERROR (Status)) {
1772 Command[Index] = 0x1f;
1773 }
1774 }
1775 }
1776
1777 PciIo->Pci.Write (
1778 PciIo,
1779 EfiPciIoWidthUint16,
1780 0x04,
1781 1,
1782 &Command[Index]
1783 );
1784 }
1785
1786 FreePool (Command);
1787 FreePool (HandleBuffer);
1788 return EFI_SUCCESS;
1789 }
1790
1791
1792 /**
1793 Test to see if a legacy PCI ROM exists for this device. Optionally return
1794 the Legacy ROM instance for this PCI device.
1795
1796 @param This Protocol instance pointer.
1797 @param PciHandle The PCI PC-AT OPROM from this devices ROM BAR will
1798 be loaded
1799 @param RomImage Return the legacy PCI ROM for this device
1800 @param RomSize Size of ROM Image
1801 @param Flags Indicates if ROM found and if PC-AT.
1802
1803 @retval EFI_SUCCESS Legacy Option ROM availible for this device
1804 @retval EFI_UNSUPPORTED Legacy Option ROM not supported.
1805
1806 **/
1807 EFI_STATUS
1808 EFIAPI
1809 LegacyBiosCheckPciRom (
1810 IN EFI_LEGACY_BIOS_PROTOCOL *This,
1811 IN EFI_HANDLE PciHandle,
1812 OUT VOID **RomImage, OPTIONAL
1813 OUT UINTN *RomSize, OPTIONAL
1814 OUT UINTN *Flags
1815 )
1816 {
1817 return LegacyBiosCheckPciRomEx (
1818 This,
1819 PciHandle,
1820 RomImage,
1821 RomSize,
1822 NULL,
1823 Flags,
1824 NULL,
1825 NULL
1826 );
1827
1828 }
1829
1830 /**
1831
1832 Routine Description:
1833 Test to see if a legacy PCI ROM exists for this device. Optionally return
1834 the Legacy ROM instance for this PCI device.
1835
1836 @param[in] This Protocol instance pointer.
1837 @param[in] PciHandle The PCI PC-AT OPROM from this devices ROM BAR will be loaded
1838 @param[out] RomImage Return the legacy PCI ROM for this device
1839 @param[out] RomSize Size of ROM Image
1840 @param[out] RuntimeImageLength Runtime size of ROM Image
1841 @param[out] Flags Indicates if ROM found and if PC-AT.
1842 @param[out] OpromRevision Revision of the PCI Rom
1843 @param[out] ConfigUtilityCodeHeaderPointer of Configuration Utility Code Header
1844
1845 @return EFI_SUCCESS Legacy Option ROM availible for this device
1846 @return EFI_ALREADY_STARTED This device is already managed by its Oprom
1847 @return EFI_UNSUPPORTED Legacy Option ROM not supported.
1848
1849 **/
1850 EFI_STATUS
1851 LegacyBiosCheckPciRomEx (
1852 IN EFI_LEGACY_BIOS_PROTOCOL *This,
1853 IN EFI_HANDLE PciHandle,
1854 OUT VOID **RomImage, OPTIONAL
1855 OUT UINTN *RomSize, OPTIONAL
1856 OUT UINTN *RuntimeImageLength, OPTIONAL
1857 OUT UINTN *Flags, OPTIONAL
1858 OUT UINT8 *OpromRevision, OPTIONAL
1859 OUT VOID **ConfigUtilityCodeHeader OPTIONAL
1860 )
1861 {
1862 EFI_STATUS Status;
1863 LEGACY_BIOS_INSTANCE *Private;
1864 EFI_PCI_IO_PROTOCOL *PciIo;
1865 UINTN LocalRomSize;
1866 VOID *LocalRomImage;
1867 PCI_TYPE00 PciConfigHeader;
1868 VOID *LocalConfigUtilityCodeHeader;
1869
1870 *Flags = NO_ROM;
1871 Status = gBS->HandleProtocol (
1872 PciHandle,
1873 &gEfiPciIoProtocolGuid,
1874 (VOID **) &PciIo
1875 );
1876 if (EFI_ERROR (Status)) {
1877 return EFI_UNSUPPORTED;
1878 }
1879
1880 //
1881 // See if the option ROM for PciHandle has already been executed
1882 //
1883 Status = IsLegacyRom (PciHandle);
1884 if (!EFI_ERROR (Status)) {
1885 *Flags |= (ROM_FOUND | VALID_LEGACY_ROM);
1886 return EFI_SUCCESS;
1887 }
1888 //
1889 // Check for PCI ROM Bar
1890 //
1891 LocalRomSize = (UINTN) PciIo->RomSize;
1892 LocalRomImage = PciIo->RomImage;
1893 if (LocalRomSize != 0) {
1894 *Flags |= ROM_FOUND;
1895 }
1896
1897 //
1898 // PCI specification states you should check VendorId and Device Id.
1899 //
1900 PciIo->Pci.Read (
1901 PciIo,
1902 EfiPciIoWidthUint32,
1903 0,
1904 sizeof (PciConfigHeader) / sizeof (UINT32),
1905 &PciConfigHeader
1906 );
1907
1908 Private = LEGACY_BIOS_INSTANCE_FROM_THIS (This);
1909 Status = GetPciLegacyRom (
1910 Private->Csm16PciInterfaceVersion,
1911 PciConfigHeader.Hdr.VendorId,
1912 PciConfigHeader.Hdr.DeviceId,
1913 &LocalRomImage,
1914 &LocalRomSize,
1915 RuntimeImageLength,
1916 OpromRevision,
1917 &LocalConfigUtilityCodeHeader
1918 );
1919 if (EFI_ERROR (Status)) {
1920 return EFI_UNSUPPORTED;
1921 }
1922
1923 *Flags |= VALID_LEGACY_ROM;
1924
1925 //
1926 // See if Configuration Utility Code Header valid
1927 //
1928 if (LocalConfigUtilityCodeHeader != NULL) {
1929 *Flags |= ROM_WITH_CONFIG;
1930 }
1931
1932 if (ConfigUtilityCodeHeader != NULL) {
1933 *ConfigUtilityCodeHeader = LocalConfigUtilityCodeHeader;
1934 }
1935
1936 if (RomImage != NULL) {
1937 *RomImage = LocalRomImage;
1938 }
1939
1940 if (RomSize != NULL) {
1941 *RomSize = LocalRomSize;
1942 }
1943
1944 return EFI_SUCCESS;
1945 }
1946
1947 /**
1948 Load a legacy PC-AT OPROM on the PciHandle device. Return information
1949 about how many disks were added by the OPROM and the shadow address and
1950 size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C:
1951
1952 @retval EFI_SUCCESS Legacy ROM loaded for this device
1953 @retval EFI_NOT_FOUND No PS2 Keyboard found
1954
1955 **/
1956 EFI_STATUS
1957 EnablePs2Keyboard (
1958 VOID
1959 )
1960 {
1961 EFI_STATUS Status;
1962 EFI_HANDLE *HandleBuffer;
1963 UINTN HandleCount;
1964 EFI_ISA_IO_PROTOCOL *IsaIo;
1965 UINTN Index;
1966
1967 //
1968 // Get SimpleTextIn and find PS2 controller
1969 //
1970 Status = gBS->LocateHandleBuffer (
1971 ByProtocol,
1972 &gEfiSimpleTextInProtocolGuid,
1973 NULL,
1974 &HandleCount,
1975 &HandleBuffer
1976 );
1977 if (EFI_ERROR (Status)) {
1978 return EFI_NOT_FOUND;
1979 }
1980 for (Index = 0; Index < HandleCount; Index++) {
1981 //
1982 // Open the IO Abstraction(s) needed to perform the supported test
1983 //
1984 Status = gBS->OpenProtocol (
1985 HandleBuffer[Index],
1986 &gEfiIsaIoProtocolGuid,
1987 (VOID **) &IsaIo,
1988 NULL,
1989 HandleBuffer[Index],
1990 EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL
1991 );
1992
1993 if (!EFI_ERROR (Status)) {
1994 //
1995 // Use the ISA I/O Protocol to see if Controller is the Keyboard
1996 // controller
1997 //
1998 if (IsaIo->ResourceList->Device.HID != EISA_PNP_ID (0x303) || IsaIo->ResourceList->Device.UID != 0) {
1999 Status = EFI_UNSUPPORTED;
2000 }
2001
2002 gBS->CloseProtocol (
2003 HandleBuffer[Index],
2004 &gEfiIsaIoProtocolGuid,
2005 NULL,
2006 HandleBuffer[Index]
2007 );
2008 }
2009
2010 if (!EFI_ERROR (Status)) {
2011 gBS->ConnectController (HandleBuffer[Index], NULL, NULL, FALSE);
2012 }
2013 }
2014 FreePool (HandleBuffer);
2015 return EFI_SUCCESS;
2016 }
2017
2018
2019 /**
2020 Load a legacy PC-AT OpROM for VGA controller.
2021
2022 @param Private Driver private data.
2023
2024 @retval EFI_SUCCESS Legacy ROM successfully installed for this device.
2025 @retval EFI_DEVICE_ERROR No VGA device handle found, or native EFI video
2026 driver cannot be successfully disconnected, or VGA
2027 thunk driver cannot be successfully connected.
2028
2029 **/
2030 EFI_STATUS
2031 LegacyBiosInstallVgaRom (
2032 IN LEGACY_BIOS_INSTANCE *Private
2033 )
2034 {
2035 EFI_STATUS Status;
2036 EFI_HANDLE VgaHandle;
2037 UINTN HandleCount;
2038 EFI_HANDLE *HandleBuffer;
2039 EFI_HANDLE *ConnectHandleBuffer;
2040 EFI_PCI_IO_PROTOCOL *PciIo;
2041 PCI_TYPE00 PciConfigHeader;
2042 UINT64 Supports;
2043 EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfoBuffer;
2044 UINTN EntryCount;
2045 UINTN Index;
2046 VOID *Interface;
2047
2048 //
2049 // EfiLegacyBiosGuild attached to a device implies that there is a legacy
2050 // BIOS associated with that device.
2051 //
2052 // There are 3 cases to consider.
2053 // Case 1: No EFI driver is controlling the video.
2054 // Action: Return EFI_SUCCESS from DisconnectController, search
2055 // video thunk driver, and connect it.
2056 // Case 2: EFI driver is controlling the video and EfiLegacyBiosGuid is
2057 // not on the image handle.
2058 // Action: Disconnect EFI driver.
2059 // ConnectController for video thunk
2060 // Case 3: EFI driver is controlling the video and EfiLegacyBiosGuid is
2061 // on the image handle.
2062 // Action: Do nothing and set Private->VgaInstalled = TRUE.
2063 // Then this routine is not called any more.
2064 //
2065 //
2066 // Get the VGA device.
2067 //
2068 Status = Private->LegacyBiosPlatform->GetPlatformHandle (
2069 Private->LegacyBiosPlatform,
2070 EfiGetPlatformVgaHandle,
2071 0,
2072 &HandleBuffer,
2073 &HandleCount,
2074 NULL
2075 );
2076 if (EFI_ERROR (Status)) {
2077 return EFI_DEVICE_ERROR;
2078 }
2079
2080 VgaHandle = HandleBuffer[0];
2081
2082 //
2083 // Check whether video thunk driver already starts.
2084 //
2085 Status = gBS->OpenProtocolInformation (
2086 VgaHandle,
2087 &gEfiPciIoProtocolGuid,
2088 &OpenInfoBuffer,
2089 &EntryCount
2090 );
2091 if (EFI_ERROR (Status)) {
2092 return Status;
2093 }
2094
2095 for (Index = 0; Index < EntryCount; Index++) {
2096 if ((OpenInfoBuffer[Index].Attributes & EFI_OPEN_PROTOCOL_BY_DRIVER) != 0) {
2097 Status = gBS->HandleProtocol (
2098 OpenInfoBuffer[Index].AgentHandle,
2099 &gEfiLegacyBiosGuid,
2100 (VOID **) &Interface
2101 );
2102 if (!EFI_ERROR (Status)) {
2103 //
2104 // This should be video thunk driver which is managing video device
2105 // So it need not start again
2106 //
2107 DEBUG ((EFI_D_INFO, "Video thunk driver already start! Return!\n"));
2108 Private->VgaInstalled = TRUE;
2109 return EFI_SUCCESS;
2110 }
2111 }
2112 }
2113
2114 //
2115 // Kick off the native EFI driver
2116 //
2117 Status = gBS->DisconnectController (
2118 VgaHandle,
2119 NULL,
2120 NULL
2121 );
2122 if (EFI_ERROR (Status)) {
2123 if (Status != EFI_NOT_FOUND) {
2124 return EFI_DEVICE_ERROR;
2125 } else {
2126 return Status;
2127 }
2128 }
2129 //
2130 // Find all the Thunk Driver
2131 //
2132 HandleBuffer = NULL;
2133 Status = gBS->LocateHandleBuffer (
2134 ByProtocol,
2135 &gEfiLegacyBiosGuid,
2136 NULL,
2137 &HandleCount,
2138 &HandleBuffer
2139 );
2140 ASSERT_EFI_ERROR (Status);
2141 ConnectHandleBuffer = (EFI_HANDLE *) AllocatePool (sizeof (EFI_HANDLE) * (HandleCount + 1));
2142 ASSERT (ConnectHandleBuffer != NULL);
2143
2144 CopyMem (
2145 ConnectHandleBuffer,
2146 HandleBuffer,
2147 sizeof (EFI_HANDLE) * HandleCount
2148 );
2149 ConnectHandleBuffer[HandleCount] = NULL;
2150
2151 FreePool (HandleBuffer);
2152
2153 //
2154 // Enable the device and make sure VGA cycles are being forwarded to this VGA device
2155 //
2156 Status = gBS->HandleProtocol (
2157 VgaHandle,
2158 &gEfiPciIoProtocolGuid,
2159 (VOID **) &PciIo
2160 );
2161 ASSERT_EFI_ERROR (Status);
2162 PciIo->Pci.Read (
2163 PciIo,
2164 EfiPciIoWidthUint32,
2165 0,
2166 sizeof (PciConfigHeader) / sizeof (UINT32),
2167 &PciConfigHeader
2168 );
2169
2170 Status = PciIo->Attributes (
2171 PciIo,
2172 EfiPciIoAttributeOperationSupported,
2173 0,
2174 &Supports
2175 );
2176 if (!EFI_ERROR (Status)) {
2177 Supports &= EFI_PCI_DEVICE_ENABLE | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | \
2178 EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_VGA_IO_16;
2179 Status = PciIo->Attributes (
2180 PciIo,
2181 EfiPciIoAttributeOperationEnable,
2182 Supports,
2183 NULL
2184 );
2185 }
2186
2187 if (Status == EFI_SUCCESS) {
2188 Private->VgaInstalled = TRUE;
2189
2190 //
2191 // Attach the VGA thunk driver.
2192 // Assume the video is installed. This prevents potential of infinite recursion.
2193 //
2194 Status = gBS->ConnectController (
2195 VgaHandle,
2196 ConnectHandleBuffer,
2197 NULL,
2198 TRUE
2199 );
2200 }
2201
2202 FreePool (ConnectHandleBuffer);
2203
2204 if (EFI_ERROR (Status)) {
2205
2206 Private->VgaInstalled = FALSE;
2207
2208 //
2209 // Reconnect the EFI VGA driver.
2210 //
2211 gBS->ConnectController (VgaHandle, NULL, NULL, TRUE);
2212 return EFI_DEVICE_ERROR;
2213 }
2214
2215 return EFI_SUCCESS;
2216 }
2217
2218
2219 /**
2220 Load a legacy PC-AT OpROM.
2221
2222 @param This Protocol instance pointer.
2223 @param Private Driver's private data.
2224 @param PciHandle The EFI handle for the PCI device. It could be
2225 NULL if the OpROM image is not associated with
2226 any device.
2227 @param OpromRevision The revision of PCI PC-AT ROM image.
2228 @param RomImage Pointer to PCI PC-AT ROM image header. It must not
2229 be NULL.
2230 @param ImageSize Size of the PCI PC-AT ROM image.
2231 @param RuntimeImageLength On input is the max runtime image length indicated by the PCIR structure
2232 On output is the actual runtime image length
2233 @param DiskStart Disk number of first device hooked by the ROM. If
2234 DiskStart is the same as DiskEnd no disked were
2235 hooked.
2236 @param DiskEnd Disk number of the last device hooked by the ROM.
2237 @param RomShadowAddress Shadow address of PC-AT ROM
2238
2239 @retval EFI_SUCCESS Legacy ROM loaded for this device
2240 @retval EFI_OUT_OF_RESOURCES No more space for this ROM
2241
2242 **/
2243 EFI_STATUS
2244 EFIAPI
2245 LegacyBiosInstallRom (
2246 IN EFI_LEGACY_BIOS_PROTOCOL *This,
2247 IN LEGACY_BIOS_INSTANCE *Private,
2248 IN EFI_HANDLE PciHandle,
2249 IN UINT8 OpromRevision,
2250 IN VOID *RomImage,
2251 IN UINTN ImageSize,
2252 IN OUT UINTN *RuntimeImageLength,
2253 OUT UINT8 *DiskStart, OPTIONAL
2254 OUT UINT8 *DiskEnd, OPTIONAL
2255 OUT VOID **RomShadowAddress OPTIONAL
2256 )
2257 {
2258 EFI_STATUS Status;
2259 EFI_STATUS PciEnableStatus;
2260 EFI_PCI_IO_PROTOCOL *PciIo;
2261 UINT8 LocalDiskStart;
2262 UINT8 LocalDiskEnd;
2263 UINTN Segment;
2264 UINTN Bus;
2265 UINTN Device;
2266 UINTN Function;
2267 EFI_IA32_REGISTER_SET Regs;
2268 UINT8 VideoMode;
2269 EFI_TIME BootTime;
2270 UINT32 *BdaPtr;
2271 UINT32 LocalTime;
2272 UINT32 StartBbsIndex;
2273 UINT32 EndBbsIndex;
2274 UINTN TempData;
2275 UINTN InitAddress;
2276 UINTN RuntimeAddress;
2277 EFI_PHYSICAL_ADDRESS PhysicalAddress;
2278 UINT32 Granularity;
2279
2280 PciIo = NULL;
2281 LocalDiskStart = 0;
2282 LocalDiskEnd = 0;
2283 Segment = 0;
2284 Bus = 0;
2285 Device = 0;
2286 Function = 0;
2287 VideoMode = 0;
2288 PhysicalAddress = 0;
2289
2290 PciProgramAllInterruptLineRegisters (Private);
2291
2292 if ((OpromRevision >= 3) && (Private->Csm16PciInterfaceVersion >= 0x0300)) {
2293 //
2294 // CSM16 3.0 meets PCI 3.0 OpROM
2295 // first test if there is enough space for its INIT code
2296 //
2297 PhysicalAddress = CONVENTIONAL_MEMORY_TOP;
2298 Status = gBS->AllocatePages (
2299 AllocateMaxAddress,
2300 EfiBootServicesCode,
2301 EFI_SIZE_TO_PAGES (ImageSize),
2302 &PhysicalAddress
2303 );
2304
2305 if (EFI_ERROR (Status)) {
2306 DEBUG ((EFI_D_ERROR, "return LegacyBiosInstallRom(%d): EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", __LINE__));
2307 return EFI_OUT_OF_RESOURCES;
2308 }
2309 InitAddress = (UINTN) PhysicalAddress;
2310 //
2311 // then test if there is enough space for its RT code
2312 //
2313 RuntimeAddress = Private->OptionRom;
2314 if (RuntimeAddress + *RuntimeImageLength > PcdGet32 (PcdEndOpromShadowAddress)) {
2315 DEBUG ((EFI_D_ERROR, "return LegacyBiosInstallRom(%d): EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", __LINE__));
2316 gBS->FreePages (PhysicalAddress, EFI_SIZE_TO_PAGES (ImageSize));
2317 return EFI_OUT_OF_RESOURCES;
2318 }
2319 } else {
2320 // CSM16 3.0 meets PCI 2.x OpROM
2321 // CSM16 2.x meets PCI 2.x/3.0 OpROM
2322 // test if there is enough space for its INIT code
2323 //
2324 InitAddress = PCI_START_ADDRESS (Private->OptionRom);
2325 if (InitAddress + ImageSize > PcdGet32 (PcdEndOpromShadowAddress)) {
2326 DEBUG ((EFI_D_ERROR, "return LegacyBiosInstallRom(%d): EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", __LINE__));
2327 return EFI_OUT_OF_RESOURCES;
2328 }
2329
2330 RuntimeAddress = InitAddress;
2331 }
2332
2333 Private->LegacyRegion->UnLock (
2334 Private->LegacyRegion,
2335 0xE0000,
2336 0x20000,
2337 &Granularity
2338 );
2339
2340 Private->LegacyRegion->UnLock (
2341 Private->LegacyRegion,
2342 (UINT32) RuntimeAddress,
2343 (UINT32) ImageSize,
2344 &Granularity
2345 );
2346
2347 DEBUG ((EFI_D_INFO, " Shadowing OpROM init/runtime/isize = %x/%x/%x\n", InitAddress, RuntimeAddress, ImageSize));
2348
2349 CopyMem ((VOID *) InitAddress, RomImage, ImageSize);
2350
2351 //
2352 // Read the highest disk number "installed: and assume a new disk will
2353 // show up on the first drive past the current value.
2354 // There are several considerations here:
2355 // 1. Non-BBS compliant drives will change 40:75 but 16-bit CSM will undo
2356 // the change until boot selection time frame.
2357 // 2. BBS compliants drives will not change 40:75 until boot time.
2358 // 3. Onboard IDE controllers will change 40:75
2359 //
2360 LocalDiskStart = (UINT8) ((*(UINT8 *) ((UINTN) 0x475)) + 0x80);
2361 if ((Private->Disk4075 + 0x80) < LocalDiskStart) {
2362 //
2363 // Update table since onboard IDE drives found
2364 //
2365 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciSegment = 0xff;
2366 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciBus = 0xff;
2367 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciDevice = 0xff;
2368 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciFunction = 0xff;
2369 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].StartDriveNumber = (UINT8) (Private->Disk4075 + 0x80);
2370 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].EndDriveNumber = LocalDiskStart;
2371 Private->LegacyEfiHddTableIndex ++;
2372 Private->Disk4075 = (UINT8) (LocalDiskStart & 0x7f);
2373 Private->DiskEnd = LocalDiskStart;
2374 }
2375
2376 if (PciHandle != mVgaHandle) {
2377
2378 EnablePs2Keyboard ();
2379
2380 //
2381 // Store current mode settings since PrepareToScanRom may change mode.
2382 //
2383 VideoMode = *(UINT8 *) ((UINTN) 0x449);
2384 }
2385 //
2386 // Notify the platform that we are about to scan the ROM
2387 //
2388 Status = Private->LegacyBiosPlatform->PlatformHooks (
2389 Private->LegacyBiosPlatform,
2390 EfiPlatformHookPrepareToScanRom,
2391 0,
2392 PciHandle,
2393 &InitAddress,
2394 NULL,
2395 NULL
2396 );
2397
2398 //
2399 // If Status returned is EFI_UNSUPPORTED then abort due to platform
2400 // policy.
2401 //
2402 if (Status == EFI_UNSUPPORTED) {
2403 goto Done;
2404 }
2405
2406 //
2407 // Report corresponding status code
2408 //
2409 REPORT_STATUS_CODE (
2410 EFI_PROGRESS_CODE,
2411 (EFI_SOFTWARE_DXE_BS_DRIVER | EFI_SW_CSM_LEGACY_ROM_INIT)
2412 );
2413
2414 //
2415 // Generate number of ticks since midnight for BDA. Some OPROMs require
2416 // this. Place result in 40:6C-6F
2417 //
2418 gRT->GetTime (&BootTime, NULL);
2419 LocalTime = BootTime.Hour * 3600 + BootTime.Minute * 60 + BootTime.Second;
2420
2421 //
2422 // Multiply result by 18.2 for number of ticks since midnight.
2423 // Use 182/10 to avoid floating point math.
2424 //
2425 LocalTime = (LocalTime * 182) / 10;
2426 BdaPtr = (UINT32 *) ((UINTN) 0x46C);
2427 *BdaPtr = LocalTime;
2428
2429 //
2430 // Pass in handoff data
2431 //
2432 PciEnableStatus = EFI_UNSUPPORTED;
2433 ZeroMem (&Regs, sizeof (Regs));
2434 if (PciHandle != NULL) {
2435
2436 Status = gBS->HandleProtocol (
2437 PciHandle,
2438 &gEfiPciIoProtocolGuid,
2439 (VOID **) &PciIo
2440 );
2441 ASSERT_EFI_ERROR (Status);
2442
2443 //
2444 // Enable command register.
2445 //
2446 PciEnableStatus = PciIo->Attributes (
2447 PciIo,
2448 EfiPciIoAttributeOperationEnable,
2449 EFI_PCI_DEVICE_ENABLE,
2450 NULL
2451 );
2452
2453 PciIo->GetLocation (
2454 PciIo,
2455 &Segment,
2456 &Bus,
2457 &Device,
2458 &Function
2459 );
2460 DEBUG ((EFI_D_INFO, "Shadowing OpROM on the PCI device %x/%x/%x\n", Bus, Device, Function));
2461 }
2462
2463 mIgnoreBbsUpdateFlag = FALSE;
2464 Regs.X.AX = Legacy16DispatchOprom;
2465
2466 //
2467 // Generate DispatchOpRomTable data
2468 //
2469 Private->IntThunk->DispatchOpromTable.PnPInstallationCheckSegment = Private->Legacy16Table->PnPInstallationCheckSegment;
2470 Private->IntThunk->DispatchOpromTable.PnPInstallationCheckOffset = Private->Legacy16Table->PnPInstallationCheckOffset;
2471 Private->IntThunk->DispatchOpromTable.OpromSegment = (UINT16) (InitAddress >> 4);
2472 Private->IntThunk->DispatchOpromTable.PciBus = (UINT8) Bus;
2473 Private->IntThunk->DispatchOpromTable.PciDeviceFunction = (UINT8) ((Device << 3) | Function);
2474 Private->IntThunk->DispatchOpromTable.NumberBbsEntries = (UINT8) Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries;
2475 Private->IntThunk->DispatchOpromTable.BbsTablePointer = (UINT32) (UINTN) Private->BbsTablePtr;
2476 Private->IntThunk->DispatchOpromTable.RuntimeSegment = (UINT16)((OpromRevision < 3) ? 0xffff : (RuntimeAddress >> 4));
2477 TempData = (UINTN) &Private->IntThunk->DispatchOpromTable;
2478 Regs.X.ES = EFI_SEGMENT ((UINT32) TempData);
2479 Regs.X.BX = EFI_OFFSET ((UINT32) TempData);
2480 //
2481 // Skip dispatching ROM for those PCI devices that can not be enabled by PciIo->Attributes
2482 // Otherwise, it may cause the system to hang in some cases
2483 //
2484 if (!EFI_ERROR (PciEnableStatus)) {
2485 DEBUG ((EFI_D_INFO, " Legacy16DispatchOprom - %02x/%02x/%02x\n", Bus, Device, Function));
2486 Private->LegacyBios.FarCall86 (
2487 &Private->LegacyBios,
2488 Private->Legacy16CallSegment,
2489 Private->Legacy16CallOffset,
2490 &Regs,
2491 NULL,
2492 0
2493 );
2494 } else {
2495 Regs.X.BX = 0;
2496 }
2497
2498 if (Private->IntThunk->DispatchOpromTable.NumberBbsEntries != (UINT8) Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries) {
2499 Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries = (UINT8) Private->IntThunk->DispatchOpromTable.NumberBbsEntries;
2500 mIgnoreBbsUpdateFlag = TRUE;
2501 }
2502 //
2503 // Check if non-BBS compliant drives found
2504 //
2505 if (Regs.X.BX != 0) {
2506 LocalDiskEnd = (UINT8) (LocalDiskStart + Regs.H.BL);
2507 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciSegment = (UINT8) Segment;
2508 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciBus = (UINT8) Bus;
2509 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciDevice = (UINT8) Device;
2510 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciFunction = (UINT8) Function;
2511 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].StartDriveNumber = Private->DiskEnd;
2512 Private->DiskEnd = LocalDiskEnd;
2513 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].EndDriveNumber = Private->DiskEnd;
2514 Private->LegacyEfiHddTableIndex += 1;
2515 }
2516 //
2517 // Skip video mode set, if installing VGA
2518 //
2519 if (PciHandle != mVgaHandle) {
2520 //
2521 // Set mode settings since PrepareToScanRom may change mode
2522 //
2523 Regs.H.AH = 0x00;
2524 Regs.H.AL = VideoMode;
2525 Private->LegacyBios.Int86 (&Private->LegacyBios, 0x10, &Regs);
2526 }
2527 //
2528 // Regs.X.AX from the adapter initializion is ignored since some adapters
2529 // do not follow the standard of setting AX = 0 on success.
2530 //
2531 //
2532 // The ROM could have updated it's size so we need to read again.
2533 //
2534 *RuntimeImageLength = ((EFI_LEGACY_EXPANSION_ROM_HEADER *) (RuntimeAddress))->Size512 * 512;
2535 DEBUG ((EFI_D_INFO, " fsize = %x\n", *RuntimeImageLength));
2536
2537 //
2538 // If OpROM runs in 2.0 mode
2539 //
2540 if (PhysicalAddress == 0) {
2541 if (*RuntimeImageLength < ImageSize) {
2542 //
2543 // Make area from end of shadowed rom to end of original rom all ffs
2544 //
2545 gBS->SetMem ((VOID *) (InitAddress + *RuntimeImageLength), ImageSize - *RuntimeImageLength, 0xff);
2546 }
2547 }
2548
2549 LocalDiskEnd = (UINT8) ((*(UINT8 *) ((UINTN) 0x475)) + 0x80);
2550
2551 //
2552 // Allow platform to perform any required actions after the
2553 // OPROM has been initialized.
2554 //
2555 Status = Private->LegacyBiosPlatform->PlatformHooks (
2556 Private->LegacyBiosPlatform,
2557 EfiPlatformHookAfterRomInit,
2558 0,
2559 PciHandle,
2560 &RuntimeAddress,
2561 NULL,
2562 NULL
2563 );
2564 if (PciHandle != NULL) {
2565 //
2566 // If no PCI Handle then no header or Bevs.
2567 //
2568 if ((*RuntimeImageLength != 0) && (!mIgnoreBbsUpdateFlag)) {
2569 StartBbsIndex = Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries;
2570 TempData = RuntimeAddress;
2571 UpdateBevBcvTable (
2572 Private,
2573 (EFI_LEGACY_EXPANSION_ROM_HEADER *) TempData,
2574 PciIo
2575 );
2576 EndBbsIndex = Private->IntThunk->EfiToLegacy16BootTable.NumberBbsEntries;
2577 LocalDiskEnd = (UINT8) (LocalDiskStart + (UINT8) (EndBbsIndex - StartBbsIndex));
2578 if (LocalDiskEnd != LocalDiskStart) {
2579 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciSegment = (UINT8) Segment;
2580 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciBus = (UINT8) Bus;
2581 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciDevice = (UINT8) Device;
2582 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].PciFunction = (UINT8) Function;
2583 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].StartDriveNumber = Private->DiskEnd;
2584 Private->DiskEnd = LocalDiskEnd;
2585 Private->LegacyEfiHddTable[Private->LegacyEfiHddTableIndex].EndDriveNumber = Private->DiskEnd;
2586 Private->LegacyEfiHddTableIndex += 1;
2587 }
2588 }
2589 //
2590 // Mark PCI device as having a legacy BIOS ROM loaded.
2591 //
2592 RomShadow (
2593 PciHandle,
2594 (UINT32) RuntimeAddress,
2595 (UINT32) *RuntimeImageLength,
2596 LocalDiskStart,
2597 LocalDiskEnd
2598 );
2599 }
2600
2601 //
2602 // Stuff caller's OPTIONAL return parameters.
2603 //
2604 if (RomShadowAddress != NULL) {
2605 *RomShadowAddress = (VOID *) RuntimeAddress;
2606 }
2607
2608 if (DiskStart != NULL) {
2609 *DiskStart = LocalDiskStart;
2610 }
2611
2612 if (DiskEnd != NULL) {
2613 *DiskEnd = LocalDiskEnd;
2614 }
2615
2616 Private->OptionRom = (UINT32) (RuntimeAddress + *RuntimeImageLength);
2617
2618 Status = EFI_SUCCESS;
2619
2620 Done:
2621 if (PhysicalAddress != 0) {
2622 //
2623 // Free pages when OpROM is 3.0
2624 //
2625 gBS->FreePages (PhysicalAddress, EFI_SIZE_TO_PAGES (ImageSize));
2626 }
2627
2628 //
2629 // Insure all shadowed areas are locked
2630 //
2631 Private->LegacyRegion->Lock (
2632 Private->LegacyRegion,
2633 0xC0000,
2634 0x40000,
2635 &Granularity
2636 );
2637
2638 return Status;
2639 }
2640
2641 /**
2642 Load a legacy PC-AT OPROM on the PciHandle device. Return information
2643 about how many disks were added by the OPROM and the shadow address and
2644 size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C:
2645
2646 @param This Protocol instance pointer.
2647 @param PciHandle The PCI PC-AT OPROM from this devices ROM BAR will
2648 be loaded. This value is NULL if RomImage is
2649 non-NULL. This is the normal case.
2650 @param RomImage A PCI PC-AT ROM image. This argument is non-NULL
2651 if there is no hardware associated with the ROM
2652 and thus no PciHandle, otherwise is must be NULL.
2653 Example is PXE base code.
2654 @param Flags Indicates if ROM found and if PC-AT.
2655 @param DiskStart Disk number of first device hooked by the ROM. If
2656 DiskStart is the same as DiskEnd no disked were
2657 hooked.
2658 @param DiskEnd Disk number of the last device hooked by the ROM.
2659 @param RomShadowAddress Shadow address of PC-AT ROM
2660 @param RomShadowedSize Size of RomShadowAddress in bytes
2661
2662 @retval EFI_SUCCESS Legacy ROM loaded for this device
2663 @retval EFI_INVALID_PARAMETER PciHandle not found
2664 @retval EFI_UNSUPPORTED There is no PCI ROM in the ROM BAR or no onboard
2665 ROM
2666
2667 **/
2668 EFI_STATUS
2669 EFIAPI
2670 LegacyBiosInstallPciRom (
2671 IN EFI_LEGACY_BIOS_PROTOCOL * This,
2672 IN EFI_HANDLE PciHandle,
2673 IN VOID **RomImage,
2674 OUT UINTN *Flags,
2675 OUT UINT8 *DiskStart, OPTIONAL
2676 OUT UINT8 *DiskEnd, OPTIONAL
2677 OUT VOID **RomShadowAddress, OPTIONAL
2678 OUT UINT32 *RomShadowedSize OPTIONAL
2679 )
2680 {
2681 EFI_STATUS Status;
2682 LEGACY_BIOS_INSTANCE *Private;
2683 VOID *LocalRomImage;
2684 UINTN ImageSize;
2685 UINTN RuntimeImageLength;
2686 EFI_PCI_IO_PROTOCOL *PciIo;
2687 PCI_TYPE01 PciConfigHeader;
2688 UINTN HandleCount;
2689 EFI_HANDLE *HandleBuffer;
2690 UINTN PciSegment;
2691 UINTN PciBus;
2692 UINTN PciDevice;
2693 UINTN PciFunction;
2694 UINTN LastBus;
2695 UINTN Index;
2696 UINT8 OpromRevision;
2697 UINT32 Granularity;
2698 PCI_3_0_DATA_STRUCTURE *Pcir;
2699
2700 OpromRevision = 0;
2701
2702 Private = LEGACY_BIOS_INSTANCE_FROM_THIS (This);
2703 if (Private->Legacy16Table->LastPciBus == 0) {
2704 //
2705 // Get last bus number if not already found
2706 //
2707 Status = gBS->LocateHandleBuffer (
2708 ByProtocol,
2709 &gEfiPciIoProtocolGuid,
2710 NULL,
2711 &HandleCount,
2712 &HandleBuffer
2713 );
2714
2715 LastBus = 0;
2716 for (Index = 0; Index < HandleCount; Index++) {
2717 Status = gBS->HandleProtocol (
2718 HandleBuffer[Index],
2719 &gEfiPciIoProtocolGuid,
2720 (VOID **) &PciIo
2721 );
2722 if (EFI_ERROR (Status)) {
2723 continue;
2724 }
2725
2726 Status = PciIo->GetLocation (
2727 PciIo,
2728 &PciSegment,
2729 &PciBus,
2730 &PciDevice,
2731 &PciFunction
2732 );
2733 if (PciBus > LastBus) {
2734 LastBus = PciBus;
2735 }
2736 }
2737
2738 Private->LegacyRegion->UnLock (
2739 Private->LegacyRegion,
2740 0xE0000,
2741 0x20000,
2742 &Granularity
2743 );
2744 Private->Legacy16Table->LastPciBus = (UINT8) LastBus;
2745 Private->LegacyRegion->Lock (
2746 Private->LegacyRegion,
2747 0xE0000,
2748 0x20000,
2749 &Granularity
2750 );
2751 }
2752
2753 *Flags = 0;
2754 if ((PciHandle != NULL) && (RomImage == NULL)) {
2755 //
2756 // If PciHandle has OpRom to Execute
2757 // and OpRom are all associated with Hardware
2758 //
2759 Status = gBS->HandleProtocol (
2760 PciHandle,
2761 &gEfiPciIoProtocolGuid,
2762 (VOID **) &PciIo
2763 );
2764
2765 if (!EFI_ERROR (Status)) {
2766 PciIo->Pci.Read (
2767 PciIo,
2768 EfiPciIoWidthUint32,
2769 0,
2770 sizeof (PciConfigHeader) / sizeof (UINT32),
2771 &PciConfigHeader
2772 );
2773
2774 //
2775 // if video installed & OPROM is video return
2776 //
2777 if (
2778 (
2779 ((PciConfigHeader.Hdr.ClassCode[2] == PCI_CLASS_OLD) &&
2780 (PciConfigHeader.Hdr.ClassCode[1] == PCI_CLASS_OLD_VGA))
2781 ||
2782 ((PciConfigHeader.Hdr.ClassCode[2] == PCI_CLASS_DISPLAY) &&
2783 (PciConfigHeader.Hdr.ClassCode[1] == PCI_CLASS_DISPLAY_VGA))
2784 )
2785 &&
2786 (!Private->VgaInstalled)
2787 ) {
2788 mVgaInstallationInProgress = TRUE;
2789
2790 //
2791 // return EFI_UNSUPPORTED;
2792 //
2793 }
2794 }
2795 //
2796 // To run any legacy image, the VGA needs to be installed first.
2797 // if installing the video, then don't need the thunk as already installed.
2798 //
2799 Status = Private->LegacyBiosPlatform->GetPlatformHandle (
2800 Private->LegacyBiosPlatform,
2801 EfiGetPlatformVgaHandle,
2802 0,
2803 &HandleBuffer,
2804 &HandleCount,
2805 NULL
2806 );
2807
2808 if (!EFI_ERROR (Status)) {
2809 mVgaHandle = HandleBuffer[0];
2810 if ((!Private->VgaInstalled) && (PciHandle != mVgaHandle)) {
2811 //
2812 // A return status of EFI_NOT_FOUND is considered valid (No EFI
2813 // driver is controlling video.
2814 //
2815 mVgaInstallationInProgress = TRUE;
2816 Status = LegacyBiosInstallVgaRom (Private);
2817 if (EFI_ERROR (Status)) {
2818 if (Status != EFI_NOT_FOUND) {
2819 mVgaInstallationInProgress = FALSE;
2820 return Status;
2821 }
2822 } else {
2823 mVgaInstallationInProgress = FALSE;
2824 }
2825 }
2826 }
2827 //
2828 // See if the option ROM for PciHandle has already been executed
2829 //
2830 Status = IsLegacyRom (PciHandle);
2831
2832 if (!EFI_ERROR (Status)) {
2833 mVgaInstallationInProgress = FALSE;
2834 GetShadowedRomParameters (
2835 PciHandle,
2836 DiskStart,
2837 DiskEnd,
2838 RomShadowAddress,
2839 (UINTN *) RomShadowedSize
2840 );
2841 return EFI_SUCCESS;
2842 }
2843
2844 Status = LegacyBiosCheckPciRomEx (
2845 &Private->LegacyBios,
2846 PciHandle,
2847 &LocalRomImage,
2848 &ImageSize,
2849 &RuntimeImageLength,
2850 Flags,
2851 &OpromRevision,
2852 NULL
2853 );
2854 if (EFI_ERROR (Status)) {
2855 //
2856 // There is no PCI ROM in the ROM BAR or no onboard ROM
2857 //
2858 mVgaInstallationInProgress = FALSE;
2859 return EFI_UNSUPPORTED;
2860 }
2861 } else {
2862 if ((RomImage == NULL) || (*RomImage == NULL)) {
2863 //
2864 // If PciHandle is NULL, and no OpRom is to be associated
2865 //
2866 mVgaInstallationInProgress = FALSE;
2867 return EFI_UNSUPPORTED;
2868 }
2869
2870 if (!Private->VgaInstalled) {
2871 //
2872 // A return status of EFI_NOT_FOUND is considered valid (No EFI
2873 // driver is controlling video.
2874 //
2875 mVgaInstallationInProgress = TRUE;
2876 Status = LegacyBiosInstallVgaRom (Private);
2877 if (EFI_ERROR (Status)) {
2878 if (Status != EFI_NOT_FOUND) {
2879 mVgaInstallationInProgress = FALSE;
2880 return Status;
2881 }
2882 } else {
2883 mVgaInstallationInProgress = FALSE;
2884 }
2885 }
2886
2887 LocalRomImage = *RomImage;
2888 if (((PCI_EXPANSION_ROM_HEADER *) LocalRomImage)->Signature != PCI_EXPANSION_ROM_HEADER_SIGNATURE ||
2889 ((PCI_EXPANSION_ROM_HEADER *) LocalRomImage)->PcirOffset == 0 ||
2890 (((PCI_EXPANSION_ROM_HEADER *) LocalRomImage)->PcirOffset & 3 ) != 0) {
2891 mVgaInstallationInProgress = FALSE;
2892 return EFI_UNSUPPORTED;
2893 }
2894
2895 Pcir = (PCI_3_0_DATA_STRUCTURE *)
2896 ((UINT8 *) LocalRomImage + ((PCI_EXPANSION_ROM_HEADER *) LocalRomImage)->PcirOffset);
2897
2898 if (Pcir->Signature != PCI_DATA_STRUCTURE_SIGNATURE) {
2899 mVgaInstallationInProgress = FALSE;
2900 return EFI_UNSUPPORTED;
2901 }
2902
2903 ImageSize = Pcir->ImageLength * 512;
2904 if (Pcir->Length >= 0x1C) {
2905 OpromRevision = Pcir->Revision;
2906 } else {
2907 OpromRevision = 0;
2908 }
2909 if (Pcir->Revision < 3) {
2910 RuntimeImageLength = 0;
2911 } else {
2912 RuntimeImageLength = Pcir->MaxRuntimeImageLength * 512;
2913 }
2914 }
2915 //
2916 // Shadow and initialize the OpROM.
2917 //
2918 ASSERT (Private->TraceIndex < 0x200);
2919 Private->Trace[Private->TraceIndex] = LEGACY_PCI_TRACE_000;
2920 Private->TraceIndex ++;
2921 Private->TraceIndex = (UINT16) (Private->TraceIndex % 0x200);
2922 Status = LegacyBiosInstallRom (
2923 This,
2924 Private,
2925 PciHandle,
2926 OpromRevision,
2927 LocalRomImage,
2928 ImageSize,
2929 &RuntimeImageLength,
2930 DiskStart,
2931 DiskEnd,
2932 RomShadowAddress
2933 );
2934 if (RomShadowedSize != NULL) {
2935 *RomShadowedSize = (UINT32) RuntimeImageLength;
2936 }
2937
2938 mVgaInstallationInProgress = FALSE;
2939 return Status;
2940 }
2941
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