3 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions
7 of the BSD License which accompanies this distribution. The
8 full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include "LegacyBiosInterface.h"
17 #include <IndustryStandard/Pci30.h>
19 #define PCI_START_ADDRESS(x) (((x) + 0x7ff) & ~0x7ff)
21 #define MAX_BRIDGE_INDEX 0x20
32 #define ROM_MAX_ENTRIES 24
33 BRIDGE_TABLE Bridges
[MAX_BRIDGE_INDEX
];
34 UINTN SortedBridgeIndex
[MAX_BRIDGE_INDEX
];
35 UINTN NumberOfBridges
;
36 LEGACY_PNP_EXPANSION_HEADER
*mBasePnpPtr
;
37 UINT16 mBbsRomSegment
;
39 EFI_HANDLE mVgaHandle
;
40 BOOLEAN mIgnoreBbsUpdateFlag
;
41 BOOLEAN mVgaInstallationInProgress
= FALSE
;
42 UINT32 mRomCount
= 0x00;
43 ROM_INSTANCE_ENTRY mRomEntry
[ROM_MAX_ENTRIES
];
47 Query shadowed legacy ROM parameters registered by RomShadow() previously.
49 @param PciHandle PCI device whos ROM has been shadowed
50 @param DiskStart DiskStart value from EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom
51 @param DiskEnd DiskEnd value from EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom
52 @param RomShadowAddress Address where ROM was shadowed
53 @param ShadowedSize Runtime size of ROM
55 @retval EFI_SUCCESS Query Logging successful.
56 @retval EFI_NOT_FOUND No logged data found about PciHandle.
60 GetShadowedRomParameters (
61 IN EFI_HANDLE PciHandle
,
62 OUT UINT8
*DiskStart
, OPTIONAL
63 OUT UINT8
*DiskEnd
, OPTIONAL
64 OUT VOID
**RomShadowAddress
, OPTIONAL
65 OUT UINTN
*ShadowedSize OPTIONAL
69 EFI_PCI_IO_PROTOCOL
*PciIo
;
77 // Get the PCI I/O Protocol on PciHandle
79 Status
= gBS
->HandleProtocol (
81 &gEfiPciIoProtocolGuid
,
84 if (EFI_ERROR (Status
)) {
89 // Get the location of the PCI device
99 for(Index
= 0; Index
< mRomCount
; Index
++) {
100 if ((mRomEntry
[Index
].PciSegment
== PciSegment
) &&
101 (mRomEntry
[Index
].PciBus
== PciBus
) &&
102 (mRomEntry
[Index
].PciDevice
== PciDevice
) &&
103 (mRomEntry
[Index
].PciFunction
== PciFunction
)) {
108 if (Index
== mRomCount
) {
109 return EFI_NOT_FOUND
;
112 if (DiskStart
!= NULL
) {
113 *DiskStart
= mRomEntry
[Index
].DiskStart
;
116 if (DiskEnd
!= NULL
) {
117 *DiskEnd
= mRomEntry
[Index
].DiskEnd
;
120 if (RomShadowAddress
!= NULL
) {
121 *RomShadowAddress
= (VOID
*)(UINTN
)mRomEntry
[Index
].ShadowAddress
;
124 if (ShadowedSize
!= NULL
) {
125 *ShadowedSize
= mRomEntry
[Index
].ShadowedSize
;
132 Every legacy ROM that is shadowed by the Legacy BIOS driver will be
133 registered into this API so that the policy code can know what has
136 @param PciHandle PCI device whos ROM is being shadowed
137 @param ShadowAddress Address that ROM was shadowed
138 @param ShadowedSize Runtime size of ROM
139 @param DiskStart DiskStart value from
140 EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom
141 @param DiskEnd DiskEnd value from
142 EFI_LEGACY_BIOS_PROTOCOL.InstallPciRom
144 @retval EFI_SUCCESS Logging successful.
145 @retval EFI_OUT_OF_RESOURCES No remaining room for registering another option
151 IN EFI_HANDLE PciHandle
,
152 IN UINT32 ShadowAddress
,
153 IN UINT32 ShadowedSize
,
159 EFI_PCI_IO_PROTOCOL
*PciIo
;
162 // See if there is room to register another option ROM
164 if (mRomCount
>= ROM_MAX_ENTRIES
) {
165 return EFI_OUT_OF_RESOURCES
;
168 // Get the PCI I/O Protocol on PciHandle
170 Status
= gBS
->HandleProtocol (
172 &gEfiPciIoProtocolGuid
,
175 if (EFI_ERROR (Status
)) {
179 // Get the location of the PCI device
183 &mRomEntry
[mRomCount
].PciSegment
,
184 &mRomEntry
[mRomCount
].PciBus
,
185 &mRomEntry
[mRomCount
].PciDevice
,
186 &mRomEntry
[mRomCount
].PciFunction
188 mRomEntry
[mRomCount
].ShadowAddress
= ShadowAddress
;
189 mRomEntry
[mRomCount
].ShadowedSize
= ShadowedSize
;
190 mRomEntry
[mRomCount
].DiskStart
= DiskStart
;
191 mRomEntry
[mRomCount
].DiskEnd
= DiskEnd
;
200 Return EFI_SUCCESS if PciHandle has had a legacy BIOS ROM shadowed. This
201 information represents every call to RomShadow ()
203 @param PciHandle PCI device to get status for
205 @retval EFI_SUCCESS Legacy ROM loaded for this device
206 @retval EFI_NOT_FOUND No Legacy ROM loaded for this device
211 IN EFI_HANDLE PciHandle
215 EFI_PCI_IO_PROTOCOL
*PciIo
;
223 // Get the PCI I/O Protocol on PciHandle
225 Status
= gBS
->HandleProtocol (
227 &gEfiPciIoProtocolGuid
,
230 if (EFI_ERROR (Status
)) {
234 // Get the location of the PCI device
245 // See if the option ROM from PciHandle has been previously posted
247 for (Index
= 0; Index
< mRomCount
; Index
++) {
248 if (mRomEntry
[Index
].PciSegment
== Segment
&&
249 mRomEntry
[Index
].PciBus
== Bus
&&
250 mRomEntry
[Index
].PciDevice
== Device
&&
251 mRomEntry
[Index
].PciFunction
== Function
257 return EFI_NOT_FOUND
;
261 Find the PC-AT ROM Image in the raw PCI Option ROM. Also return the
262 related information from the header.
264 @param Csm16Revision The PCI interface version of underlying CSM16
265 @param VendorId Vendor ID of the PCI device
266 @param DeviceId Device ID of the PCI device
267 @param Rom On input pointing to beginning of the raw PCI OpROM
268 On output pointing to the first legacy PCI OpROM
269 @param ImageSize On input is the size of Raw PCI Rom
270 On output is the size of the first legacy PCI ROM
271 @param MaxRuntimeImageLength The max runtime image length only valid if OpRomRevision >= 3
272 @param OpRomRevision Revision of the PCI Rom
273 @param ConfigUtilityCodeHeader Pointer to Configuration Utility Code Header
275 @retval EFI_SUCCESS Successfully find the legacy PCI ROM
276 @retval EFI_NOT_FOUND Failed to find the legacy PCI ROM
281 IN UINT16 Csm16Revision
,
285 IN OUT UINTN
*ImageSize
,
286 OUT UINTN
*MaxRuntimeImageLength
, OPTIONAL
287 OUT UINT8
*OpRomRevision
, OPTIONAL
288 OUT VOID
**ConfigUtilityCodeHeader OPTIONAL
292 UINT16
*DeviceIdList
;
293 EFI_PCI_ROM_HEADER RomHeader
;
294 PCI_3_0_DATA_STRUCTURE
*Pcir
;
299 if (*ImageSize
< sizeof (EFI_PCI_ROM_HEADER
)) {
300 return EFI_NOT_FOUND
;
305 RomHeader
.Raw
= *Rom
;
306 while (RomHeader
.Generic
->Signature
== PCI_EXPANSION_ROM_HEADER_SIGNATURE
) {
308 RomHeader
.Raw
- (UINT8
*) *Rom
+ RomHeader
.Generic
->PcirOffset
+ sizeof (PCI_DATA_STRUCTURE
)
310 return EFI_NOT_FOUND
;
313 Pcir
= (PCI_3_0_DATA_STRUCTURE
*) (RomHeader
.Raw
+ RomHeader
.Generic
->PcirOffset
);
315 if (Pcir
->CodeType
== PCI_CODE_TYPE_PCAT_IMAGE
) {
317 if (Pcir
->VendorId
== VendorId
) {
318 if (Pcir
->DeviceId
== DeviceId
) {
320 } else if ((Pcir
->Revision
>= 3) && (Pcir
->DeviceListOffset
!= 0)) {
321 DeviceIdList
= (UINT16
*)(((UINT8
*) Pcir
) + Pcir
->DeviceListOffset
);
323 // Checking the device list
325 while (*DeviceIdList
!= 0) {
326 if (*DeviceIdList
== DeviceId
) {
336 if (Csm16Revision
>= 0x0300) {
340 if (Pcir
->Revision
>= 3) {
342 // case 1.1: meets OpRom 3.0
345 BestImage
= RomHeader
.Raw
;
349 // case 1.2: meets OpRom 2.x
350 // Store it and try to find the OpRom 3.0
352 BackupImage
= RomHeader
.Raw
;
358 if (Pcir
->Revision
>= 3) {
360 // case 2.1: meets OpRom 3.0
361 // Store it and try to find the OpRom 2.x
363 BackupImage
= RomHeader
.Raw
;
366 // case 2.2: meets OpRom 2.x
369 BestImage
= RomHeader
.Raw
;
374 DEBUG ((EFI_D_ERROR
, "GetPciLegacyRom - OpRom not match (%04x-%04x)\n", (UINTN
)VendorId
, (UINTN
)DeviceId
));
378 if ((Pcir
->Indicator
& 0x80) == 0x80) {
381 RomHeader
.Raw
+= 512 * Pcir
->ImageLength
;
385 if (BestImage
== NULL
) {
386 if (BackupImage
== NULL
) {
387 return EFI_NOT_FOUND
;
390 // The versions of CSM16 and OpRom don't match exactly
392 BestImage
= BackupImage
;
394 RomHeader
.Raw
= BestImage
;
395 Pcir
= (PCI_3_0_DATA_STRUCTURE
*) (RomHeader
.Raw
+ RomHeader
.Generic
->PcirOffset
);
397 *ImageSize
= Pcir
->ImageLength
* 512;
399 if (MaxRuntimeImageLength
!= NULL
) {
400 if (Pcir
->Revision
< 3) {
401 *MaxRuntimeImageLength
= 0;
403 *MaxRuntimeImageLength
= Pcir
->MaxRuntimeImageLength
* 512;
407 if (OpRomRevision
!= NULL
) {
409 // Optional return PCI Data Structure revision
411 if (Pcir
->Length
>= 0x1C) {
412 *OpRomRevision
= Pcir
->Revision
;
418 if (ConfigUtilityCodeHeader
!= NULL
) {
420 // Optional return ConfigUtilityCodeHeaderOffset supported by the PC-AT ROM
422 if ((Pcir
->Revision
< 3) || (Pcir
->ConfigUtilityCodeHeaderOffset
== 0)) {
423 *ConfigUtilityCodeHeader
= NULL
;
425 *ConfigUtilityCodeHeader
= RomHeader
.Raw
+ Pcir
->ConfigUtilityCodeHeaderOffset
;
433 Build a table of bridge info for PIRQ translation.
435 @param RoutingTable RoutingTable obtained from Platform.
436 @param RoutingTableEntries Number of RoutingTable entries.
438 @retval EFI_SUCCESS New Subordinate bus.
439 @retval EFI_NOT_FOUND No more Subordinate busses.
444 IN EFI_LEGACY_IRQ_ROUTING_ENTRY
*RoutingTable
,
445 IN UINTN RoutingTableEntries
450 EFI_HANDLE
*HandleBuffer
;
454 EFI_PCI_IO_PROTOCOL
*PciIo
;
455 PCI_TYPE01 PciConfigHeader
;
456 BRIDGE_TABLE SlotBridges
[MAX_BRIDGE_INDEX
];
457 UINTN SlotBridgeIndex
;
460 SlotBridgeIndex
= 0x00;
463 // Assumption is table is built from low bus to high bus numbers.
465 Status
= gBS
->LocateHandleBuffer (
467 &gEfiPciIoProtocolGuid
,
472 if (EFI_ERROR (Status
)) {
473 return EFI_NOT_FOUND
;
475 for (Index
= 0; Index
< HandleCount
; Index
++) {
476 Status
= gBS
->HandleProtocol (
478 &gEfiPciIoProtocolGuid
,
481 if (EFI_ERROR (Status
)) {
489 sizeof (PciConfigHeader
) / sizeof (UINT32
),
493 if (IS_PCI_P2P (&PciConfigHeader
) && (BridgeIndex
< MAX_BRIDGE_INDEX
)) {
496 &Bridges
[BridgeIndex
].PciSegment
,
497 &Bridges
[BridgeIndex
].PciBus
,
498 &Bridges
[BridgeIndex
].PciDevice
,
499 &Bridges
[BridgeIndex
].PciFunction
502 Bridges
[BridgeIndex
].PrimaryBus
= PciConfigHeader
.Bridge
.PrimaryBus
;
504 Bridges
[BridgeIndex
].SecondaryBus
= PciConfigHeader
.Bridge
.SecondaryBus
;
506 Bridges
[BridgeIndex
].SubordinateBus
= PciConfigHeader
.Bridge
.SubordinateBus
;
508 for (Index1
= 0; Index1
< RoutingTableEntries
; Index1
++){
510 // Test whether we have found the Bridge in the slot, must be the one that directly interfaced to the board
511 // Once we find one, store it in the SlotBridges[]
513 if ((RoutingTable
[Index1
].Slot
!= 0) && (Bridges
[BridgeIndex
].PrimaryBus
== RoutingTable
[Index1
].Bus
)
514 && ((Bridges
[BridgeIndex
].PciDevice
<< 3) == RoutingTable
[Index1
].Device
)) {
515 CopyMem (&SlotBridges
[SlotBridgeIndex
], &Bridges
[BridgeIndex
], sizeof (BRIDGE_TABLE
));
527 // Pack up Bridges by removing those useless ones
529 for (Index
= 0; Index
< BridgeIndex
;){
530 for (Index1
= 0; Index1
< SlotBridgeIndex
; Index1
++) {
531 if (((Bridges
[Index
].PciBus
== SlotBridges
[Index1
].PrimaryBus
) && (Bridges
[Index
].PciDevice
== SlotBridges
[Index1
].PciDevice
)) ||
532 ((Bridges
[Index
].PciBus
>= SlotBridges
[Index1
].SecondaryBus
) && (Bridges
[Index
].PciBus
<= SlotBridges
[Index1
].SubordinateBus
))) {
534 // We have found one that meets our criteria
542 // This one doesn't meet criteria, pack it
544 if (Index1
>= SlotBridgeIndex
) {
545 for (Index1
= Index
; BridgeIndex
> 1 && Index1
< BridgeIndex
- 1 ; Index1
++) {
546 CopyMem (&Bridges
[Index1
], &Bridges
[Index1
+ 1], sizeof (BRIDGE_TABLE
));
553 NumberOfBridges
= BridgeIndex
;
556 // Sort bridges low to high by Secondary bus followed by subordinate bus
558 if (NumberOfBridges
> 1) {
561 SortedBridgeIndex
[Index
] = Index
;
563 } while (Index
< NumberOfBridges
);
565 for (Index
= 0; Index
< NumberOfBridges
- 1; Index
++) {
566 for (Index1
= Index
+ 1; Index1
< NumberOfBridges
; Index1
++) {
567 if (Bridges
[Index
].SecondaryBus
> Bridges
[Index1
].SecondaryBus
) {
568 SortedBridgeIndex
[Index
] = Index1
;
569 SortedBridgeIndex
[Index1
] = Index
;
572 if ((Bridges
[Index
].SecondaryBus
== Bridges
[Index1
].SecondaryBus
) &&
573 (Bridges
[Index
].SubordinateBus
> Bridges
[Index1
].SubordinateBus
)
575 SortedBridgeIndex
[Index
] = Index1
;
576 SortedBridgeIndex
[Index1
] = Index
;
581 FreePool (HandleBuffer
);
587 Find base Bridge for device.
589 @param Private Legacy BIOS Instance data
590 @param PciBus Input = Bus of device.
591 @param PciDevice Input = Device.
592 @param RoutingTable The platform specific routing table
593 @param RoutingTableEntries Number of entries in table
595 @retval EFI_SUCCESS At base bus.
596 @retval EFI_NOT_FOUND Behind a bridge.
601 IN LEGACY_BIOS_INSTANCE
*Private
,
604 IN EFI_LEGACY_IRQ_ROUTING_ENTRY
*RoutingTable
,
605 IN UINTN RoutingTableEntries
609 for (Index
= 0; Index
< RoutingTableEntries
; Index
++) {
610 if ((RoutingTable
[Index
].Bus
== PciBus
) && (RoutingTable
[Index
].Device
== (PciDevice
<< 3))) {
615 return EFI_NOT_FOUND
;
619 Translate PIRQ through busses
621 @param Private Legacy BIOS Instance data
622 @param PciBus Input = Bus of device. Output = Translated Bus
623 @param PciDevice Input = Device. Output = Translated Device
624 @param PciFunction Input = Function. Output = Translated Function
625 @param PirqIndex Input = Original PIRQ index. If single function
626 device then 0, otherwise 0-3.
627 Output = Translated Index
629 @retval EFI_SUCCESS Pirq successfully translated.
630 @retval EFI_NOT_FOUND The device is not behind any known bridge.
635 IN LEGACY_BIOS_INSTANCE
*Private
,
636 IN OUT UINTN
*PciBus
,
637 IN OUT UINTN
*PciDevice
,
638 IN OUT UINTN
*PciFunction
,
639 IN OUT UINT8
*PirqIndex
643 This routine traverses the PCI busses from base slot
644 and translates the PIRQ register to the appropriate one.
648 Bus 0, Device 1 is PCI-PCI bridge that all PCI slots reside on.
651 Subordinate bus # is highest bus # behind this bus
652 Bus 1, Device 0 is Slot 0 and is not a bridge.
653 Bus 1, Device 1 is Slot 1 and is a bridge.
654 Slot PIRQ routing is A,B,C,D.
657 Subordinate bus # = 5
658 Bus 2, Device 6 is a bridge. It has no bridges behind it.
661 Subordinate bus # = 3
662 Bridge PIRQ routing is C,D,A,B
663 Bus 2, Device 7 is a bridge. It has 1 bridge behind it.
665 Secondary bus = 4 Device 6 takes bus 2.
667 Bridge PIRQ routing is D,A,B,C
668 Bus 4, Device 2 is a bridge. It has no bridges behind it.
672 Bridge PIRQ routing is B,C,D,A
673 Bus 5, Device 1 is to be programmed.
674 Device PIRQ routing is C,D,A,B
677 Search busses starting from slot bus for final bus >= Secondary bus and
678 final bus <= Suborninate bus. Assumption is bus entries increase in bus
680 Starting PIRQ is A,B,C,D.
681 Bus 2, Device 7 satisfies search criteria. Rotate (A,B,C,D) left by device
682 7 modulo 4 giving (D,A,B,C).
683 Bus 4, Device 2 satisfies search criteria. Rotate (D,A,B,C) left by 2 giving
685 No other busses match criteria. Device to be programmed is Bus 5, Device 1.
686 Rotate (B,C,D,A) by 1 giving C,D,A,B. Translated PIRQ is C.
694 UINT8 LocalPirqIndex
;
695 BOOLEAN BaseIndexFlag
;
698 BaseIndexFlag
= FALSE
;
701 LocalPirqIndex
= *PirqIndex
;
703 LocalDevice
= *PciDevice
;
705 BaseDevice
= *PciDevice
;
706 BaseFunction
= *PciFunction
;
709 // LocalPirqIndex list PIRQs in rotated fashion
716 for (BridgeIndex
= 0; BridgeIndex
< NumberOfBridges
; BridgeIndex
++) {
717 SBridgeIndex
= SortedBridgeIndex
[BridgeIndex
];
719 // Check if device behind this bridge
721 if ((LocalBus
>= Bridges
[SBridgeIndex
].SecondaryBus
) && (LocalBus
<= Bridges
[SBridgeIndex
].SubordinateBus
)) {
723 // If BaseIndexFlag = FALSE then have found base bridge, i.e
724 // bridge in slot. Save info for use by IRQ routing table.
726 if (!BaseIndexFlag
) {
727 BaseBus
= Bridges
[SBridgeIndex
].PciBus
;
728 BaseDevice
= Bridges
[SBridgeIndex
].PciDevice
;
729 BaseFunction
= Bridges
[SBridgeIndex
].PciFunction
;
730 BaseIndexFlag
= TRUE
;
732 LocalPirqIndex
= (UINT8
) ((LocalPirqIndex
+ (UINT8
)Bridges
[SBridgeIndex
].PciDevice
)%4);
736 // Check if at device. If not get new PCI location & PIRQ
738 if (Bridges
[SBridgeIndex
].SecondaryBus
== (UINT8
) LocalBus
) {
742 LocalPirqIndex
= (UINT8
) ((LocalPirqIndex
+ (UINT8
) (LocalDevice
)) % 4);
749 // In case we fail to find the Bridge just above us, this is some potential error and we want to warn the user
751 if(BridgeIndex
>= NumberOfBridges
){
752 DEBUG ((EFI_D_ERROR
, "Cannot Find IRQ Routing for Bus %d, Device %d, Function %d\n", *PciBus
, *PciDevice
, *PciFunction
));
755 *PirqIndex
= LocalPirqIndex
;
757 *PciDevice
= BaseDevice
;
758 *PciFunction
= BaseFunction
;
765 Copy the $PIR table as required.
767 @param Private Legacy BIOS Instance data
768 @param RoutingTable Pointer to IRQ routing table
769 @param RoutingTableEntries IRQ routing table entries
770 @param PirqTable Pointer to $PIR table
771 @param PirqTableSize Length of table
776 IN LEGACY_BIOS_INSTANCE
*Private
,
777 IN EFI_LEGACY_IRQ_ROUTING_ENTRY
*RoutingTable
,
778 IN UINTN RoutingTableEntries
,
779 IN EFI_LEGACY_PIRQ_TABLE_HEADER
*PirqTable
,
780 IN UINTN PirqTableSize
783 EFI_IA32_REGISTER_SET Regs
;
787 // Copy $PIR table, if it exists.
789 if (PirqTable
!= NULL
) {
790 Private
->LegacyRegion
->UnLock (
791 Private
->LegacyRegion
,
797 Private
->InternalIrqRoutingTable
= RoutingTable
;
798 Private
->NumberIrqRoutingEntries
= (UINT16
) (RoutingTableEntries
);
799 ZeroMem (&Regs
, sizeof (EFI_IA32_REGISTER_SET
));
801 Regs
.X
.AX
= Legacy16GetTableAddress
;
802 Regs
.X
.CX
= (UINT16
) PirqTableSize
;
804 // Allocate at F segment according to PCI IRQ Routing Table Specification
806 Regs
.X
.BX
= (UINT16
) 0x1;
808 // 16-byte boundary alignment requirement according to
809 // PCI IRQ Routing Table Specification
812 Private
->LegacyBios
.FarCall86 (
813 &Private
->LegacyBios
,
814 Private
->Legacy16CallSegment
,
815 Private
->Legacy16CallOffset
,
821 Private
->Legacy16Table
->IrqRoutingTablePointer
= (UINT32
) (Regs
.X
.DS
* 16 + Regs
.X
.BX
);
822 if (Regs
.X
.AX
!= 0) {
823 DEBUG ((EFI_D_ERROR
, "PIRQ table length insufficient - %x\n", PirqTableSize
));
825 DEBUG ((EFI_D_INFO
, "PIRQ table in legacy region - %x\n", Private
->Legacy16Table
->IrqRoutingTablePointer
));
826 Private
->Legacy16Table
->IrqRoutingTableLength
= (UINT32
)PirqTableSize
;
828 (VOID
*) (UINTN
)Private
->Legacy16Table
->IrqRoutingTablePointer
,
834 Private
->Cpu
->FlushDataCache (Private
->Cpu
, 0xE0000, 0x20000, EfiCpuFlushTypeWriteBackInvalidate
);
835 Private
->LegacyRegion
->Lock (
836 Private
->LegacyRegion
,
843 Private
->PciInterruptLine
= TRUE
;
848 Dump EFI_LEGACY_INSTALL_PCI_HANDLER structure information.
850 @param PciHandle The pointer to EFI_LEGACY_INSTALL_PCI_HANDLER structure
855 IN EFI_LEGACY_INSTALL_PCI_HANDLER
*PciHandle
858 DEBUG ((EFI_D_INFO
, "PciBus - %02x\n", (UINTN
)PciHandle
->PciBus
));
859 DEBUG ((EFI_D_INFO
, "PciDeviceFun - %02x\n", (UINTN
)PciHandle
->PciDeviceFun
));
860 DEBUG ((EFI_D_INFO
, "PciSegment - %02x\n", (UINTN
)PciHandle
->PciSegment
));
861 DEBUG ((EFI_D_INFO
, "PciClass - %02x\n", (UINTN
)PciHandle
->PciClass
));
862 DEBUG ((EFI_D_INFO
, "PciSubclass - %02x\n", (UINTN
)PciHandle
->PciSubclass
));
863 DEBUG ((EFI_D_INFO
, "PciInterface - %02x\n", (UINTN
)PciHandle
->PciInterface
));
865 DEBUG ((EFI_D_INFO
, "PrimaryIrq - %02x\n", (UINTN
)PciHandle
->PrimaryIrq
));
866 DEBUG ((EFI_D_INFO
, "PrimaryReserved - %02x\n", (UINTN
)PciHandle
->PrimaryReserved
));
867 DEBUG ((EFI_D_INFO
, "PrimaryControl - %04x\n", (UINTN
)PciHandle
->PrimaryControl
));
868 DEBUG ((EFI_D_INFO
, "PrimaryBase - %04x\n", (UINTN
)PciHandle
->PrimaryBase
));
869 DEBUG ((EFI_D_INFO
, "PrimaryBusMaster - %04x\n", (UINTN
)PciHandle
->PrimaryBusMaster
));
871 DEBUG ((EFI_D_INFO
, "SecondaryIrq - %02x\n", (UINTN
)PciHandle
->SecondaryIrq
));
872 DEBUG ((EFI_D_INFO
, "SecondaryReserved - %02x\n", (UINTN
)PciHandle
->SecondaryReserved
));
873 DEBUG ((EFI_D_INFO
, "SecondaryControl - %04x\n", (UINTN
)PciHandle
->SecondaryControl
));
874 DEBUG ((EFI_D_INFO
, "SecondaryBase - %04x\n", (UINTN
)PciHandle
->SecondaryBase
));
875 DEBUG ((EFI_D_INFO
, "SecondaryBusMaster - %04x\n", (UINTN
)PciHandle
->SecondaryBusMaster
));
880 Copy the $PIR table as required.
882 @param Private Legacy BIOS Instance data
883 @param PciIo Pointer to PCI_IO protocol
884 @param PciIrq Pci IRQ number
885 @param PciConfigHeader Type00 Pci configuration header
889 InstallLegacyIrqHandler (
890 IN LEGACY_BIOS_INSTANCE
*Private
,
891 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
893 IN PCI_TYPE00
*PciConfigHeader
896 EFI_IA32_REGISTER_SET Regs
;
902 EFI_LEGACY_8259_PROTOCOL
*Legacy8259
;
903 UINT16 PrimaryMaster
;
904 UINT16 SecondaryMaster
;
906 UINTN RegisterAddress
;
911 Legacy8259
= Private
->Legacy8259
;
913 // Disable interrupt in PIC, in case shared, to prevent an
914 // interrupt from occuring.
916 Legacy8259
->GetMask (
924 LegMask
= (UINT16
) (LegMask
| (UINT16
) (1 << PciIrq
));
926 Legacy8259
->SetMask (
941 Private
->IntThunk
->PciHandler
.PciBus
= (UINT8
) PciBus
;
942 Private
->IntThunk
->PciHandler
.PciDeviceFun
= (UINT8
) ((PciDevice
<< 3) + PciFunction
);
943 Private
->IntThunk
->PciHandler
.PciSegment
= (UINT8
) PciSegment
;
944 Private
->IntThunk
->PciHandler
.PciClass
= PciConfigHeader
->Hdr
.ClassCode
[2];
945 Private
->IntThunk
->PciHandler
.PciSubclass
= PciConfigHeader
->Hdr
.ClassCode
[1];
946 Private
->IntThunk
->PciHandler
.PciInterface
= PciConfigHeader
->Hdr
.ClassCode
[0];
949 // Use native mode base address registers in two cases:
950 // 1. Programming Interface (PI) register indicates Primary Controller is
952 // 2. PCI device Sub Class Code is not IDE
954 Private
->IntThunk
->PciHandler
.PrimaryBusMaster
= (UINT16
)(PciConfigHeader
->Device
.Bar
[4] & 0xfffc);
955 if (((PciConfigHeader
->Hdr
.ClassCode
[0] & 0x01) != 0) || (PciConfigHeader
->Hdr
.ClassCode
[1] != PCI_CLASS_MASS_STORAGE_IDE
)) {
956 Private
->IntThunk
->PciHandler
.PrimaryIrq
= PciIrq
;
957 Private
->IntThunk
->PciHandler
.PrimaryBase
= (UINT16
) (PciConfigHeader
->Device
.Bar
[0] & 0xfffc);
958 Private
->IntThunk
->PciHandler
.PrimaryControl
= (UINT16
) ((PciConfigHeader
->Device
.Bar
[1] & 0xfffc) + 2);
960 Private
->IntThunk
->PciHandler
.PrimaryIrq
= 14;
961 Private
->IntThunk
->PciHandler
.PrimaryBase
= 0x1f0;
962 Private
->IntThunk
->PciHandler
.PrimaryControl
= 0x3f6;
965 // Secondary controller data
967 if (Private
->IntThunk
->PciHandler
.PrimaryBusMaster
!= 0) {
968 Private
->IntThunk
->PciHandler
.SecondaryBusMaster
= (UINT16
) ((PciConfigHeader
->Device
.Bar
[4] & 0xfffc) + 8);
969 PrimaryMaster
= (UINT16
) (Private
->IntThunk
->PciHandler
.PrimaryBusMaster
+ 2);
970 SecondaryMaster
= (UINT16
) (Private
->IntThunk
->PciHandler
.SecondaryBusMaster
+ 2);
973 // Clear pending interrupts in Bus Master registers
975 IoWrite16 (PrimaryMaster
, 0x04);
976 IoWrite16 (SecondaryMaster
, 0x04);
981 // Use native mode base address registers in two cases:
982 // 1. Programming Interface (PI) register indicates Secondary Controller is
984 // 2. PCI device Sub Class Code is not IDE
986 if (((PciConfigHeader
->Hdr
.ClassCode
[0] & 0x04) != 0) || (PciConfigHeader
->Hdr
.ClassCode
[1] != PCI_CLASS_MASS_STORAGE_IDE
)) {
987 Private
->IntThunk
->PciHandler
.SecondaryIrq
= PciIrq
;
988 Private
->IntThunk
->PciHandler
.SecondaryBase
= (UINT16
) (PciConfigHeader
->Device
.Bar
[2] & 0xfffc);
989 Private
->IntThunk
->PciHandler
.SecondaryControl
= (UINT16
) ((PciConfigHeader
->Device
.Bar
[3] & 0xfffc) + 2);
992 Private
->IntThunk
->PciHandler
.SecondaryIrq
= 15;
993 Private
->IntThunk
->PciHandler
.SecondaryBase
= 0x170;
994 Private
->IntThunk
->PciHandler
.SecondaryControl
= 0x376;
998 // Clear pending interrupts in IDE Command Block Status reg before we
999 // Thunk to CSM16 below. Don't want a pending Interrupt before we
1000 // install the handlers as wierd corruption would occur and hang system.
1003 // Read IDE CMD blk status reg to clear out any pending interrupts.
1004 // Do here for Primary and Secondary IDE channels
1006 RegisterAddress
= (UINT16
)Private
->IntThunk
->PciHandler
.PrimaryBase
+ 0x07;
1007 IoRead8 (RegisterAddress
);
1008 RegisterAddress
= (UINT16
)Private
->IntThunk
->PciHandler
.SecondaryBase
+ 0x07;
1009 IoRead8 (RegisterAddress
);
1011 Private
->IntThunk
->PciHandler
.PrimaryReserved
= 0;
1012 Private
->IntThunk
->PciHandler
.SecondaryReserved
= 0;
1013 Private
->LegacyRegion
->UnLock (
1014 Private
->LegacyRegion
,
1020 Regs
.X
.AX
= Legacy16InstallPciHandler
;
1021 TempData
= (UINTN
) &Private
->IntThunk
->PciHandler
;
1022 Regs
.X
.ES
= EFI_SEGMENT ((UINT32
) TempData
);
1023 Regs
.X
.BX
= EFI_OFFSET ((UINT32
) TempData
);
1025 DumpPciHandle (&Private
->IntThunk
->PciHandler
);
1027 Private
->LegacyBios
.FarCall86 (
1028 &Private
->LegacyBios
,
1029 Private
->Legacy16CallSegment
,
1030 Private
->Legacy16CallOffset
,
1036 Private
->Cpu
->FlushDataCache (Private
->Cpu
, 0xE0000, 0x20000, EfiCpuFlushTypeWriteBackInvalidate
);
1037 Private
->LegacyRegion
->Lock (
1038 Private
->LegacyRegion
,
1048 Program the interrupt routing register in all the PCI devices. On a PC AT system
1049 this register contains the 8259 IRQ vector that matches it's PCI interrupt.
1051 @param Private Legacy BIOS Instance data
1053 @retval EFI_SUCCESS Succeed.
1054 @retval EFI_ALREADY_STARTED All PCI devices have been processed.
1058 PciProgramAllInterruptLineRegisters (
1059 IN LEGACY_BIOS_INSTANCE
*Private
1063 EFI_PCI_IO_PROTOCOL
*PciIo
;
1064 EFI_LEGACY_8259_PROTOCOL
*Legacy8259
;
1065 EFI_LEGACY_INTERRUPT_PROTOCOL
*LegacyInterrupt
;
1066 EFI_LEGACY_BIOS_PLATFORM_PROTOCOL
*LegacyBiosPlatform
;
1070 EFI_HANDLE
*HandleBuffer
;
1071 UINTN MassStorageHandleCount
;
1072 EFI_HANDLE
*MassStorageHandleBuffer
;
1073 UINTN MassStorageHandleIndex
;
1080 EFI_LEGACY_IRQ_ROUTING_ENTRY
*RoutingTable
;
1081 UINTN RoutingTableEntries
;
1083 UINT16 LegEdgeLevel
;
1084 PCI_TYPE00 PciConfigHeader
;
1085 EFI_LEGACY_PIRQ_TABLE_HEADER
*PirqTable
;
1086 UINTN PirqTableSize
;
1092 // Note - This routine use to return immediately if Private->PciInterruptLine
1093 // was true. Routine changed since resets etc can cause not all
1094 // PciIo protocols to be registered the first time through.
1095 // New algorithm is to do the copy $PIR table on first pass and save
1096 // HandleCount on first pass. If subsequent passes LocateHandleBuffer gives
1097 // a larger handle count then proceed with body of function else return
1098 // EFI_ALREADY_STARTED. In addition check if PCI device InterruptLine != 0.
1099 // If zero then function unprogrammed else skip function.
1101 Legacy8259
= Private
->Legacy8259
;
1102 LegacyInterrupt
= Private
->LegacyInterrupt
;
1103 LegacyBiosPlatform
= Private
->LegacyBiosPlatform
;
1105 LegacyBiosPlatform
->GetRoutingTable (
1106 Private
->LegacyBiosPlatform
,
1107 (VOID
*) &RoutingTable
,
1108 &RoutingTableEntries
,
1109 (VOID
*) &PirqTable
,
1114 CreateBridgeTable (RoutingTable
, RoutingTableEntries
);
1116 if (!Private
->PciInterruptLine
) {
1120 RoutingTableEntries
,
1126 Status
= gBS
->LocateHandleBuffer (
1128 &gEfiPciIoProtocolGuid
,
1133 if (EFI_ERROR (Status
)) {
1134 return EFI_NOT_FOUND
;
1136 if (HandleCount
== mHandleCount
) {
1137 FreePool (HandleBuffer
);
1138 return EFI_ALREADY_STARTED
;
1141 if (mHandleCount
== 0x00) {
1142 mHandleCount
= HandleCount
;
1145 for (Index
= 0; Index
< HandleCount
; Index
++) {
1147 // If VGA then only do VGA to allow drives fore time to spin up
1148 // otherwise assign PCI IRQs to all potential devices.
1150 if ((mVgaInstallationInProgress
) && (HandleBuffer
[Index
] != mVgaHandle
)) {
1154 // Force code to go through all handles next time called if video.
1155 // This will catch case where HandleCount doesn't change but want
1156 // to get drive info etc.
1158 mHandleCount
= 0x00;
1161 Status
= gBS
->HandleProtocol (
1162 HandleBuffer
[Index
],
1163 &gEfiPciIoProtocolGuid
,
1166 ASSERT_EFI_ERROR (Status
);
1169 // Test whether the device can be enabled or not.
1170 // If it can't be enabled, then just skip it to avoid further operation.
1174 EfiPciIoWidthUint32
,
1176 sizeof (PciConfigHeader
) / sizeof (UINT32
),
1179 Command
= PciConfigHeader
.Hdr
.Command
;
1182 // Note PciIo->Attributes does not program the PCI command register
1184 Status
= PciIo
->Attributes (
1186 EfiPciIoAttributeOperationSupported
,
1190 if (!EFI_ERROR (Status
)) {
1191 Supports
&= EFI_PCI_DEVICE_ENABLE
;
1192 Status
= PciIo
->Attributes (
1194 EfiPciIoAttributeOperationEnable
,
1199 PciIo
->Pci
.Write (PciIo
, EfiPciIoWidthUint16
, 0x04, 1, &Command
);
1201 if (EFI_ERROR (Status
)) {
1205 InterruptPin
= PciConfigHeader
.Device
.InterruptPin
;
1207 if ((InterruptPin
!= 0) && (PciConfigHeader
.Device
.InterruptLine
== PCI_INT_LINE_UNKNOWN
)) {
1208 PciIo
->GetLocation (
1216 // Translate PIRQ index back thru busses to slot bus with InterruptPin
1221 Status
= GetBaseBus (
1229 if (Status
== EFI_NOT_FOUND
) {
1239 // Translate InterruptPin(0-3) into PIRQ
1241 Status
= LegacyBiosPlatform
->TranslatePirq (
1250 // TranslatePirq() should never fail or we are in trouble
1251 // If it does return failure status, check your PIRQ routing table to see if some item is missing or incorrect
1253 if (EFI_ERROR (Status
)) {
1254 DEBUG ((EFI_D_ERROR
, "Translate Pirq Failed - Status = %r\n ", Status
));
1258 LegacyInterrupt
->WritePirq (
1265 // Check if device has an OPROM associated with it.
1266 // If not invoke special 16-bit function, to allow 16-bit
1267 // code to install an interrupt handler.
1269 Status
= LegacyBiosCheckPciRom (
1270 &Private
->LegacyBios
,
1271 HandleBuffer
[Index
],
1276 if ((EFI_ERROR (Status
)) && (PciConfigHeader
.Hdr
.ClassCode
[2] == PCI_CLASS_MASS_STORAGE
)) {
1278 // Device has no OPROM associated with it and is a mass storage
1279 // device. It needs to have an PCI IRQ handler installed. To
1280 // correctly install the handler we need to insure device is
1281 // connected. The device may just have register itself but not
1282 // been connected. Re-read PCI config space after as it can
1286 // Get IDE Handle. If matches handle then skip ConnectController
1287 // since ConnectController may force native mode and we don't
1288 // want that for primary IDE controller
1290 MassStorageHandleCount
= 0;
1291 MassStorageHandleBuffer
= NULL
;
1292 LegacyBiosPlatform
->GetPlatformHandle (
1293 Private
->LegacyBiosPlatform
,
1294 EfiGetPlatformIdeHandle
,
1296 &MassStorageHandleBuffer
,
1297 &MassStorageHandleCount
,
1301 HddInfo
= &Private
->IntThunk
->EfiToLegacy16BootTable
.HddInfo
[0];
1303 LegacyBiosBuildIdeData (Private
, &HddInfo
, 0);
1306 EfiPciIoWidthUint32
,
1308 sizeof (PciConfigHeader
) / sizeof (UINT32
),
1312 for (MassStorageHandleIndex
= 0; MassStorageHandleIndex
< MassStorageHandleCount
; MassStorageHandleIndex
++) {
1313 if (MassStorageHandleBuffer
[MassStorageHandleIndex
] == HandleBuffer
[Index
]) {
1315 // InstallLegacyIrqHandler according to Platform requirement
1317 InstallLegacyIrqHandler (
1328 // Write InterruptPin and enable 8259.
1337 Private
->IntThunk
->EfiToLegacy16BootTable
.PciIrqMask
= (UINT16
) (Private
->IntThunk
->EfiToLegacy16BootTable
.PciIrqMask
| (UINT16
) (1 << PciIrq
));
1339 Legacy8259
->GetMask (
1347 LegMask
= (UINT16
) (LegMask
& (UINT16
)~(1 << PciIrq
));
1348 LegEdgeLevel
= (UINT16
) (LegEdgeLevel
| (UINT16
) (1 << PciIrq
));
1349 Legacy8259
->SetMask (
1358 FreePool (HandleBuffer
);
1364 Find & verify PnP Expansion header in ROM image
1366 @param Private Protocol instance pointer.
1367 @param FirstHeader 1 = Find first header, 0 = Find successive headers
1368 @param PnpPtr Input Rom start if FirstHeader =1, Current Header
1369 otherwise Output Next header, if it exists
1371 @retval EFI_SUCCESS Next Header found at BasePnpPtr
1372 @retval EFI_NOT_FOUND No more headers
1376 FindNextPnpExpansionHeader (
1377 IN LEGACY_BIOS_INSTANCE
*Private
,
1378 IN BOOLEAN FirstHeader
,
1379 IN OUT LEGACY_PNP_EXPANSION_HEADER
**PnpPtr
1384 LEGACY_PNP_EXPANSION_HEADER
*LocalPnpPtr
;
1385 LocalPnpPtr
= *PnpPtr
;
1386 if (FirstHeader
== FIRST_INSTANCE
) {
1387 mBasePnpPtr
= LocalPnpPtr
;
1388 mBbsRomSegment
= (UINT16
) ((UINTN
) mBasePnpPtr
>> 4);
1390 // Offset 0x1a gives offset to PnP expansion header for the first
1391 // instance, there after the structure gives the offset to the next
1394 LocalPnpPtr
= (LEGACY_PNP_EXPANSION_HEADER
*) ((UINT8
*) LocalPnpPtr
+ 0x1a);
1395 TempData
= (*((UINT16
*) LocalPnpPtr
));
1397 TempData
= (UINT16
) LocalPnpPtr
->NextHeader
;
1400 LocalPnpPtr
= (LEGACY_PNP_EXPANSION_HEADER
*) (((UINT8
*) mBasePnpPtr
+ TempData
));
1403 // Search for PnP table in Shadowed ROM
1405 *PnpPtr
= LocalPnpPtr
;
1406 if (*(UINT32
*) LocalPnpPtr
== SIGNATURE_32 ('$', 'P', 'n', 'P')) {
1409 return EFI_NOT_FOUND
;
1415 Update list of Bev or BCV table entries.
1417 @param Private Protocol instance pointer.
1418 @param RomStart Table of ROM start address in RAM/ROM. PciIo _
1419 Handle to PCI IO for this device
1420 @param PciIo Instance of PCI I/O Protocol
1422 @retval EFI_SUCCESS Always should succeed.
1427 IN LEGACY_BIOS_INSTANCE
*Private
,
1428 IN EFI_LEGACY_EXPANSION_ROM_HEADER
*RomStart
,
1429 IN EFI_PCI_IO_PROTOCOL
*PciIo
1433 BBS_TABLE
*BbsTable
;
1435 EFI_LEGACY_EXPANSION_ROM_HEADER
*PciPtr
;
1436 LEGACY_PNP_EXPANSION_HEADER
*PnpPtr
;
1450 DeviceType
= BBS_UNKNOWN
;
1453 // Skip floppy and 2*onboard IDE controller entries(Master/Slave per
1456 BbsIndex
= Private
->IntThunk
->EfiToLegacy16BootTable
.NumberBbsEntries
;
1458 BbsTable
= (BBS_TABLE
*)(UINTN
) Private
->IntThunk
->EfiToLegacy16BootTable
.BbsTable
;
1459 PnpPtr
= (LEGACY_PNP_EXPANSION_HEADER
*) RomStart
;
1460 PciPtr
= (EFI_LEGACY_EXPANSION_ROM_HEADER
*) RomStart
;
1462 RomEnd
= (VOID
*) (PciPtr
->Size512
* 512 + (UINTN
) PciPtr
);
1463 Instance
= FIRST_INSTANCE
;
1465 // OPROMs like PXE may not be tied to a piece of hardware and thus
1466 // don't have a PciIo associated with them
1468 if (PciIo
!= NULL
) {
1469 PciIo
->GetLocation (
1484 if (Class
== PCI_CLASS_MASS_STORAGE
) {
1485 DeviceType
= BBS_HARDDISK
;
1487 if (Class
== PCI_CLASS_NETWORK
) {
1488 DeviceType
= BBS_EMBED_NETWORK
;
1493 if (PciPtr
>= (EFI_LEGACY_EXPANSION_ROM_HEADER
*) ((UINTN
) 0xc8000)) {
1495 Status
= FindNextPnpExpansionHeader (Private
, Instance
, &PnpPtr
);
1496 Instance
= NOT_FIRST_INSTANCE
;
1497 if (EFI_ERROR (Status
)) {
1501 // There can be additional $PnP headers within the OPROM.
1502 // Example: SCSI can have one per drive.
1504 BbsTable
[BbsIndex
].BootPriority
= BBS_UNPRIORITIZED_ENTRY
;
1505 BbsTable
[BbsIndex
].DeviceType
= DeviceType
;
1506 BbsTable
[BbsIndex
].Bus
= (UINT32
) Bus
;
1507 BbsTable
[BbsIndex
].Device
= (UINT32
) Device
;
1508 BbsTable
[BbsIndex
].Function
= (UINT32
) Function
;
1509 BbsTable
[BbsIndex
].StatusFlags
.OldPosition
= 0;
1510 BbsTable
[BbsIndex
].StatusFlags
.Reserved1
= 0;
1511 BbsTable
[BbsIndex
].StatusFlags
.Enabled
= 0;
1512 BbsTable
[BbsIndex
].StatusFlags
.Failed
= 0;
1513 BbsTable
[BbsIndex
].StatusFlags
.MediaPresent
= 0;
1514 BbsTable
[BbsIndex
].StatusFlags
.Reserved2
= 0;
1515 BbsTable
[BbsIndex
].Class
= PnpPtr
->Class
;
1516 BbsTable
[BbsIndex
].SubClass
= PnpPtr
->SubClass
;
1517 BbsTable
[BbsIndex
].DescStringOffset
= PnpPtr
->ProductNamePointer
;
1518 BbsTable
[BbsIndex
].DescStringSegment
= mBbsRomSegment
;
1519 BbsTable
[BbsIndex
].MfgStringOffset
= PnpPtr
->MfgPointer
;
1520 BbsTable
[BbsIndex
].MfgStringSegment
= mBbsRomSegment
;
1521 BbsTable
[BbsIndex
].BootHandlerSegment
= mBbsRomSegment
;
1524 // Have seen case where PXE base code have PnP expansion ROM
1525 // header but no Bcv or Bev vectors.
1527 if (PnpPtr
->Bcv
!= 0) {
1528 BbsTable
[BbsIndex
].BootHandlerOffset
= PnpPtr
->Bcv
;
1532 if (PnpPtr
->Bev
!= 0) {
1533 BbsTable
[BbsIndex
].BootHandlerOffset
= PnpPtr
->Bev
;
1534 BbsTable
[BbsIndex
].DeviceType
= BBS_BEV_DEVICE
;
1538 if ((PnpPtr
== (LEGACY_PNP_EXPANSION_HEADER
*) PciPtr
) || (PnpPtr
> (LEGACY_PNP_EXPANSION_HEADER
*) RomEnd
)) {
1544 BbsTable
[BbsIndex
].BootPriority
= BBS_IGNORE_ENTRY
;
1545 Private
->IntThunk
->EfiToLegacy16BootTable
.NumberBbsEntries
= (UINT32
) BbsIndex
;
1551 Shadow all the PCI legacy ROMs. Use data from the Legacy BIOS Protocol
1552 to chose the order. Skip any devices that have already have legacy
1555 @param Private Protocol instance pointer.
1557 @retval EFI_SUCCESS Succeed.
1558 @retval EFI_UNSUPPORTED Cannot get VGA device handle.
1563 IN LEGACY_BIOS_INSTANCE
*Private
1567 EFI_PCI_IO_PROTOCOL
*PciIo
;
1571 EFI_HANDLE
*HandleBuffer
;
1572 EFI_HANDLE VgaHandle
;
1573 EFI_HANDLE FirstHandle
;
1576 PCI_TYPE00 PciConfigHeader
;
1581 // Make the VGA device first
1583 Status
= Private
->LegacyBiosPlatform
->GetPlatformHandle (
1584 Private
->LegacyBiosPlatform
,
1585 EfiGetPlatformVgaHandle
,
1591 if (EFI_ERROR (Status
)) {
1592 return EFI_UNSUPPORTED
;
1595 VgaHandle
= HandleBuffer
[0];
1597 Status
= gBS
->LocateHandleBuffer (
1599 &gEfiPciIoProtocolGuid
,
1605 if (EFI_ERROR (Status
)) {
1609 // Place the VGA handle as first.
1611 for (Index
= 0; Index
< HandleCount
; Index
++) {
1612 if (HandleBuffer
[Index
] == VgaHandle
) {
1613 FirstHandle
= HandleBuffer
[0];
1614 HandleBuffer
[0] = HandleBuffer
[Index
];
1615 HandleBuffer
[Index
] = FirstHandle
;
1620 // Allocate memory to save Command WORD from each device. We do this
1621 // to restore devices to same state as EFI after switching to legacy.
1623 Command
= (UINT16
*) AllocatePool (
1624 sizeof (UINT16
) * (HandleCount
+ 1)
1626 if (NULL
== Command
) {
1627 FreePool (HandleBuffer
);
1628 return EFI_OUT_OF_RESOURCES
;
1631 // Disconnect all EFI devices first. This covers cases where alegacy BIOS
1632 // may control multiple PCI devices.
1634 for (Index
= 0; Index
< HandleCount
; Index
++) {
1636 Status
= gBS
->HandleProtocol (
1637 HandleBuffer
[Index
],
1638 &gEfiPciIoProtocolGuid
,
1641 ASSERT_EFI_ERROR (Status
);
1644 // Save command register for "connect" loop
1648 EfiPciIoWidthUint32
,
1650 sizeof (PciConfigHeader
) / sizeof (UINT32
),
1653 Command
[Index
] = PciConfigHeader
.Hdr
.Command
;
1655 // Skip any device that already has a legacy ROM run
1657 Status
= IsLegacyRom (HandleBuffer
[Index
]);
1658 if (!EFI_ERROR (Status
)) {
1662 // Stop EFI Drivers with oprom.
1664 gBS
->DisconnectController (
1665 HandleBuffer
[Index
],
1671 // For every device that has not had a legacy ROM started. Start a legacy ROM.
1673 for (Index
= 0; Index
< HandleCount
; Index
++) {
1675 Status
= gBS
->HandleProtocol (
1676 HandleBuffer
[Index
],
1677 &gEfiPciIoProtocolGuid
,
1681 ASSERT_EFI_ERROR (Status
);
1684 // Here make sure if one VGA have been shadowed,
1685 // then wil not shadowed another one.
1689 EfiPciIoWidthUint32
,
1691 sizeof (Pci
) / sizeof (UINT32
),
1696 // Only one Video OPROM can be given control in BIOS phase. If there are multiple Video devices,
1697 // one will work in legacy mode (OPROM will be given control) and
1698 // other Video devices will work in native mode (OS driver will handle these devices).
1700 if (IS_PCI_DISPLAY (&Pci
) && Index
!= 0) {
1704 // Skip any device that already has a legacy ROM run
1706 Status
= IsLegacyRom (HandleBuffer
[Index
]);
1707 if (!EFI_ERROR (Status
)) {
1711 // Install legacy ROM
1713 Status
= LegacyBiosInstallPciRom (
1714 &Private
->LegacyBios
,
1715 HandleBuffer
[Index
],
1720 (VOID
**) &RomStart
,
1723 if (EFI_ERROR (Status
)) {
1724 if (!((Status
== EFI_UNSUPPORTED
) && (Flags
== NO_ROM
))) {
1729 // Restore Command register so legacy has same devices enabled or disabled
1731 // If Flags = NO_ROM use command register as is. This covers the
1733 // Device has no ROMs associated with it.
1734 // Device has ROM associated with it but was already
1736 // = ROM_FOUND but not VALID_LEGACY_ROM, disable it.
1737 // = ROM_FOUND and VALID_LEGACY_ROM, enable it.
1739 if ((Flags
& ROM_FOUND
) == ROM_FOUND
) {
1740 if ((Flags
& VALID_LEGACY_ROM
) == 0) {
1744 // For several VGAs, only one of them can be enabled.
1746 Status
= PciIo
->Attributes (
1748 EfiPciIoAttributeOperationSupported
,
1752 if (!EFI_ERROR (Status
)) {
1753 Supports
&= EFI_PCI_DEVICE_ENABLE
;
1754 Status
= PciIo
->Attributes (
1756 EfiPciIoAttributeOperationEnable
,
1761 if (!EFI_ERROR (Status
)) {
1762 Command
[Index
] = 0x1f;
1769 EfiPciIoWidthUint16
,
1777 FreePool (HandleBuffer
);
1783 Test to see if a legacy PCI ROM exists for this device. Optionally return
1784 the Legacy ROM instance for this PCI device.
1786 @param This Protocol instance pointer.
1787 @param PciHandle The PCI PC-AT OPROM from this devices ROM BAR will
1789 @param RomImage Return the legacy PCI ROM for this device
1790 @param RomSize Size of ROM Image
1791 @param Flags Indicates if ROM found and if PC-AT.
1793 @retval EFI_SUCCESS Legacy Option ROM availible for this device
1794 @retval EFI_UNSUPPORTED Legacy Option ROM not supported.
1799 LegacyBiosCheckPciRom (
1800 IN EFI_LEGACY_BIOS_PROTOCOL
*This
,
1801 IN EFI_HANDLE PciHandle
,
1802 OUT VOID
**RomImage
, OPTIONAL
1803 OUT UINTN
*RomSize
, OPTIONAL
1807 return LegacyBiosCheckPciRomEx (
1822 Routine Description:
1823 Test to see if a legacy PCI ROM exists for this device. Optionally return
1824 the Legacy ROM instance for this PCI device.
1826 @param[in] This Protocol instance pointer.
1827 @param[in] PciHandle The PCI PC-AT OPROM from this devices ROM BAR will be loaded
1828 @param[out] RomImage Return the legacy PCI ROM for this device
1829 @param[out] RomSize Size of ROM Image
1830 @param[out] RuntimeImageLength Runtime size of ROM Image
1831 @param[out] Flags Indicates if ROM found and if PC-AT.
1832 @param[out] OpromRevision Revision of the PCI Rom
1833 @param[out] ConfigUtilityCodeHeaderPointer of Configuration Utility Code Header
1835 @return EFI_SUCCESS Legacy Option ROM availible for this device
1836 @return EFI_ALREADY_STARTED This device is already managed by its Oprom
1837 @return EFI_UNSUPPORTED Legacy Option ROM not supported.
1841 LegacyBiosCheckPciRomEx (
1842 IN EFI_LEGACY_BIOS_PROTOCOL
*This
,
1843 IN EFI_HANDLE PciHandle
,
1844 OUT VOID
**RomImage
, OPTIONAL
1845 OUT UINTN
*RomSize
, OPTIONAL
1846 OUT UINTN
*RuntimeImageLength
, OPTIONAL
1847 OUT UINTN
*Flags
, OPTIONAL
1848 OUT UINT8
*OpromRevision
, OPTIONAL
1849 OUT VOID
**ConfigUtilityCodeHeader OPTIONAL
1853 LEGACY_BIOS_INSTANCE
*Private
;
1854 EFI_PCI_IO_PROTOCOL
*PciIo
;
1856 VOID
*LocalRomImage
;
1857 PCI_TYPE00 PciConfigHeader
;
1858 VOID
*LocalConfigUtilityCodeHeader
;
1861 Status
= gBS
->HandleProtocol (
1863 &gEfiPciIoProtocolGuid
,
1866 if (EFI_ERROR (Status
)) {
1867 return EFI_UNSUPPORTED
;
1871 // See if the option ROM for PciHandle has already been executed
1873 Status
= IsLegacyRom (PciHandle
);
1874 if (!EFI_ERROR (Status
)) {
1875 *Flags
|= (ROM_FOUND
| VALID_LEGACY_ROM
);
1879 // Check for PCI ROM Bar
1881 LocalRomSize
= (UINTN
) PciIo
->RomSize
;
1882 LocalRomImage
= PciIo
->RomImage
;
1883 if (LocalRomSize
!= 0) {
1884 *Flags
|= ROM_FOUND
;
1888 // PCI specification states you should check VendorId and Device Id.
1892 EfiPciIoWidthUint32
,
1894 sizeof (PciConfigHeader
) / sizeof (UINT32
),
1898 Private
= LEGACY_BIOS_INSTANCE_FROM_THIS (This
);
1899 Status
= GetPciLegacyRom (
1900 Private
->Csm16PciInterfaceVersion
,
1901 PciConfigHeader
.Hdr
.VendorId
,
1902 PciConfigHeader
.Hdr
.DeviceId
,
1907 &LocalConfigUtilityCodeHeader
1909 if (EFI_ERROR (Status
)) {
1910 return EFI_UNSUPPORTED
;
1913 *Flags
|= VALID_LEGACY_ROM
;
1916 // See if Configuration Utility Code Header valid
1918 if (LocalConfigUtilityCodeHeader
!= NULL
) {
1919 *Flags
|= ROM_WITH_CONFIG
;
1922 if (ConfigUtilityCodeHeader
!= NULL
) {
1923 *ConfigUtilityCodeHeader
= LocalConfigUtilityCodeHeader
;
1926 if (RomImage
!= NULL
) {
1927 *RomImage
= LocalRomImage
;
1930 if (RomSize
!= NULL
) {
1931 *RomSize
= LocalRomSize
;
1938 Load a legacy PC-AT OPROM on the PciHandle device. Return information
1939 about how many disks were added by the OPROM and the shadow address and
1940 size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C:
1942 @retval EFI_SUCCESS Legacy ROM loaded for this device
1943 @retval EFI_NOT_FOUND No PS2 Keyboard found
1952 EFI_HANDLE
*HandleBuffer
;
1954 EFI_ISA_IO_PROTOCOL
*IsaIo
;
1958 // Get SimpleTextIn and find PS2 controller
1960 Status
= gBS
->LocateHandleBuffer (
1962 &gEfiSimpleTextInProtocolGuid
,
1967 if (EFI_ERROR (Status
)) {
1968 return EFI_NOT_FOUND
;
1970 for (Index
= 0; Index
< HandleCount
; Index
++) {
1972 // Open the IO Abstraction(s) needed to perform the supported test
1974 Status
= gBS
->OpenProtocol (
1975 HandleBuffer
[Index
],
1976 &gEfiIsaIoProtocolGuid
,
1979 HandleBuffer
[Index
],
1980 EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL
1983 if (!EFI_ERROR (Status
)) {
1985 // Use the ISA I/O Protocol to see if Controller is the Keyboard
1988 if (IsaIo
->ResourceList
->Device
.HID
!= EISA_PNP_ID (0x303) || IsaIo
->ResourceList
->Device
.UID
!= 0) {
1989 Status
= EFI_UNSUPPORTED
;
1992 gBS
->CloseProtocol (
1993 HandleBuffer
[Index
],
1994 &gEfiIsaIoProtocolGuid
,
2000 if (!EFI_ERROR (Status
)) {
2001 gBS
->ConnectController (HandleBuffer
[Index
], NULL
, NULL
, FALSE
);
2004 FreePool (HandleBuffer
);
2010 Load a legacy PC-AT OpROM for VGA controller.
2012 @param Private Driver private data.
2014 @retval EFI_SUCCESS Legacy ROM successfully installed for this device.
2015 @retval EFI_DEVICE_ERROR No VGA device handle found, or native EFI video
2016 driver cannot be successfully disconnected, or VGA
2017 thunk driver cannot be successfully connected.
2021 LegacyBiosInstallVgaRom (
2022 IN LEGACY_BIOS_INSTANCE
*Private
2026 EFI_HANDLE VgaHandle
;
2028 EFI_HANDLE
*HandleBuffer
;
2029 EFI_HANDLE
*ConnectHandleBuffer
;
2030 EFI_PCI_IO_PROTOCOL
*PciIo
;
2031 PCI_TYPE00 PciConfigHeader
;
2033 EFI_OPEN_PROTOCOL_INFORMATION_ENTRY
*OpenInfoBuffer
;
2039 // EfiLegacyBiosGuild attached to a device implies that there is a legacy
2040 // BIOS associated with that device.
2042 // There are 3 cases to consider.
2043 // Case 1: No EFI driver is controlling the video.
2044 // Action: Return EFI_SUCCESS from DisconnectController, search
2045 // video thunk driver, and connect it.
2046 // Case 2: EFI driver is controlling the video and EfiLegacyBiosGuid is
2047 // not on the image handle.
2048 // Action: Disconnect EFI driver.
2049 // ConnectController for video thunk
2050 // Case 3: EFI driver is controlling the video and EfiLegacyBiosGuid is
2051 // on the image handle.
2052 // Action: Do nothing and set Private->VgaInstalled = TRUE.
2053 // Then this routine is not called any more.
2056 // Get the VGA device.
2058 Status
= Private
->LegacyBiosPlatform
->GetPlatformHandle (
2059 Private
->LegacyBiosPlatform
,
2060 EfiGetPlatformVgaHandle
,
2066 if (EFI_ERROR (Status
)) {
2067 return EFI_DEVICE_ERROR
;
2070 VgaHandle
= HandleBuffer
[0];
2073 // Check whether video thunk driver already starts.
2075 Status
= gBS
->OpenProtocolInformation (
2077 &gEfiPciIoProtocolGuid
,
2081 if (EFI_ERROR (Status
)) {
2085 for (Index
= 0; Index
< EntryCount
; Index
++) {
2086 if ((OpenInfoBuffer
[Index
].Attributes
& EFI_OPEN_PROTOCOL_BY_DRIVER
) != 0) {
2087 Status
= gBS
->HandleProtocol (
2088 OpenInfoBuffer
[Index
].AgentHandle
,
2089 &gEfiLegacyBiosGuid
,
2090 (VOID
**) &Interface
2092 if (!EFI_ERROR (Status
)) {
2094 // This should be video thunk driver which is managing video device
2095 // So it need not start again
2097 DEBUG ((EFI_D_INFO
, "Video thunk driver already start! Return!\n"));
2098 Private
->VgaInstalled
= TRUE
;
2105 // Kick off the native EFI driver
2107 Status
= gBS
->DisconnectController (
2112 if (EFI_ERROR (Status
)) {
2113 if (Status
!= EFI_NOT_FOUND
) {
2114 return EFI_DEVICE_ERROR
;
2120 // Find all the Thunk Driver
2122 HandleBuffer
= NULL
;
2123 Status
= gBS
->LocateHandleBuffer (
2125 &gEfiLegacyBiosGuid
,
2130 ASSERT_EFI_ERROR (Status
);
2131 ConnectHandleBuffer
= (EFI_HANDLE
*) AllocatePool (sizeof (EFI_HANDLE
) * (HandleCount
+ 1));
2132 ASSERT (ConnectHandleBuffer
!= NULL
);
2135 ConnectHandleBuffer
,
2137 sizeof (EFI_HANDLE
) * HandleCount
2139 ConnectHandleBuffer
[HandleCount
] = NULL
;
2141 FreePool (HandleBuffer
);
2144 // Enable the device and make sure VGA cycles are being forwarded to this VGA device
2146 Status
= gBS
->HandleProtocol (
2148 &gEfiPciIoProtocolGuid
,
2151 ASSERT_EFI_ERROR (Status
);
2154 EfiPciIoWidthUint32
,
2156 sizeof (PciConfigHeader
) / sizeof (UINT32
),
2160 Status
= PciIo
->Attributes (
2162 EfiPciIoAttributeOperationSupported
,
2166 if (!EFI_ERROR (Status
)) {
2167 Supports
&= EFI_PCI_DEVICE_ENABLE
| EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY
| \
2168 EFI_PCI_IO_ATTRIBUTE_VGA_IO
| EFI_PCI_IO_ATTRIBUTE_VGA_IO_16
;
2169 Status
= PciIo
->Attributes (
2171 EfiPciIoAttributeOperationEnable
,
2177 if (Status
== EFI_SUCCESS
) {
2178 Private
->VgaInstalled
= TRUE
;
2181 // Attach the VGA thunk driver.
2182 // Assume the video is installed. This prevents potential of infinite recursion.
2184 Status
= gBS
->ConnectController (
2186 ConnectHandleBuffer
,
2192 FreePool (ConnectHandleBuffer
);
2194 if (EFI_ERROR (Status
)) {
2196 Private
->VgaInstalled
= FALSE
;
2199 // Reconnect the EFI VGA driver.
2201 gBS
->ConnectController (VgaHandle
, NULL
, NULL
, TRUE
);
2202 return EFI_DEVICE_ERROR
;
2210 Load a legacy PC-AT OpROM.
2212 @param This Protocol instance pointer.
2213 @param Private Driver's private data.
2214 @param PciHandle The EFI handle for the PCI device. It could be
2215 NULL if the OpROM image is not associated with
2217 @param OpromRevision The revision of PCI PC-AT ROM image.
2218 @param RomImage Pointer to PCI PC-AT ROM image header. It must not
2220 @param ImageSize Size of the PCI PC-AT ROM image.
2221 @param RuntimeImageLength On input is the max runtime image length indicated by the PCIR structure
2222 On output is the actual runtime image length
2223 @param DiskStart Disk number of first device hooked by the ROM. If
2224 DiskStart is the same as DiskEnd no disked were
2226 @param DiskEnd Disk number of the last device hooked by the ROM.
2227 @param RomShadowAddress Shadow address of PC-AT ROM
2229 @retval EFI_SUCCESS Legacy ROM loaded for this device
2230 @retval EFI_OUT_OF_RESOURCES No more space for this ROM
2235 LegacyBiosInstallRom (
2236 IN EFI_LEGACY_BIOS_PROTOCOL
*This
,
2237 IN LEGACY_BIOS_INSTANCE
*Private
,
2238 IN EFI_HANDLE PciHandle
,
2239 IN UINT8 OpromRevision
,
2242 IN OUT UINTN
*RuntimeImageLength
,
2243 OUT UINT8
*DiskStart
, OPTIONAL
2244 OUT UINT8
*DiskEnd
, OPTIONAL
2245 OUT VOID
**RomShadowAddress OPTIONAL
2249 EFI_STATUS PciEnableStatus
;
2250 EFI_PCI_IO_PROTOCOL
*PciIo
;
2251 UINT8 LocalDiskStart
;
2257 EFI_IA32_REGISTER_SET Regs
;
2262 UINT32 StartBbsIndex
;
2266 UINTN RuntimeAddress
;
2267 EFI_PHYSICAL_ADDRESS PhysicalAddress
;
2278 PhysicalAddress
= 0;
2280 PciProgramAllInterruptLineRegisters (Private
);
2282 if ((OpromRevision
>= 3) && (Private
->Csm16PciInterfaceVersion
>= 0x0300)) {
2284 // CSM16 3.0 meets PCI 3.0 OpROM
2285 // first test if there is enough space for its INIT code
2287 PhysicalAddress
= CONVENTIONAL_MEMORY_TOP
;
2288 Status
= gBS
->AllocatePages (
2290 EfiBootServicesCode
,
2291 EFI_SIZE_TO_PAGES (ImageSize
),
2295 if (EFI_ERROR (Status
)) {
2296 DEBUG ((EFI_D_ERROR
, "return LegacyBiosInstallRom(%d): EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", __LINE__
));
2297 return EFI_OUT_OF_RESOURCES
;
2299 InitAddress
= (UINTN
) PhysicalAddress
;
2301 // then test if there is enough space for its RT code
2303 RuntimeAddress
= Private
->OptionRom
;
2304 if (RuntimeAddress
+ *RuntimeImageLength
> mEndOpromShadowAddress
) {
2305 DEBUG ((EFI_D_ERROR
, "return LegacyBiosInstallRom(%d): EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", __LINE__
));
2306 gBS
->FreePages (PhysicalAddress
, EFI_SIZE_TO_PAGES (ImageSize
));
2307 return EFI_OUT_OF_RESOURCES
;
2310 // CSM16 3.0 meets PCI 2.x OpROM
2311 // CSM16 2.x meets PCI 2.x/3.0 OpROM
2312 // test if there is enough space for its INIT code
2314 InitAddress
= PCI_START_ADDRESS (Private
->OptionRom
);
2315 if (InitAddress
+ ImageSize
> mEndOpromShadowAddress
) {
2316 DEBUG ((EFI_D_ERROR
, "return LegacyBiosInstallRom(%d): EFI_OUT_OF_RESOURCES (no more space for OpROM)\n", __LINE__
));
2317 return EFI_OUT_OF_RESOURCES
;
2320 RuntimeAddress
= InitAddress
;
2323 Private
->LegacyRegion
->UnLock (
2324 Private
->LegacyRegion
,
2330 Private
->LegacyRegion
->UnLock (
2331 Private
->LegacyRegion
,
2332 (UINT32
) RuntimeAddress
,
2337 DEBUG ((EFI_D_INFO
, " Shadowing OpROM init/runtime/isize = %x/%x/%x\n", InitAddress
, RuntimeAddress
, ImageSize
));
2339 CopyMem ((VOID
*) InitAddress
, RomImage
, ImageSize
);
2342 // Read the highest disk number "installed: and assume a new disk will
2343 // show up on the first drive past the current value.
2344 // There are several considerations here:
2345 // 1. Non-BBS compliant drives will change 40:75 but 16-bit CSM will undo
2346 // the change until boot selection time frame.
2347 // 2. BBS compliants drives will not change 40:75 until boot time.
2348 // 3. Onboard IDE controllers will change 40:75
2350 LocalDiskStart
= (UINT8
) ((*(UINT8
*) ((UINTN
) 0x475)) + 0x80);
2351 if ((Private
->Disk4075
+ 0x80) < LocalDiskStart
) {
2353 // Update table since onboard IDE drives found
2355 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].PciSegment
= 0xff;
2356 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].PciBus
= 0xff;
2357 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].PciDevice
= 0xff;
2358 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].PciFunction
= 0xff;
2359 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].StartDriveNumber
= (UINT8
) (Private
->Disk4075
+ 0x80);
2360 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].EndDriveNumber
= LocalDiskStart
;
2361 Private
->LegacyEfiHddTableIndex
++;
2362 Private
->Disk4075
= (UINT8
) (LocalDiskStart
& 0x7f);
2363 Private
->DiskEnd
= LocalDiskStart
;
2366 if (PciHandle
!= mVgaHandle
) {
2368 EnablePs2Keyboard ();
2371 // Store current mode settings since PrepareToScanRom may change mode.
2373 VideoMode
= *(UINT8
*) ((UINTN
) 0x449);
2376 // Notify the platform that we are about to scan the ROM
2378 Status
= Private
->LegacyBiosPlatform
->PlatformHooks (
2379 Private
->LegacyBiosPlatform
,
2380 EfiPlatformHookPrepareToScanRom
,
2389 // If Status returned is EFI_UNSUPPORTED then abort due to platform
2392 if (Status
== EFI_UNSUPPORTED
) {
2397 // Report corresponding status code
2399 REPORT_STATUS_CODE (
2401 (EFI_SOFTWARE_DXE_BS_DRIVER
| EFI_SW_CSM_LEGACY_ROM_INIT
)
2405 // Generate number of ticks since midnight for BDA. Some OPROMs require
2406 // this. Place result in 40:6C-6F
2408 gRT
->GetTime (&BootTime
, NULL
);
2409 LocalTime
= BootTime
.Hour
* 3600 + BootTime
.Minute
* 60 + BootTime
.Second
;
2412 // Multiply result by 18.2 for number of ticks since midnight.
2413 // Use 182/10 to avoid floating point math.
2415 LocalTime
= (LocalTime
* 182) / 10;
2416 BdaPtr
= (UINT32
*) ((UINTN
) 0x46C);
2417 *BdaPtr
= LocalTime
;
2420 // Pass in handoff data
2422 PciEnableStatus
= EFI_UNSUPPORTED
;
2423 ZeroMem (&Regs
, sizeof (Regs
));
2424 if (PciHandle
!= NULL
) {
2426 Status
= gBS
->HandleProtocol (
2428 &gEfiPciIoProtocolGuid
,
2431 ASSERT_EFI_ERROR (Status
);
2434 // Enable command register.
2436 PciEnableStatus
= PciIo
->Attributes (
2438 EfiPciIoAttributeOperationEnable
,
2439 EFI_PCI_DEVICE_ENABLE
,
2443 PciIo
->GetLocation (
2450 DEBUG ((EFI_D_INFO
, "Shadowing OpROM on the PCI device %x/%x/%x\n", Bus
, Device
, Function
));
2453 mIgnoreBbsUpdateFlag
= FALSE
;
2454 Regs
.X
.AX
= Legacy16DispatchOprom
;
2457 // Generate DispatchOpRomTable data
2459 Private
->IntThunk
->DispatchOpromTable
.PnPInstallationCheckSegment
= Private
->Legacy16Table
->PnPInstallationCheckSegment
;
2460 Private
->IntThunk
->DispatchOpromTable
.PnPInstallationCheckOffset
= Private
->Legacy16Table
->PnPInstallationCheckOffset
;
2461 Private
->IntThunk
->DispatchOpromTable
.OpromSegment
= (UINT16
) (InitAddress
>> 4);
2462 Private
->IntThunk
->DispatchOpromTable
.PciBus
= (UINT8
) Bus
;
2463 Private
->IntThunk
->DispatchOpromTable
.PciDeviceFunction
= (UINT8
) ((Device
<< 3) | Function
);
2464 Private
->IntThunk
->DispatchOpromTable
.NumberBbsEntries
= (UINT8
) Private
->IntThunk
->EfiToLegacy16BootTable
.NumberBbsEntries
;
2465 Private
->IntThunk
->DispatchOpromTable
.BbsTablePointer
= (UINT32
) (UINTN
) Private
->BbsTablePtr
;
2466 Private
->IntThunk
->DispatchOpromTable
.RuntimeSegment
= (UINT16
)((OpromRevision
< 3) ? 0xffff : (RuntimeAddress
>> 4));
2467 TempData
= (UINTN
) &Private
->IntThunk
->DispatchOpromTable
;
2468 Regs
.X
.ES
= EFI_SEGMENT ((UINT32
) TempData
);
2469 Regs
.X
.BX
= EFI_OFFSET ((UINT32
) TempData
);
2471 // Skip dispatching ROM for those PCI devices that can not be enabled by PciIo->Attributes
2472 // Otherwise, it may cause the system to hang in some cases
2474 if (!EFI_ERROR (PciEnableStatus
)) {
2475 DEBUG ((EFI_D_INFO
, " Legacy16DispatchOprom - %02x/%02x/%02x\n", Bus
, Device
, Function
));
2476 Private
->LegacyBios
.FarCall86 (
2477 &Private
->LegacyBios
,
2478 Private
->Legacy16CallSegment
,
2479 Private
->Legacy16CallOffset
,
2488 if (Private
->IntThunk
->DispatchOpromTable
.NumberBbsEntries
!= (UINT8
) Private
->IntThunk
->EfiToLegacy16BootTable
.NumberBbsEntries
) {
2489 Private
->IntThunk
->EfiToLegacy16BootTable
.NumberBbsEntries
= (UINT8
) Private
->IntThunk
->DispatchOpromTable
.NumberBbsEntries
;
2490 mIgnoreBbsUpdateFlag
= TRUE
;
2493 // Check if non-BBS compliant drives found
2495 if (Regs
.X
.BX
!= 0) {
2496 LocalDiskEnd
= (UINT8
) (LocalDiskStart
+ Regs
.H
.BL
);
2497 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].PciSegment
= (UINT8
) Segment
;
2498 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].PciBus
= (UINT8
) Bus
;
2499 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].PciDevice
= (UINT8
) Device
;
2500 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].PciFunction
= (UINT8
) Function
;
2501 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].StartDriveNumber
= Private
->DiskEnd
;
2502 Private
->DiskEnd
= LocalDiskEnd
;
2503 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].EndDriveNumber
= Private
->DiskEnd
;
2504 Private
->LegacyEfiHddTableIndex
+= 1;
2507 // Skip video mode set, if installing VGA
2509 if (PciHandle
!= mVgaHandle
) {
2511 // Set mode settings since PrepareToScanRom may change mode
2514 Regs
.H
.AL
= VideoMode
;
2515 Private
->LegacyBios
.Int86 (&Private
->LegacyBios
, 0x10, &Regs
);
2518 // Regs.X.AX from the adapter initializion is ignored since some adapters
2519 // do not follow the standard of setting AX = 0 on success.
2522 // The ROM could have updated it's size so we need to read again.
2524 *RuntimeImageLength
= ((EFI_LEGACY_EXPANSION_ROM_HEADER
*) (RuntimeAddress
))->Size512
* 512;
2525 DEBUG ((EFI_D_INFO
, " fsize = %x\n", *RuntimeImageLength
));
2528 // If OpROM runs in 2.0 mode
2530 if (PhysicalAddress
== 0) {
2531 if (*RuntimeImageLength
< ImageSize
) {
2533 // Make area from end of shadowed rom to end of original rom all ffs
2535 gBS
->SetMem ((VOID
*) (InitAddress
+ *RuntimeImageLength
), ImageSize
- *RuntimeImageLength
, 0xff);
2539 LocalDiskEnd
= (UINT8
) ((*(UINT8
*) ((UINTN
) 0x475)) + 0x80);
2542 // Allow platform to perform any required actions after the
2543 // OPROM has been initialized.
2545 Status
= Private
->LegacyBiosPlatform
->PlatformHooks (
2546 Private
->LegacyBiosPlatform
,
2547 EfiPlatformHookAfterRomInit
,
2554 if (PciHandle
!= NULL
) {
2556 // If no PCI Handle then no header or Bevs.
2558 if ((*RuntimeImageLength
!= 0) && (!mIgnoreBbsUpdateFlag
)) {
2559 StartBbsIndex
= Private
->IntThunk
->EfiToLegacy16BootTable
.NumberBbsEntries
;
2560 TempData
= RuntimeAddress
;
2563 (EFI_LEGACY_EXPANSION_ROM_HEADER
*) TempData
,
2566 EndBbsIndex
= Private
->IntThunk
->EfiToLegacy16BootTable
.NumberBbsEntries
;
2567 LocalDiskEnd
= (UINT8
) (LocalDiskStart
+ (UINT8
) (EndBbsIndex
- StartBbsIndex
));
2568 if (LocalDiskEnd
!= LocalDiskStart
) {
2569 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].PciSegment
= (UINT8
) Segment
;
2570 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].PciBus
= (UINT8
) Bus
;
2571 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].PciDevice
= (UINT8
) Device
;
2572 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].PciFunction
= (UINT8
) Function
;
2573 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].StartDriveNumber
= Private
->DiskEnd
;
2574 Private
->DiskEnd
= LocalDiskEnd
;
2575 Private
->LegacyEfiHddTable
[Private
->LegacyEfiHddTableIndex
].EndDriveNumber
= Private
->DiskEnd
;
2576 Private
->LegacyEfiHddTableIndex
+= 1;
2580 // Mark PCI device as having a legacy BIOS ROM loaded.
2584 (UINT32
) RuntimeAddress
,
2585 (UINT32
) *RuntimeImageLength
,
2592 // Stuff caller's OPTIONAL return parameters.
2594 if (RomShadowAddress
!= NULL
) {
2595 *RomShadowAddress
= (VOID
*) RuntimeAddress
;
2598 if (DiskStart
!= NULL
) {
2599 *DiskStart
= LocalDiskStart
;
2602 if (DiskEnd
!= NULL
) {
2603 *DiskEnd
= LocalDiskEnd
;
2606 Private
->OptionRom
= (UINT32
) (RuntimeAddress
+ *RuntimeImageLength
);
2608 Status
= EFI_SUCCESS
;
2611 if (PhysicalAddress
!= 0) {
2613 // Free pages when OpROM is 3.0
2615 gBS
->FreePages (PhysicalAddress
, EFI_SIZE_TO_PAGES (ImageSize
));
2619 // Insure all shadowed areas are locked
2621 Private
->LegacyRegion
->Lock (
2622 Private
->LegacyRegion
,
2632 Load a legacy PC-AT OPROM on the PciHandle device. Return information
2633 about how many disks were added by the OPROM and the shadow address and
2634 size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C:
2636 @param This Protocol instance pointer.
2637 @param PciHandle The PCI PC-AT OPROM from this devices ROM BAR will
2638 be loaded. This value is NULL if RomImage is
2639 non-NULL. This is the normal case.
2640 @param RomImage A PCI PC-AT ROM image. This argument is non-NULL
2641 if there is no hardware associated with the ROM
2642 and thus no PciHandle, otherwise is must be NULL.
2643 Example is PXE base code.
2644 @param Flags Indicates if ROM found and if PC-AT.
2645 @param DiskStart Disk number of first device hooked by the ROM. If
2646 DiskStart is the same as DiskEnd no disked were
2648 @param DiskEnd Disk number of the last device hooked by the ROM.
2649 @param RomShadowAddress Shadow address of PC-AT ROM
2650 @param RomShadowedSize Size of RomShadowAddress in bytes
2652 @retval EFI_SUCCESS Legacy ROM loaded for this device
2653 @retval EFI_INVALID_PARAMETER PciHandle not found
2654 @retval EFI_UNSUPPORTED There is no PCI ROM in the ROM BAR or no onboard
2660 LegacyBiosInstallPciRom (
2661 IN EFI_LEGACY_BIOS_PROTOCOL
* This
,
2662 IN EFI_HANDLE PciHandle
,
2665 OUT UINT8
*DiskStart
, OPTIONAL
2666 OUT UINT8
*DiskEnd
, OPTIONAL
2667 OUT VOID
**RomShadowAddress
, OPTIONAL
2668 OUT UINT32
*RomShadowedSize OPTIONAL
2672 LEGACY_BIOS_INSTANCE
*Private
;
2673 VOID
*LocalRomImage
;
2675 UINTN RuntimeImageLength
;
2676 EFI_PCI_IO_PROTOCOL
*PciIo
;
2677 PCI_TYPE01 PciConfigHeader
;
2679 EFI_HANDLE
*HandleBuffer
;
2686 UINT8 OpromRevision
;
2688 PCI_3_0_DATA_STRUCTURE
*Pcir
;
2692 Private
= LEGACY_BIOS_INSTANCE_FROM_THIS (This
);
2693 if (Private
->Legacy16Table
->LastPciBus
== 0) {
2695 // Get last bus number if not already found
2697 Status
= gBS
->LocateHandleBuffer (
2699 &gEfiPciIoProtocolGuid
,
2706 for (Index
= 0; Index
< HandleCount
; Index
++) {
2707 Status
= gBS
->HandleProtocol (
2708 HandleBuffer
[Index
],
2709 &gEfiPciIoProtocolGuid
,
2712 if (EFI_ERROR (Status
)) {
2716 Status
= PciIo
->GetLocation (
2723 if (PciBus
> LastBus
) {
2728 Private
->LegacyRegion
->UnLock (
2729 Private
->LegacyRegion
,
2734 Private
->Legacy16Table
->LastPciBus
= (UINT8
) LastBus
;
2735 Private
->LegacyRegion
->Lock (
2736 Private
->LegacyRegion
,
2744 if ((PciHandle
!= NULL
) && (RomImage
== NULL
)) {
2746 // If PciHandle has OpRom to Execute
2747 // and OpRom are all associated with Hardware
2749 Status
= gBS
->HandleProtocol (
2751 &gEfiPciIoProtocolGuid
,
2755 if (!EFI_ERROR (Status
)) {
2758 EfiPciIoWidthUint32
,
2760 sizeof (PciConfigHeader
) / sizeof (UINT32
),
2765 // if video installed & OPROM is video return
2769 ((PciConfigHeader
.Hdr
.ClassCode
[2] == PCI_CLASS_OLD
) &&
2770 (PciConfigHeader
.Hdr
.ClassCode
[1] == PCI_CLASS_OLD_VGA
))
2772 ((PciConfigHeader
.Hdr
.ClassCode
[2] == PCI_CLASS_DISPLAY
) &&
2773 (PciConfigHeader
.Hdr
.ClassCode
[1] == PCI_CLASS_DISPLAY_VGA
))
2776 (!Private
->VgaInstalled
)
2778 mVgaInstallationInProgress
= TRUE
;
2781 // return EFI_UNSUPPORTED;
2786 // To run any legacy image, the VGA needs to be installed first.
2787 // if installing the video, then don't need the thunk as already installed.
2789 Status
= Private
->LegacyBiosPlatform
->GetPlatformHandle (
2790 Private
->LegacyBiosPlatform
,
2791 EfiGetPlatformVgaHandle
,
2798 if (!EFI_ERROR (Status
)) {
2799 mVgaHandle
= HandleBuffer
[0];
2800 if ((!Private
->VgaInstalled
) && (PciHandle
!= mVgaHandle
)) {
2802 // A return status of EFI_NOT_FOUND is considered valid (No EFI
2803 // driver is controlling video.
2805 mVgaInstallationInProgress
= TRUE
;
2806 Status
= LegacyBiosInstallVgaRom (Private
);
2807 if (EFI_ERROR (Status
)) {
2808 if (Status
!= EFI_NOT_FOUND
) {
2809 mVgaInstallationInProgress
= FALSE
;
2813 mVgaInstallationInProgress
= FALSE
;
2818 // See if the option ROM for PciHandle has already been executed
2820 Status
= IsLegacyRom (PciHandle
);
2822 if (!EFI_ERROR (Status
)) {
2823 mVgaInstallationInProgress
= FALSE
;
2824 GetShadowedRomParameters (
2829 (UINTN
*) RomShadowedSize
2834 Status
= LegacyBiosCheckPciRomEx (
2835 &Private
->LegacyBios
,
2839 &RuntimeImageLength
,
2844 if (EFI_ERROR (Status
)) {
2846 // There is no PCI ROM in the ROM BAR or no onboard ROM
2848 mVgaInstallationInProgress
= FALSE
;
2849 return EFI_UNSUPPORTED
;
2852 if (*RomImage
== NULL
) {
2854 // If PciHandle is NULL, and no OpRom is to be associated
2856 mVgaInstallationInProgress
= FALSE
;
2857 return EFI_UNSUPPORTED
;
2860 LocalRomImage
= *RomImage
;
2861 Pcir
= (PCI_3_0_DATA_STRUCTURE
*)
2862 ((UINT8
*) LocalRomImage
+ ((PCI_EXPANSION_ROM_HEADER
*) LocalRomImage
)->PcirOffset
);
2863 ImageSize
= Pcir
->ImageLength
* 512;
2864 if (Pcir
->Length
>= 0x1C) {
2865 OpromRevision
= Pcir
->Revision
;
2869 if (Pcir
->Revision
< 3) {
2870 RuntimeImageLength
= 0;
2872 RuntimeImageLength
= Pcir
->MaxRuntimeImageLength
* 512;
2876 // Shadow and initialize the OpROM.
2878 ASSERT (Private
->TraceIndex
< 0x200);
2879 Private
->Trace
[Private
->TraceIndex
] = LEGACY_PCI_TRACE_000
;
2880 Private
->TraceIndex
++;
2881 Private
->TraceIndex
= (UINT16
) (Private
->TraceIndex
% 0x200);
2882 Status
= LegacyBiosInstallRom (
2889 &RuntimeImageLength
,
2894 if (RomShadowedSize
!= NULL
) {
2895 *RomShadowedSize
= (UINT32
) RuntimeImageLength
;
2898 mVgaInstallationInProgress
= FALSE
;