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1 ;------------------------------------------------------------------------------
2 ;
3 ; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
4 ; SPDX-License-Identifier: BSD-2-Clause-Patent
5 ;
6 ; Abstract:
7 ;
8 ;------------------------------------------------------------------------------
9
10
11 SECTION .data
12 ;
13 ; Float control word initial value:
14 ; all exceptions masked, double-precision, round-to-nearest
15 ;
16 ASM_PFX(mFpuControlWord):
17 dw 0x027F
18 ;
19 ; Multimedia-extensions control word:
20 ; all exceptions masked, round-to-nearest, flush to zero for masked underflow
21 ;
22 ASM_PFX(mMmxControlWord):
23 dd 0x01F80
24
25 SECTION .text
26
27 ;
28 ; Initializes floating point units for requirement of UEFI specification.
29 ;
30 ; This function initializes floating-point control word to 0x027F (all exceptions
31 ; masked,double-precision, round-to-nearest) and multimedia-extensions control word
32 ; (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
33 ; for masked underflow).
34 ;
35
36 global ASM_PFX(InitializeFloatingPointUnits)
37 ASM_PFX(InitializeFloatingPointUnits):
38
39
40 push ebx
41
42 ;
43 ; Initialize floating point units
44 ;
45 finit
46 fldcw [ASM_PFX(mFpuControlWord)]
47
48 ;
49 ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
50 ; whether the processor supports SSE instruction.
51 ;
52 mov eax, 1
53 cpuid
54 bt edx, 25
55 jnc Done
56
57 ;
58 ; Set OSFXSR bit 9 in CR4
59 ;
60 mov eax, cr4
61 or eax, BIT9
62 mov cr4, eax
63
64 ;
65 ; The processor should support SSE instruction and we can use
66 ; ldmxcsr instruction
67 ;
68 ldmxcsr [ASM_PFX(mMmxControlWord)]
69 Done:
70 pop ebx
71
72 ret