IntelFsp2Pkg/Include/FspGlobalData.h

   1 /** @file
   2
   3   Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>
   4   SPDX-License-Identifier: BSD-2-Clause-Patent
   5
   6 **/
   7
   8 #ifndef _FSP_GLOBAL_DATA_H_
   9 #define _FSP_GLOBAL_DATA_H_
  10
  11 #include <FspEas.h>
  12
  13 #define FSP_IN_API_MODE          0
  14 #define FSP_IN_DISPATCH_MODE     1
  15 #define FSP_GLOBAL_DATA_VERSION  0x3
  16
  17 #pragma pack(1)
  18
  19 typedef enum {
  20   TempRamInitApiIndex,
  21   FspInitApiIndex,
  22   NotifyPhaseApiIndex,
  23   FspMemoryInitApiIndex,
  24   TempRamExitApiIndex,
  25   FspSiliconInitApiIndex,
  26   FspMultiPhaseSiInitApiIndex,
  27   FspSmmInitApiIndex,
  28   FspMultiPhaseMemInitApiIndex,
  29   FspApiIndexMax
  30 } FSP_API_INDEX;
  31
  32 typedef struct  {
  33   VOID     *DataPtr;
  34   UINTN    MicrocodeRegionBase;
  35   UINTN    MicrocodeRegionSize;
  36   UINTN    CodeRegionBase;
  37   UINTN    CodeRegionSize;
  38   UINTN    Reserved;
  39 } FSP_PLAT_DATA;
  40
  41 #define FSP_GLOBAL_DATA_SIGNATURE        SIGNATURE_32 ('F', 'S', 'P', 'D')
  42 #define FSP_PERFORMANCE_DATA_SIGNATURE   SIGNATURE_32 ('P', 'E', 'R', 'F')
  43 #define FSP_PERFORMANCE_DATA_TIMER_MASK  0xFFFFFFFFFFFFFF
  44
  45 typedef struct  {
  46   UINT32             Signature;
  47   UINT8              Version;
  48   UINT8              Reserved1[3];
  49   ///
  50   /// Offset 0x08
  51   ///
  52   UINTN              CoreStack;
  53   VOID               *SmmInitUpdPtr;
  54   ///
  55   /// IA32: Offset 0x10; X64: Offset 0x18
  56   ///
  57   UINT32             StatusCode;
  58   UINT8              ApiIdx;
  59   ///
  60   /// 0: FSP in API mode; 1: FSP in DISPATCH mode
  61   ///
  62   UINT8              FspMode;
  63   UINT8              OnSeparateStack;
  64   UINT8              Reserved2;
  65   UINT32             NumberOfPhases;
  66   UINT32             PhasesExecuted;
  67   UINT32             Reserved3[8];
  68   ///
  69   /// IA32: Offset 0x40; X64: Offset 0x48
  70   /// Start of UINTN and pointer section
  71   /// All UINTN and pointer members are put in this section
  72   /// for maintaining natural alignment for both IA32 and X64 builds.
  73   ///
  74   FSP_PLAT_DATA      PlatformData;
  75   VOID               *TempRamInitUpdPtr;
  76   VOID               *MemoryInitUpdPtr;
  77   VOID               *SiliconInitUpdPtr;
  78   ///
  79   /// IA32: Offset 0x64; X64: Offset 0x90
  80   /// To store function parameters pointer
  81   /// so it can be retrieved after stack switched.
  82   ///
  83   VOID               *FunctionParameterPtr;
  84   FSP_INFO_HEADER    *FspInfoHeader;
  85   VOID               *UpdDataPtr;
  86   VOID               *FspHobListPtr;
  87   VOID               *VariableRequestParameterPtr;
  88   ///
  89   /// End of UINTN and pointer section
  90   /// At this point, next field offset must be either *0h or *8h to
  91   /// meet natural alignment requirement.
  92   ///
  93   UINT8              Reserved4[16];
  94   UINT32             PerfSig;
  95   UINT16             PerfLen;
  96   UINT16             Reserved5;
  97   UINT32             PerfIdx;
  98   UINT32             Reserved6;
  99   UINT64             PerfData[32];
 100 } FSP_GLOBAL_DATA;
 101
 102 #pragma pack()
 103
 104 #endif