IntelFsp2Pkg/Include/Guid/FspHeaderFile.h

   1 /** @file
   2   Intel FSP Header File definition from Intel Firmware Support Package External
   3   Architecture Specification v2.0 and above.
   4
   5   Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>
   6   SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #include <Base.h>
  11
  12 #ifndef __FSP_HEADER_FILE_H__
  13 #define __FSP_HEADER_FILE_H__
  14
  15 #define FSP_HEADER_REVISION_3  3
  16
  17 #define FSPE_HEADER_REVISION_1  1
  18 #define FSPP_HEADER_REVISION_1  1
  19
  20 ///
  21 /// Fixed FSP header offset in the FSP image
  22 ///
  23 #define FSP_INFO_HEADER_OFF  0x94
  24
  25 #define OFFSET_IN_FSP_INFO_HEADER(x)  (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x
  26
  27 #define FSP_INFO_HEADER_SIGNATURE  SIGNATURE_32 ('F', 'S', 'P', 'H')
  28
  29 #define IMAGE_ATTRIBUTE_GRAPHICS_SUPPORT       BIT0
  30 #define IMAGE_ATTRIBUTE_DISPATCH_MODE_SUPPORT  BIT1
  31 #define IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT     BIT2
  32 #define FSP_IA32                               0
  33 #define FSP_X64                                1
  34
  35   #pragma pack(1)
  36
  37 ///
  38 /// FSP Information Header as described in FSP v2.0 Spec section 5.1.1.
  39 ///
  40 typedef struct {
  41   ///
  42   /// Byte 0x00: Signature ('FSPH') for the FSP Information Header.
  43   ///
  44   UINT32    Signature;
  45   ///
  46   /// Byte 0x04: Length of the FSP Information Header.
  47   ///
  48   UINT32    HeaderLength;
  49   ///
  50   /// Byte 0x08: Reserved.
  51   ///
  52   UINT8     Reserved1[2];
  53   ///
  54   /// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.
  55   ///            For revision v2.4 the value will be 0x24.
  56   ///
  57   UINT8     SpecVersion;
  58   ///
  59   /// Byte 0x0B: Revision of the FSP Information Header.
  60   ///            The Current value for this field is 0x7.
  61   ///
  62   UINT8     HeaderRevision;
  63   ///
  64   /// Byte 0x0C: Revision of the FSP binary.
  65   ///            Major.Minor.Revision.Build
  66   ///            If FSP HeaderRevision is <= 5, the ImageRevision can be decoded as follows:
  67   ///               7 : 0  - Build Number
  68   ///              15 : 8  - Revision
  69   ///              23 : 16 - Minor Version
  70   ///              31 : 24 - Major Version
  71   ///            If FSP HeaderRevision is >= 6, ImageRevision specifies the low-order bytes of the build number and revision
  72   ///            while ExtendedImageRevision specifies the high-order bytes of the build number and revision.
  73   ///               7 : 0  - Low Byte of Build Number
  74   ///              15 : 8  - Low Byte of Revision
  75   ///              23 : 16 - Minor Version
  76   ///              31 : 24 - Major Version
  77   ///
  78   UINT32    ImageRevision;
  79   ///
  80   /// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration.
  81   ///
  82   CHAR8     ImageId[8];
  83   ///
  84   /// Byte 0x18: Size of the entire FSP binary.
  85   ///
  86   UINT32    ImageSize;
  87   ///
  88   /// Byte 0x1C: FSP binary preferred base address.
  89   ///
  90   UINT32    ImageBase;
  91   ///
  92   /// Byte 0x20: Attribute for the FSP binary.
  93   ///   Bit 0: Graphics Support - Set to 1 when FSP supports enabling Graphics Display.
  94   ///   Bit 1: Dispatch Mode Support - Set to 1 when FSP supports the optional Dispatch Mode API defined in Section 7.2 and 9. This bit is only valid if FSP HeaderRevision is >= 4.
  95   ///   Bit 2: 64-bit mode support - Set to 1 to indicate FSP supports 64-bit long mode interfaces. Set to 0 to indicate FSP supports 32-bit mode interfaces. This bit is only valid if FSP HeaderRevision is >= 7.
  96   ///   Bit 3: FSP Variable Services Support - Set to 1 to indicate FSP utilizes the FSP Variable Services defined in Section 9.6 to store non-volatile data. This bit is only valid if FSP HeaderRevision is >= 7.
  97   ///   Bits 15:4 - Reserved
  98   ///
  99   UINT16    ImageAttribute;
 100   ///
 101   /// Byte 0x22: Attributes of the FSP Component.
 102   ///   Bit 0 - Build Type
 103   ///     0 - Debug Build
 104   ///     1 - Release Build
 105   ///   Bit 1 - Release Type
 106   ///     0 - Test Release
 107   ///     1 - Official Release
 108   ///   Bit 11:2 - Reserved
 109   ///   Bits 15:12 - Component Type
 110   ///     0000 - Reserved
 111   ///     0001 - FSP-T
 112   ///     0010 - FSP-M
 113   ///     0011 - FSP-S
 114   ///     0100 - FSP-I (FSP SMM)
 115   ///     0101 to 0111 - Reserved
 116   ///     1000 - FSP-O
 117   ///     1001 to 1111 - Reserved
 118   ///
 119   UINT16    ComponentAttribute;
 120   ///
 121   /// Byte 0x24: Offset of the FSP configuration region.
 122   ///
 123   UINT32    CfgRegionOffset;
 124   ///
 125   /// Byte 0x28: Size of the FSP configuration region.
 126   ///
 127   UINT32    CfgRegionSize;
 128   ///
 129   /// Byte 0x2C: Reserved2.
 130   ///
 131   UINT32    Reserved2;
 132   ///
 133   /// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized.
 134   ///
 135   UINT32    TempRamInitEntryOffset;
 136   ///
 137   /// Byte 0x34: Reserved3.
 138   ///
 139   UINT32    Reserved3;
 140   ///
 141   /// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process.
 142   ///
 143   UINT32    NotifyPhaseEntryOffset;
 144   ///
 145   /// Byte 0x3C: The offset for the API to initialize the memory.
 146   ///
 147   UINT32    FspMemoryInitEntryOffset;
 148   ///
 149   /// Byte 0x40: The offset for the API to tear down temporary RAM.
 150   ///
 151   UINT32    TempRamExitEntryOffset;
 152   ///
 153   /// Byte 0x44: The offset for the API to initialize the CPU and chipset.
 154   ///
 155   UINT32    FspSiliconInitEntryOffset;
 156   ///
 157   /// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization.
 158   ///            This value is only valid if FSP HeaderRevision is >= 5.
 159   ///            If the value is set to 0x00000000, then this API is not available in this component.
 160   ///
 161   UINT32    FspMultiPhaseSiInitEntryOffset;
 162   ///
 163   /// Byte 0x4C: Extended revision of the FSP binary.
 164   ///            This value is only valid if FSP HeaderRevision is >= 6.
 165   ///            ExtendedImageRevision specifies the high-order byte of the revision and build number in the FSP binary revision.
 166   ///               7 : 0 - High Byte of Build Number
 167   ///              15 : 8 - High Byte of Revision
 168   ///            The FSP binary build number can be decoded as follows:
 169   ///            Build Number = (ExtendedImageRevision[7:0] << 8) | ImageRevision[7:0]
 170   ///            Revision = (ExtendedImageRevision[15:8] << 8) | ImageRevision[15:8]
 171   ///            Minor Version = ImageRevision[23:16]
 172   ///            Major Version = ImageRevision[31:24]
 173   ///
 174   UINT16    ExtendedImageRevision;
 175   ///
 176   /// Byte 0x4E: Reserved4.
 177   ///
 178   UINT16    Reserved4;
 179   ///
 180   /// Byte 0x50: Offset for the API for the Multi-Phase memory initialization.
 181   ///
 182   UINT32    FspMultiPhaseMemInitEntryOffset;
 183   ///
 184   /// Byte 0x54: Offset for the API to initialize SMM.
 185   ///
 186   UINT32    FspSmmInitEntryOffset;
 187 } FSP_INFO_HEADER;
 188
 189 ///
 190 /// Signature of the FSP Extended Header
 191 ///
 192 #define FSP_INFO_EXTENDED_HEADER_SIGNATURE  SIGNATURE_32 ('F', 'S', 'P', 'E')
 193
 194 ///
 195 /// FSP Information Extended Header as described in FSP v2.0 Spec section 5.1.2.
 196 ///
 197 typedef struct {
 198   ///
 199   /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header.
 200   ///
 201   UINT32    Signature;
 202   ///
 203   /// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.
 204   ///
 205   UINT32    Length;
 206   ///
 207   /// Byte 0x08: FSP producer defined revision of the table.
 208   ///
 209   UINT8     Revision;
 210   ///
 211   /// Byte 0x09: Reserved for future use.
 212   ///
 213   UINT8     Reserved;
 214   ///
 215   /// Byte 0x0A: FSP producer identification string
 216   ///
 217   CHAR8     FspProducerId[6];
 218   ///
 219   /// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.
 220   ///
 221   UINT32    FspProducerRevision;
 222   ///
 223   /// Byte 0x14: Size of the FSP producer defined data (n) in bytes.
 224   ///
 225   UINT32    FspProducerDataSize;
 226   ///
 227   /// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.
 228   ///
 229 } FSP_INFO_EXTENDED_HEADER;
 230
 231 //
 232 // A generic table search algorithm for additional tables can be implemented with a
 233 // signature search algorithm until a terminator signature 'FSPP' is found.
 234 //
 235 #define FSP_FSPP_SIGNATURE         SIGNATURE_32 ('F', 'S', 'P', 'P')
 236 #define FSP_PATCH_TABLE_SIGNATURE  FSP_FSPP_SIGNATURE
 237
 238 ///
 239 /// FSP Patch Table as described in FSP v2.0 Spec section 5.1.5.
 240 ///
 241 typedef struct {
 242   ///
 243   /// Byte 0x00: FSP Patch Table Signature "FSPP".
 244   ///
 245   UINT32    Signature;
 246   ///
 247   /// Byte 0x04: Size including the PatchData.
 248   ///
 249   UINT16    HeaderLength;
 250   ///
 251   /// Byte 0x06: Revision is set to 0x01.
 252   ///
 253   UINT8     HeaderRevision;
 254   ///
 255   /// Byte 0x07: Reserved for future use.
 256   ///
 257   UINT8     Reserved;
 258   ///
 259   /// Byte 0x08: Number of entries to Patch.
 260   ///
 261   UINT32    PatchEntryNum;
 262   ///
 263   /// Byte 0x0C: Patch Data.
 264   ///
 265   // UINT32  PatchData[];
 266 } FSP_PATCH_TABLE;
 267
 268   #pragma pack()
 269
 270 extern EFI_GUID  gFspHeaderFileGuid;
 271
 272 #endif