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1 /** @file
2 Header file for FSP-M Arch Config PPI for Dispatch mode
3
4 Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
5
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10 #ifndef _FSPM_ARCH_CONFIG_PPI_H_
11 #define _FSPM_ARCH_CONFIG_PPI_H_
12
13 #define FSPM_ARCH_CONFIG_PPI_REVISION 0x1
14
15 ///
16 /// Global ID for the FSPM_ARCH_CONFIG_PPI.
17 ///
18 #define FSPM_ARCH_CONFIG_GUID \
19 { \
20 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \
21 }
22
23 ///
24 /// This PPI provides FSP-M Arch Config PPI.
25 ///
26 typedef struct {
27 ///
28 /// Revision of the structure
29 ///
30 UINT8 Revision;
31 UINT8 Reserved[3];
32 ///
33 /// Pointer to the non-volatile storage (NVS) data buffer.
34 /// If it is NULL it indicates the NVS data is not available.
35 ///
36 VOID *NvsBufferPtr;
37 ///
38 /// Size of memory to be reserved by FSP below "top
39 /// of low usable memory" for bootloader usage.
40 ///
41 UINT32 BootLoaderTolumSize;
42 UINT8 Reserved1[4];
43 } FSPM_ARCH_CONFIG_PPI;
44
45 extern EFI_GUID gFspmArchConfigPpiGuid;
46
47 #endif // _FSPM_ARCH_CONFIG_PPI_H_