ArmPkg: only attempt buildin MmCommunicationDxe for AArch64
[mirror_edk2.git] / IntelFsp2Pkg / IntelFsp2Pkg.dec
1 ## @file\r
2 # Provides driver and definitions to build fsp in EDKII bios.\r
3 #\r
4 # Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>\r
5 # SPDX-License-Identifier: BSD-2-Clause-Patent\r
6 #\r
7 ##\r
8 \r
9 [Defines]\r
10   DEC_SPECIFICATION              = 0x00010005\r
11   PACKAGE_NAME                   = IntelFsp2Pkg\r
12   PACKAGE_GUID                   = A8C53B5E-D556-4F3E-874D-0D6FA2CDC7BF\r
13   PACKAGE_VERSION                = 0.1\r
14 \r
15 [Includes]\r
16   Include\r
17 \r
18 [LibraryClasses]\r
19   ##  @libraryclass  Provides cache-as-ram support.\r
20   CacheAsRamLib|Include/Library/CacheAsRamLib.h\r
21 \r
22   ##  @libraryclass  Provides cache setting on MTRR.\r
23   CacheLib|Include/Library/CacheLib.h\r
24 \r
25   ##  @libraryclass  Provides debug device abstraction.\r
26   DebugDeviceLib|Include/Library/DebugDeviceLib.h\r
27 \r
28   ##  @libraryclass  Provides FSP related services.\r
29   FspCommonLib|Include/Library/FspCommonLib.h\r
30 \r
31   ##  @libraryclass  Provides FSP platform related actions.\r
32   FspPlatformLib|Include/Library/FspPlatformLib.h\r
33 \r
34   ##  @libraryclass  Provides FSP switch stack function.\r
35   FspSwitchStackLib|Include/Library/FspSwitchStackLib.h\r
36 \r
37   ##  @libraryclass  Provides FSP platform sec related actions.\r
38   FspSecPlatformLib|Include/Library/FspSecPlatformLib.h\r
39 \r
40 [Ppis]\r
41   #\r
42   # PPI to indicate FSP is ready to enter notify phase\r
43   # This provides flexibility for any late initialization that must be done right before entering notify phase.\r
44   #\r
45   gFspReadyForNotifyPhasePpiGuid        = { 0xcd167c1e, 0x6e0b, 0x42b3, {0x82, 0xf6, 0xe3, 0xe9, 0x06, 0x19, 0x98, 0x10}}\r
46 \r
47   #\r
48   # PPI as dependency on some modules which only required for API mode\r
49   #\r
50   gFspInApiModePpiGuid                  = { 0xa1eeab87, 0xc859, 0x479d, {0x89, 0xb5, 0x14, 0x61, 0xf4, 0x06, 0x1a, 0x3e}}\r
51 \r
52   #\r
53   # PPI for Architectural configuration data for FSP-M\r
54   #\r
55   gFspmArchConfigPpiGuid                = { 0x824d5a3a, 0xaf92, 0x4c0c, {0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb}}\r
56 \r
57   #\r
58   # PPI to tear down the temporary memory set up by TempRamInit ().\r
59   #\r
60   gFspTempRamExitPpiGuid                = { 0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}\r
61 \r
62 [Guids]\r
63   #\r
64   # GUID defined in package\r
65   #\r
66   gIntelFsp2PkgTokenSpaceGuid           = { 0xed6e0531, 0xf715, 0x4a3d, { 0x9b, 0x12, 0xc1, 0xca, 0x5e, 0xf6, 0x98, 0xa2 } }\r
67 \r
68   # Guid define in FSP EAS\r
69   gFspHeaderFileGuid                    = { 0x912740BE, 0x2284, 0x4734, { 0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C } }\r
70   gFspReservedMemoryResourceHobGuid     = { 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } }\r
71   gFspNonVolatileStorageHobGuid         = { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }\r
72   gFspBootLoaderTolumHobGuid            = { 0x73ff4f56, 0xaa8e, 0x4451, { 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } } # FSP EAS v1.1\r
73 \r
74   gFspPerformanceDataGuid               = { 0x56ed21b6, 0xba23, 0x429e, { 0x89, 0x32, 0x37, 0x6d, 0x8e, 0x18, 0x2e, 0xe3 } }\r
75   gFspEventEndOfFirmwareGuid            = { 0xbd44f629, 0xeae7, 0x4198, { 0x87, 0xf1, 0x39, 0xfa, 0xb0, 0xfd, 0x71, 0x7e } }\r
76 \r
77 [PcdsFixedAtBuild]\r
78   gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress |0xFED00108|UINT32|0x00000001\r
79   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase         |0xFEF00000|UINT32|0x10001001\r
80   gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize         |    0x2000|UINT32|0x10001002\r
81   gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize      |    0x1000|UINT32|0x10001003\r
82   gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize    |     0x100|UINT32|0x10001004\r
83   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry          |        32|UINT32|0x00002001\r
84   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry         |         6|UINT32|0x00002002\r
85   gIntelFsp2PkgTokenSpaceGuid.PcdFspAreaBaseAddress       |0xFFF80000|UINT32|0x10000001\r
86   gIntelFsp2PkgTokenSpaceGuid.PcdFspAreaSize              |0x00040000|UINT32|0x10000002\r
87   gIntelFsp2PkgTokenSpaceGuid.PcdFspBootFirmwareVolumeBase|0xFFF80000|UINT32|0x10000003\r
88   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeaderSpecVersion     |      0x20| UINT8|0x00000002\r
89 \r
90   #\r
91   # x % of FSP temporary memory will be used for heap\r
92   # (100 - x) % of FSP temporary memory will be used for stack\r
93   # 0 means FSP will share the stack with boot loader and FSP temporary memory is heap\r
94   #   Note: This mode assumes boot loader stack is large enough for FSP to use.\r
95   #\r
96   gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage    |        50| UINT8|0x10000004\r
97   #\r
98   # Maximal Interrupt supported in IDT table.\r
99   #\r
100   gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported |        34| UINT8|0x10000005\r
101 \r
102 [PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx]\r
103   gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT32|0x46530000\r
104   gIntelFsp2PkgTokenSpaceGuid.PcdBootLoaderEntry         |0xFFFFFFE4|UINT32|0x46530100\r