IntelFspPkg/FspSecCore/Ia32/InitializeFpu.s

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
   4 # This program and the accompanying materials
   5 # are licensed and made available under the terms and conditions of the BSD License
   6 # which accompanies this distribution.  The full text of the license may be found at
   7 # http://opensource.org/licenses/bsd-license.php.
   8 #
   9 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 #
  12 # Abstract:
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 #
  17 # Float control word initial value:
  18 # all exceptions masked, double-precision, round-to-nearest
  19 #
  20 ASM_PFX(mFpuControlWord): .word     0x027F
  21 #
  22 # Multimedia-extensions control word:
  23 # all exceptions masked, round-to-nearest, flush to zero for masked underflow
  24 #
  25 ASM_PFX(mMmxControlWord): .long     0x01F80
  26
  27
  28
  29 #
  30 # Initializes floating point units for requirement of UEFI specification.
  31 #
  32 # This function initializes floating-point control word to 0x027F (all exceptions
  33 # masked,double-precision, round-to-nearest) and multimedia-extensions control word
  34 # (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero
  35 # for masked underflow).
  36 #
  37 ASM_GLOBAL ASM_PFX(InitializeFloatingPointUnits)
  38 ASM_PFX(InitializeFloatingPointUnits):
  39
  40     pushl   %ebx
  41
  42     #
  43     # Initialize floating point units
  44     #
  45     finit
  46     fldcw   ASM_PFX(mFpuControlWord)
  47
  48     #
  49     # Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
  50     # whether the processor supports SSE instruction.
  51     #
  52     movl    $1,  %eax
  53     cpuid
  54     btl     $25, %edx
  55     jnc     Done
  56
  57     #
  58     # Set OSFXSR bit 9 in CR4
  59     #
  60     movl    %cr4, %eax
  61     or      BIT9, %eax
  62     movl    %eax, %cr4
  63
  64     #
  65     # The processor should support SSE instruction and we can use
  66     # ldmxcsr instruction
  67     #
  68     ldmxcsr ASM_PFX(mMmxControlWord)
  69
  70 Done:
  71     popl    %ebx
  72
  73     ret