2 Intel FSP Info Header definition from Intel Firmware Support Package External
3 Architecture Specification v1.1, April 2015, revision 001.
5 Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #ifndef _FSP_INFO_HEADER_H_
11 #define _FSP_INFO_HEADER_H_
13 #define FSP_HEADER_REVISION_1 1
14 #define FSP_HEADER_REVISION_2 2
16 #define FSPE_HEADER_REVISION_1 1
17 #define FSPP_HEADER_REVISION_1 1
20 /// Fixed FSP header offset in the FSP image
22 #define FSP_INFO_HEADER_OFF 0x94
24 #define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x
26 #define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H')
32 /// Byte 0x00: Signature ('FSPH') for the FSP Information Header
36 /// Byte 0x04: Length of the FSP Information Header
40 /// Byte 0x08: Reserved
44 /// Byte 0x0B: Revision of the FSP Information Header
48 /// Byte 0x0C: Revision of the FSP binary
54 /// Byte 0x10: Signature string that will help match the FSP Binary to a supported
55 /// hardware configuration.
59 /// Byte 0x18: Size of the entire FSP binary
63 /// Byte 0x1C: FSP binary preferred base address
69 /// Byte 0x20: Attribute for the FSP binary
71 UINT32 ImageAttribute
;
73 /// Byte 0x24: Offset of the FSP configuration region
75 UINT32 CfgRegionOffset
;
77 /// Byte 0x28: Size of the FSP configuration region
81 /// Byte 0x2C: Number of API entries this FSP supports
87 /// Byte 0x30: The offset for the API to setup a temporary stack till the memory
90 UINT32 TempRamInitEntryOffset
;
92 /// Byte 0x34: The offset for the API to initialize the CPU and the chipset (SOC)
94 UINT32 FspInitEntryOffset
;
96 /// Byte 0x38: The offset for the API to inform the FSP about the different stages
97 /// in the boot process
99 UINT32 NotifyPhaseEntryOffset
;
102 /// Below fields are added in FSP Revision 2
106 /// Byte 0x3C: The offset for the API to initialize the memory
108 UINT32 FspMemoryInitEntryOffset
;
110 /// Byte 0x40: The offset for the API to tear down temporary RAM
112 UINT32 TempRamExitEntryOffset
;
114 /// Byte 0x44: The offset for the API to initialize the CPU and chipset
116 UINT32 FspSiliconInitEntryOffset
;
121 /// Below structure is added in FSP version 2
123 #define FSP_INFO_EXTENDED_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'E')
127 /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header
131 /// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.
135 /// Byte 0x08: FSP producer defined revision of the table.
139 /// Byte 0x09: Reserved for future use.
143 /// Byte 0x0A: FSP producer identification string
145 CHAR8 FspProducerId
[6];
147 /// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.
149 UINT32 FspProducerRevision
;
151 /// Byte 0x14: Size of the FSP producer defined data (n) in bytes.
153 UINT32 FspProducerDataSize
;
155 /// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.
158 } FSP_INFO_EXTENDED_HEADER
;
161 // A generic table search algorithm for additional tables can be implemented with a
162 // signature search algorithm until a terminator signature 'FSPP' is found.
164 #define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P')