MdeModulePkg/Bus/Ata/AhciPei/AhciPei.h

   1 /** @file
   2   The AhciPei driver is used to manage ATA hard disk device working under AHCI
   3   mode at PEI phase.
   4
   5   Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
   6
   7   SPDX-License-Identifier: BSD-2-Clause-Patent
   8
   9 **/
  10
  11 #ifndef _AHCI_PEI_H_
  12 #define _AHCI_PEI_H_
  13
  14 #include <PiPei.h>
  15
  16 #include <IndustryStandard/Atapi.h>
  17
  18 #include <Ppi/AtaAhciController.h>
  19 #include <Ppi/IoMmu.h>
  20 #include <Ppi/EndOfPeiPhase.h>
  21 #include <Ppi/AtaPassThru.h>
  22 #include <Ppi/BlockIo.h>
  23 #include <Ppi/BlockIo2.h>
  24 #include <Ppi/StorageSecurityCommand.h>
  25
  26 #include <Library/DebugLib.h>
  27 #include <Library/PeiServicesLib.h>
  28 #include <Library/MemoryAllocationLib.h>
  29 #include <Library/BaseMemoryLib.h>
  30 #include <Library/IoLib.h>
  31 #include <Library/TimerLib.h>
  32
  33 //
  34 // Structure forward declarations
  35 //
  36 typedef struct _PEI_AHCI_CONTROLLER_PRIVATE_DATA  PEI_AHCI_CONTROLLER_PRIVATE_DATA;
  37
  38 #include "AhciPeiPassThru.h"
  39 #include "AhciPeiBlockIo.h"
  40 #include "AhciPeiStorageSecurity.h"
  41
  42 //
  43 // ATA AHCI driver implementation related definitions
  44 //
  45 //
  46 // Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.
  47 // The value is in millisecond units. Add a bit of margin for robustness.
  48 //
  49 #define AHCI_BUS_PHY_DETECT_TIMEOUT            15
  50 //
  51 // Refer SATA1.0a spec, the bus reset time should be less than 1s.
  52 // The value is in 100ns units.
  53 //
  54 #define AHCI_PEI_RESET_TIMEOUT                 10000000
  55 //
  56 // Time out Value for ATA pass through protocol, in 100ns units.
  57 //
  58 #define ATA_TIMEOUT                            30000000
  59 //
  60 // Maximal number of Physical Region Descriptor Table entries supported.
  61 //
  62 #define AHCI_MAX_PRDT_NUMBER                   8
  63
  64 #define AHCI_CAPABILITY_OFFSET                 0x0000
  65 #define   AHCI_CAP_SAM                         BIT18
  66 #define   AHCI_CAP_SSS                         BIT27
  67
  68 #define AHCI_GHC_OFFSET                        0x0004
  69 #define   AHCI_GHC_RESET                       BIT0
  70 #define   AHCI_GHC_ENABLE                      BIT31
  71
  72 #define AHCI_IS_OFFSET                         0x0008
  73 #define AHCI_PI_OFFSET                         0x000C
  74
  75 #define AHCI_MAX_PORTS                         32
  76
  77 typedef struct {
  78   UINT32  Lower32;
  79   UINT32  Upper32;
  80 } DATA_32;
  81
  82 typedef union {
  83   DATA_32   Uint32;
  84   UINT64    Uint64;
  85 } DATA_64;
  86
  87 #define AHCI_ATAPI_SIG_MASK                    0xFFFF0000
  88 #define AHCI_ATA_DEVICE_SIG                    0x00000000
  89
  90 //
  91 // Each PRDT entry can point to a memory block up to 4M byte
  92 //
  93 #define AHCI_MAX_DATA_PER_PRDT                 0x400000
  94
  95 #define AHCI_FIS_REGISTER_H2D                  0x27      //Register FIS - Host to Device
  96 #define   AHCI_FIS_REGISTER_H2D_LENGTH         20
  97 #define AHCI_FIS_REGISTER_D2H                  0x34      //Register FIS - Device to Host
  98 #define AHCI_FIS_PIO_SETUP                     0x5F      //PIO Setup FIS - Device to Host
  99
 100 #define AHCI_D2H_FIS_OFFSET                    0x40
 101 #define AHCI_PIO_FIS_OFFSET                    0x20
 102 #define AHCI_FIS_TYPE_MASK                     0xFF
 103
 104 //
 105 // Port register
 106 //
 107 #define AHCI_PORT_START                        0x0100
 108 #define AHCI_PORT_REG_WIDTH                    0x0080
 109 #define AHCI_PORT_CLB                          0x0000
 110 #define AHCI_PORT_CLBU                         0x0004
 111 #define AHCI_PORT_FB                           0x0008
 112 #define AHCI_PORT_FBU                          0x000C
 113 #define AHCI_PORT_IS                           0x0010
 114 #define AHCI_PORT_IE                           0x0014
 115 #define AHCI_PORT_CMD                          0x0018
 116 #define   AHCI_PORT_CMD_ST                     BIT0
 117 #define   AHCI_PORT_CMD_SUD                    BIT1
 118 #define   AHCI_PORT_CMD_POD                    BIT2
 119 #define   AHCI_PORT_CMD_CLO                    BIT3
 120 #define   AHCI_PORT_CMD_FRE                    BIT4
 121 #define   AHCI_PORT_CMD_FR                     BIT14
 122 #define   AHCI_PORT_CMD_CR                     BIT15
 123 #define   AHCI_PORT_CMD_CPD                    BIT20
 124 #define   AHCI_PORT_CMD_ATAPI                  BIT24
 125 #define   AHCI_PORT_CMD_DLAE                   BIT25
 126 #define   AHCI_PORT_CMD_ALPE                   BIT26
 127 #define   AHCI_PORT_CMD_ACTIVE                 (1 << 28)
 128 #define   AHCI_PORT_CMD_ICC_MASK               (BIT28 | BIT29 | BIT30 | BIT31)
 129
 130 #define AHCI_PORT_TFD                          0x0020
 131 #define   AHCI_PORT_TFD_ERR                    BIT0
 132 #define   AHCI_PORT_TFD_DRQ                    BIT3
 133 #define   AHCI_PORT_TFD_BSY                    BIT7
 134 #define   AHCI_PORT_TFD_MASK                   (BIT7 | BIT3 | BIT0)
 135
 136 #define AHCI_PORT_SIG                          0x0024
 137 #define AHCI_PORT_SSTS                         0x0028
 138 #define   AHCI_PORT_SSTS_DET_MASK              0x000F
 139 #define   AHCI_PORT_SSTS_DET                   0x0001
 140 #define   AHCI_PORT_SSTS_DET_PCE               0x0003
 141
 142 #define AHCI_PORT_SCTL                         0x002C
 143 #define   AHCI_PORT_SCTL_IPM_INIT              0x0300
 144
 145 #define AHCI_PORT_SERR                         0x0030
 146 #define AHCI_PORT_CI                           0x0038
 147
 148 #define IS_ALIGNED(addr, size)                 (((UINTN) (addr) & (size - 1)) == 0)
 149 #define TIMER_PERIOD_SECONDS(Seconds)          MultU64x32((UINT64)(Seconds), 10000000)
 150
 151 #pragma pack(1)
 152
 153 //
 154 // Received FIS structure
 155 //
 156 typedef struct {
 157   UINT8     AhciDmaSetupFis[0x1C];         // Dma Setup Fis: offset 0x00
 158   UINT8     AhciDmaSetupFisRsvd[0x04];
 159   UINT8     AhciPioSetupFis[0x14];         // Pio Setup Fis: offset 0x20
 160   UINT8     AhciPioSetupFisRsvd[0x0C];
 161   UINT8     AhciD2HRegisterFis[0x14];      // D2H Register Fis: offset 0x40
 162   UINT8     AhciD2HRegisterFisRsvd[0x04];
 163   UINT64    AhciSetDeviceBitsFis;          // Set Device Bits Fix: offset 0x58
 164   UINT8     AhciUnknownFis[0x40];          // Unkonwn Fis: offset 0x60
 165   UINT8     AhciUnknownFisRsvd[0x60];
 166 } EFI_AHCI_RECEIVED_FIS;
 167
 168 //
 169 // Command List structure includes total 32 entries.
 170 // The entry Data structure is listed at the following.
 171 //
 172 typedef struct {
 173   UINT32    AhciCmdCfl:5;      //Command FIS Length
 174   UINT32    AhciCmdA:1;        //ATAPI
 175   UINT32    AhciCmdW:1;        //Write
 176   UINT32    AhciCmdP:1;        //Prefetchable
 177   UINT32    AhciCmdR:1;        //Reset
 178   UINT32    AhciCmdB:1;        //BIST
 179   UINT32    AhciCmdC:1;        //Clear Busy upon R_OK
 180   UINT32    AhciCmdRsvd:1;
 181   UINT32    AhciCmdPmp:4;      //Port Multiplier Port
 182   UINT32    AhciCmdPrdtl:16;   //Physical Region Descriptor Table Length
 183   UINT32    AhciCmdPrdbc;      //Physical Region Descriptor Byte Count
 184   UINT32    AhciCmdCtba;       //Command Table Descriptor Base Address
 185   UINT32    AhciCmdCtbau;      //Command Table Descriptor Base Address Upper 32-BITs
 186   UINT32    AhciCmdRsvd1[4];
 187 } EFI_AHCI_COMMAND_LIST;
 188
 189 //
 190 // This is a software constructed FIS.
 191 // For Data transfer operations, this is the H2D Register FIS format as
 192 // specified in the Serial ATA Revision 2.6 specification.
 193 //
 194 typedef struct {
 195   UINT8     AhciCFisType;
 196   UINT8     AhciCFisPmNum:4;
 197   UINT8     AhciCFisRsvd:1;
 198   UINT8     AhciCFisRsvd1:1;
 199   UINT8     AhciCFisRsvd2:1;
 200   UINT8     AhciCFisCmdInd:1;
 201   UINT8     AhciCFisCmd;
 202   UINT8     AhciCFisFeature;
 203   UINT8     AhciCFisSecNum;
 204   UINT8     AhciCFisClyLow;
 205   UINT8     AhciCFisClyHigh;
 206   UINT8     AhciCFisDevHead;
 207   UINT8     AhciCFisSecNumExp;
 208   UINT8     AhciCFisClyLowExp;
 209   UINT8     AhciCFisClyHighExp;
 210   UINT8     AhciCFisFeatureExp;
 211   UINT8     AhciCFisSecCount;
 212   UINT8     AhciCFisSecCountExp;
 213   UINT8     AhciCFisRsvd3;
 214   UINT8     AhciCFisControl;
 215   UINT8     AhciCFisRsvd4[4];
 216   UINT8     AhciCFisRsvd5[44];
 217 } EFI_AHCI_COMMAND_FIS;
 218
 219 //
 220 // ACMD: ATAPI command (12 or 16 bytes)
 221 //
 222 typedef struct {
 223   UINT8    AtapiCmd[0x10];
 224 } EFI_AHCI_ATAPI_COMMAND;
 225
 226 //
 227 // Physical Region Descriptor Table includes up to 65535 entries
 228 // The entry data structure is listed at the following.
 229 // the actual entry number comes from the PRDTL field in the command
 230 // list entry for this command slot.
 231 //
 232 typedef struct {
 233   UINT32    AhciPrdtDba;       //Data Base Address
 234   UINT32    AhciPrdtDbau;      //Data Base Address Upper 32-BITs
 235   UINT32    AhciPrdtRsvd;
 236   UINT32    AhciPrdtDbc:22;    //Data Byte Count
 237   UINT32    AhciPrdtRsvd1:9;
 238   UINT32    AhciPrdtIoc:1;     //Interrupt on Completion
 239 } EFI_AHCI_COMMAND_PRDT;
 240
 241 //
 242 // Command table Data strucute which is pointed to by the entry in the command list
 243 //
 244 typedef struct {
 245   EFI_AHCI_COMMAND_FIS      CommandFis;       // A software constructed FIS.
 246   EFI_AHCI_ATAPI_COMMAND    AtapiCmd;         // 12 or 16 bytes ATAPI cmd.
 247   UINT8                     Reserved[0x30];
 248   //
 249   // The scatter/gather list for Data transfer.
 250   //
 251   EFI_AHCI_COMMAND_PRDT     PrdtTable[AHCI_MAX_PRDT_NUMBER];
 252 } EFI_AHCI_COMMAND_TABLE;
 253
 254 #pragma pack()
 255
 256 typedef struct {
 257   EFI_AHCI_RECEIVED_FIS     *AhciRFis;
 258   EFI_AHCI_COMMAND_LIST     *AhciCmdList;
 259   EFI_AHCI_COMMAND_TABLE    *AhciCmdTable;
 260   UINTN                     MaxRFisSize;
 261   UINTN                     MaxCmdListSize;
 262   UINTN                     MaxCmdTableSize;
 263   VOID                      *AhciRFisMap;
 264   VOID                      *AhciCmdListMap;
 265   VOID                      *AhciCmdTableMap;
 266 } EFI_AHCI_REGISTERS;
 267
 268 //
 269 // Unique signature for AHCI ATA device information structure.
 270 //
 271 #define AHCI_PEI_ATA_DEVICE_DATA_SIGNATURE    SIGNATURE_32 ('A', 'P', 'A', 'D')
 272
 273 //
 274 // AHCI mode device information structure.
 275 //
 276 typedef struct {
 277   UINT32                              Signature;
 278   LIST_ENTRY                          Link;
 279
 280   UINT16                              Port;
 281   UINT16                              PortMultiplier;
 282   UINT8                               FisIndex;
 283   UINTN                               DeviceIndex;
 284   ATA_IDENTIFY_DATA                   *IdentifyData;
 285
 286   BOOLEAN                             Lba48Bit;
 287   BOOLEAN                             TrustComputing;
 288   UINTN                               TrustComputingDeviceIndex;
 289   EFI_PEI_BLOCK_IO2_MEDIA             Media;
 290
 291   PEI_AHCI_CONTROLLER_PRIVATE_DATA    *Private;
 292 } PEI_AHCI_ATA_DEVICE_DATA;
 293
 294 #define AHCI_PEI_ATA_DEVICE_INFO_FROM_THIS(a)  \
 295   CR (a,                                       \
 296       PEI_AHCI_ATA_DEVICE_DATA,                \
 297       Link,                                    \
 298       AHCI_PEI_ATA_DEVICE_DATA_SIGNATURE       \
 299       );
 300
 301 //
 302 // Unique signature for private data structure.
 303 //
 304 #define AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE    SIGNATURE_32 ('A','P','C','P')
 305
 306 //
 307 // ATA AHCI controller private data structure.
 308 //
 309 struct _PEI_AHCI_CONTROLLER_PRIVATE_DATA {
 310   UINT32                                Signature;
 311   UINTN                                 MmioBase;
 312   UINTN                                 DevicePathLength;
 313   EFI_DEVICE_PATH_PROTOCOL              *DevicePath;
 314
 315   EFI_ATA_PASS_THRU_MODE                AtaPassThruMode;
 316   EDKII_PEI_ATA_PASS_THRU_PPI           AtaPassThruPpi;
 317   EFI_PEI_RECOVERY_BLOCK_IO_PPI         BlkIoPpi;
 318   EFI_PEI_RECOVERY_BLOCK_IO2_PPI        BlkIo2Ppi;
 319   EDKII_PEI_STORAGE_SECURITY_CMD_PPI    StorageSecurityPpi;
 320   EFI_PEI_PPI_DESCRIPTOR                AtaPassThruPpiList;
 321   EFI_PEI_PPI_DESCRIPTOR                BlkIoPpiList;
 322   EFI_PEI_PPI_DESCRIPTOR                BlkIo2PpiList;
 323   EFI_PEI_PPI_DESCRIPTOR                StorageSecurityPpiList;
 324   EFI_PEI_NOTIFY_DESCRIPTOR             EndOfPeiNotifyList;
 325
 326   EFI_AHCI_REGISTERS                    AhciRegisters;
 327
 328   UINT32                                PortBitMap;
 329   UINT32                                ActiveDevices;
 330   UINT32                                TrustComputingDevices;
 331   LIST_ENTRY                            DeviceList;
 332
 333   UINT16                                PreviousPort;
 334   UINT16                                PreviousPortMultiplier;
 335 };
 336
 337 #define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_PASS_THRU(a)           \
 338   CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, AtaPassThruPpi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
 339 #define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO(a)               \
 340   CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, BlkIoPpi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
 341 #define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_BLKIO2(a)              \
 342   CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, BlkIo2Ppi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
 343 #define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_STROAGE_SECURITY(a)    \
 344   CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, StorageSecurityPpi, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
 345 #define GET_AHCI_PEIM_HC_PRIVATE_DATA_FROM_THIS_NOTIFY(a)              \
 346   CR (a, PEI_AHCI_CONTROLLER_PRIVATE_DATA, EndOfPeiNotifyList, AHCI_PEI_CONTROLLER_PRIVATE_DATA_SIGNATURE)
 347
 348 //
 349 // Global variables
 350 //
 351 extern UINT32    mMaxTransferBlockNumber[2];
 352
 353 //
 354 // Internal functions
 355 //
 356
 357 /**
 358   Allocates pages that are suitable for an OperationBusMasterCommonBuffer or
 359   OperationBusMasterCommonBuffer64 mapping.
 360
 361   @param  Pages                 The number of pages to allocate.
 362   @param  HostAddress           A pointer to store the base system memory address of the
 363                                 allocated range.
 364   @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to
 365                                 access the hosts HostAddress.
 366   @param  Mapping               A resulting value to pass to Unmap().
 367
 368   @retval EFI_SUCCESS           The requested memory pages were allocated.
 369   @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are
 370                                 MEMORY_WRITE_COMBINE and MEMORY_CACHED.
 371   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 372   @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.
 373
 374 **/
 375 EFI_STATUS
 376 IoMmuAllocateBuffer (
 377   IN UINTN                  Pages,
 378   OUT VOID                  **HostAddress,
 379   OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,
 380   OUT VOID                  **Mapping
 381   );
 382
 383 /**
 384   Frees memory that was allocated with AllocateBuffer().
 385
 386   @param  Pages                 The number of pages to free.
 387   @param  HostAddress           The base system memory address of the allocated range.
 388   @param  Mapping               The mapping value returned from Map().
 389
 390   @retval EFI_SUCCESS           The requested memory pages were freed.
 391   @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
 392                                 was not allocated with AllocateBuffer().
 393
 394 **/
 395 EFI_STATUS
 396 IoMmuFreeBuffer (
 397   IN UINTN                  Pages,
 398   IN VOID                   *HostAddress,
 399   IN VOID                   *Mapping
 400   );
 401
 402 /**
 403   Provides the controller-specific addresses required to access system memory from a
 404   DMA bus master.
 405
 406   @param  Operation             Indicates if the bus master is going to read or write to system memory.
 407   @param  HostAddress           The system memory address to map to the PCI controller.
 408   @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes
 409                                 that were mapped.
 410   @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to
 411                                 access the hosts HostAddress.
 412   @param  Mapping               A resulting value to pass to Unmap().
 413
 414   @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.
 415   @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.
 416   @retval EFI_INVALID_PARAMETER One or more parameters are invalid.
 417   @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.
 418   @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.
 419
 420 **/
 421 EFI_STATUS
 422 IoMmuMap (
 423   IN  EDKII_IOMMU_OPERATION Operation,
 424   IN VOID                   *HostAddress,
 425   IN  OUT UINTN             *NumberOfBytes,
 426   OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,
 427   OUT VOID                  **Mapping
 428   );
 429
 430 /**
 431   Completes the Map() operation and releases any corresponding resources.
 432
 433   @param  Mapping               The mapping value returned from Map().
 434
 435   @retval EFI_SUCCESS           The range was unmapped.
 436   @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
 437   @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.
 438 **/
 439 EFI_STATUS
 440 IoMmuUnmap (
 441   IN VOID                  *Mapping
 442   );
 443
 444 /**
 445   One notified function to cleanup the allocated DMA buffers at EndOfPei.
 446
 447   @param[in] PeiServices         Pointer to PEI Services Table.
 448   @param[in] NotifyDescriptor    Pointer to the descriptor for the Notification
 449                                  event that caused this function to execute.
 450   @param[in] Ppi                 Pointer to the PPI data associated with this function.
 451
 452   @retval EFI_SUCCESS    The function completes successfully
 453
 454 **/
 455 EFI_STATUS
 456 EFIAPI
 457 AhciPeimEndOfPei (
 458   IN EFI_PEI_SERVICES           **PeiServices,
 459   IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
 460   IN VOID                       *Ppi
 461   );
 462
 463 /**
 464   Collect the number of bits set within a port bitmap.
 465
 466   @param[in]    PortBitMap    A 32-bit wide bit map of ATA AHCI ports.
 467
 468   @retval The number of bits set in the bitmap.
 469
 470 **/
 471 UINT8
 472 AhciGetNumberOfPortsFromMap (
 473   IN UINT32    PortBitMap
 474   );
 475
 476 /**
 477   Start a PIO Data transfer on specific port.
 478
 479   @param[in]     Private            The pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA.
 480   @param[in]     Port               The number of port.
 481   @param[in]     PortMultiplier     The number of port multiplier.
 482   @param[in]     FisIndex           The offset index of the FIS base address.
 483   @param[in]     Read               The transfer direction.
 484   @param[in]     AtaCommandBlock    The EFI_ATA_COMMAND_BLOCK data.
 485   @param[in,out] AtaStatusBlock     The EFI_ATA_STATUS_BLOCK data.
 486   @param[in,out] MemoryAddr         The pointer to the data buffer.
 487   @param[in]     DataCount          The data count to be transferred.
 488   @param[in]     Timeout            The timeout value of PIO data transfer, uses
 489                                     100ns as a unit.
 490
 491   @retval EFI_DEVICE_ERROR        The PIO data transfer abort with error occurs.
 492   @retval EFI_TIMEOUT             The operation is time out.
 493   @retval EFI_UNSUPPORTED         The device is not ready for transfer.
 494   @retval EFI_OUT_OF_RESOURCES    The operation fails due to lack of resources.
 495   @retval EFI_SUCCESS             The PIO data transfer executes successfully.
 496
 497 **/
 498 EFI_STATUS
 499 AhciPioTransfer (
 500   IN     PEI_AHCI_CONTROLLER_PRIVATE_DATA    *Private,
 501   IN     UINT8                               Port,
 502   IN     UINT8                               PortMultiplier,
 503   IN     UINT8                               FisIndex,
 504   IN     BOOLEAN                             Read,
 505   IN     EFI_ATA_COMMAND_BLOCK               *AtaCommandBlock,
 506   IN OUT EFI_ATA_STATUS_BLOCK                *AtaStatusBlock,
 507   IN OUT VOID                                *MemoryAddr,
 508   IN     UINT32                              DataCount,
 509   IN     UINT64                              Timeout
 510   );
 511
 512 /**
 513   Start a non data transfer on specific port.
 514
 515   @param[in]     Private            The pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA.
 516   @param[in]     Port               The number of port.
 517   @param[in]     PortMultiplier     The number of port multiplier.
 518   @param[in]     FisIndex           The offset index of the FIS base address.
 519   @param[in]     AtaCommandBlock    The EFI_ATA_COMMAND_BLOCK data.
 520   @param[in,out] AtaStatusBlock     The EFI_ATA_STATUS_BLOCK data.
 521   @param[in]     Timeout            The timeout value of non data transfer, uses
 522                                     100ns as a unit.
 523
 524   @retval EFI_DEVICE_ERROR        The non data transfer abort with error occurs.
 525   @retval EFI_TIMEOUT             The operation is time out.
 526   @retval EFI_UNSUPPORTED         The device is not ready for transfer.
 527   @retval EFI_SUCCESS             The non data transfer executes successfully.
 528
 529 **/
 530 EFI_STATUS
 531 AhciNonDataTransfer (
 532   IN     PEI_AHCI_CONTROLLER_PRIVATE_DATA    *Private,
 533   IN     UINT8                               Port,
 534   IN     UINT8                               PortMultiplier,
 535   IN     UINT8                               FisIndex,
 536   IN     EFI_ATA_COMMAND_BLOCK               *AtaCommandBlock,
 537   IN OUT EFI_ATA_STATUS_BLOCK                *AtaStatusBlock,
 538   IN     UINT64                              Timeout
 539   );
 540
 541 /**
 542   Initialize ATA host controller at AHCI mode.
 543
 544   The function is designed to initialize ATA host controller.
 545
 546   @param[in,out] Private    A pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA instance.
 547
 548   @retval EFI_SUCCESS             The ATA AHCI controller is initialized successfully.
 549   @retval EFI_OUT_OF_RESOURCES    Not enough resource to complete while initializing
 550                                   the controller.
 551   @retval Others                  A device error occurred while initializing the
 552                                   controller.
 553
 554 **/
 555 EFI_STATUS
 556 AhciModeInitialization (
 557   IN OUT PEI_AHCI_CONTROLLER_PRIVATE_DATA    *Private
 558   );
 559
 560 /**
 561   Transfer data from ATA device.
 562
 563   This function performs one ATA pass through transaction to transfer data from/to
 564   ATA device. It chooses the appropriate ATA command and protocol to invoke PassThru
 565   interface of ATA pass through.
 566
 567   @param[in]     DeviceData        A pointer to PEI_AHCI_ATA_DEVICE_DATA structure.
 568   @param[in,out] Buffer            The pointer to the current transaction buffer.
 569   @param[in]     StartLba          The starting logical block address to be accessed.
 570   @param[in]     TransferLength    The block number or sector count of the transfer.
 571   @param[in]     IsWrite           Indicates whether it is a write operation.
 572
 573   @retval EFI_SUCCESS    The data transfer is complete successfully.
 574   @return others         Some error occurs when transferring data.
 575
 576 **/
 577 EFI_STATUS
 578 TransferAtaDevice (
 579   IN     PEI_AHCI_ATA_DEVICE_DATA    *DeviceData,
 580   IN OUT VOID                        *Buffer,
 581   IN     EFI_LBA                     StartLba,
 582   IN     UINT32                      TransferLength,
 583   IN     BOOLEAN                     IsWrite
 584   );
 585
 586 /**
 587   Trust transfer data from/to ATA device.
 588
 589   This function performs one ATA pass through transaction to do a trust transfer
 590   from/to ATA device. It chooses the appropriate ATA command and protocol to invoke
 591   PassThru interface of ATA pass through.
 592
 593   @param[in]     DeviceData     Pointer to PEI_AHCI_ATA_DEVICE_DATA structure.
 594   @param[in,out] Buffer         The pointer to the current transaction buffer.
 595   @param[in]     SecurityProtocolId
 596                                 The value of the "Security Protocol" parameter
 597                                 of the security protocol command to be sent.
 598   @param[in]     SecurityProtocolSpecificData
 599                                 The value of the "Security Protocol Specific"
 600                                 parameter of the security protocol command to
 601                                 be sent.
 602   @param[in]     TransferLength The block number or sector count of the transfer.
 603   @param[in]     IsTrustSend    Indicates whether it is a trust send operation
 604                                 or not.
 605   @param[in]     Timeout        The timeout, in 100ns units, to use for the execution
 606                                 of the security protocol command. A Timeout value
 607                                 of 0 means that this function will wait indefinitely
 608                                 for the security protocol command to execute. If
 609                                 Timeout is greater than zero, then this function
 610                                 will return EFI_TIMEOUT if the time required to
 611                                 execute the receive data command is greater than
 612                                 Timeout.
 613   @param[out]    TransferLengthOut
 614                                 A pointer to a buffer to store the size in bytes
 615                                 of the data written to the buffer. Ignore it when
 616                                 IsTrustSend is TRUE.
 617
 618   @retval EFI_SUCCESS    The data transfer is complete successfully.
 619   @return others         Some error occurs when transferring data.
 620
 621 **/
 622 EFI_STATUS
 623 TrustTransferAtaDevice (
 624   IN     PEI_AHCI_ATA_DEVICE_DATA    *DeviceData,
 625   IN OUT VOID                        *Buffer,
 626   IN     UINT8                       SecurityProtocolId,
 627   IN     UINT16                      SecurityProtocolSpecificData,
 628   IN     UINTN                       TransferLength,
 629   IN     BOOLEAN                     IsTrustSend,
 630   IN     UINT64                      Timeout,
 631   OUT    UINTN                       *TransferLengthOut
 632   );
 633
 634 /**
 635   Returns a pointer to the next node in a device path.
 636
 637   If Node is NULL, then ASSERT().
 638
 639   @param  Node    A pointer to a device path node data structure.
 640
 641   @return a pointer to the device path node that follows the device path node
 642   specified by Node.
 643
 644 **/
 645 EFI_DEVICE_PATH_PROTOCOL *
 646 NextDevicePathNode (
 647   IN CONST VOID  *Node
 648   );
 649
 650 /**
 651   Get the size of the current device path instance.
 652
 653   @param[in]  DevicePath             A pointer to the EFI_DEVICE_PATH_PROTOCOL
 654                                      structure.
 655   @param[out] InstanceSize           The size of the current device path instance.
 656   @param[out] EntireDevicePathEnd    Indicate whether the instance is the last
 657                                      one in the device path strucure.
 658
 659   @retval EFI_SUCCESS    The size of the current device path instance is fetched.
 660   @retval Others         Fails to get the size of the current device path instance.
 661
 662 **/
 663 EFI_STATUS
 664 GetDevicePathInstanceSize (
 665   IN  EFI_DEVICE_PATH_PROTOCOL    *DevicePath,
 666   OUT UINTN                       *InstanceSize,
 667   OUT BOOLEAN                     *EntireDevicePathEnd
 668   );
 669
 670 /**
 671   Check the validity of the device path of a ATA AHCI host controller.
 672
 673   @param[in] DevicePath          A pointer to the EFI_DEVICE_PATH_PROTOCOL
 674                                  structure.
 675   @param[in] DevicePathLength    The length of the device path.
 676
 677   @retval EFI_SUCCESS              The device path is valid.
 678   @retval EFI_INVALID_PARAMETER    The device path is invalid.
 679
 680 **/
 681 EFI_STATUS
 682 AhciIsHcDevicePathValid (
 683   IN EFI_DEVICE_PATH_PROTOCOL    *DevicePath,
 684   IN UINTN                       DevicePathLength
 685   );
 686
 687 /**
 688   Build the device path for an ATA device with given port and port multiplier number.
 689
 690   @param[in]  Private               A pointer to the PEI_AHCI_CONTROLLER_PRIVATE_DATA
 691                                     data structure.
 692   @param[in]  Port                  The given port number.
 693   @param[in]  PortMultiplierPort    The given port multiplier number.
 694   @param[out] DevicePathLength      The length of the device path in bytes specified
 695                                     by DevicePath.
 696   @param[out] DevicePath            The device path of ATA device.
 697
 698   @retval EFI_SUCCESS               The operation succeeds.
 699   @retval EFI_INVALID_PARAMETER     The parameters are invalid.
 700   @retval EFI_OUT_OF_RESOURCES      The operation fails due to lack of resources.
 701
 702 **/
 703 EFI_STATUS
 704 AhciBuildDevicePath (
 705   IN  PEI_AHCI_CONTROLLER_PRIVATE_DATA    *Private,
 706   IN  UINT16                              Port,
 707   IN  UINT16                              PortMultiplierPort,
 708   OUT UINTN                               *DevicePathLength,
 709   OUT EFI_DEVICE_PATH_PROTOCOL            **DevicePath
 710   );
 711
 712 /**
 713   Collect the ports that need to be enumerated on a controller for S3 phase.
 714
 715   @param[in]  HcDevicePath          Device path of the controller.
 716   @param[in]  HcDevicePathLength    Length of the device path specified by
 717                                     HcDevicePath.
 718   @param[out] PortBitMap            Bitmap that indicates the ports that need
 719                                     to be enumerated on the controller.
 720
 721   @retval    The number of ports that need to be enumerated.
 722
 723 **/
 724 UINT8
 725 AhciS3GetEumeratePorts (
 726   IN  EFI_DEVICE_PATH_PROTOCOL    *HcDevicePath,
 727   IN  UINTN                       HcDevicePathLength,
 728   OUT UINT32                      *PortBitMap
 729   );
 730
 731 #endif