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[mirror_edk2.git] / MdeModulePkg / Bus / Ata / AtaAtapiPassThru / AhciMode.c
1 /** @file
2 The file for AHCI mode of ATA host controller.
3
4 Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
6 SPDX-License-Identifier: BSD-2-Clause-Patent
7
8 **/
9
10 #include "AtaAtapiPassThru.h"
11
12 /**
13 Read AHCI Operation register.
14
15 @param PciIo The PCI IO protocol instance.
16 @param Offset The operation register offset.
17
18 @return The register content read.
19
20 **/
21 UINT32
22 EFIAPI
23 AhciReadReg (
24 IN EFI_PCI_IO_PROTOCOL *PciIo,
25 IN UINT32 Offset
26 )
27 {
28 UINT32 Data;
29
30 ASSERT (PciIo != NULL);
31
32 Data = 0;
33
34 PciIo->Mem.Read (
35 PciIo,
36 EfiPciIoWidthUint32,
37 EFI_AHCI_BAR_INDEX,
38 (UINT64) Offset,
39 1,
40 &Data
41 );
42
43 return Data;
44 }
45
46 /**
47 Write AHCI Operation register.
48
49 @param PciIo The PCI IO protocol instance.
50 @param Offset The operation register offset.
51 @param Data The data used to write down.
52
53 **/
54 VOID
55 EFIAPI
56 AhciWriteReg (
57 IN EFI_PCI_IO_PROTOCOL *PciIo,
58 IN UINT32 Offset,
59 IN UINT32 Data
60 )
61 {
62 ASSERT (PciIo != NULL);
63
64 PciIo->Mem.Write (
65 PciIo,
66 EfiPciIoWidthUint32,
67 EFI_AHCI_BAR_INDEX,
68 (UINT64) Offset,
69 1,
70 &Data
71 );
72
73 return ;
74 }
75
76 /**
77 Do AND operation with the value of AHCI Operation register.
78
79 @param PciIo The PCI IO protocol instance.
80 @param Offset The operation register offset.
81 @param AndData The data used to do AND operation.
82
83 **/
84 VOID
85 EFIAPI
86 AhciAndReg (
87 IN EFI_PCI_IO_PROTOCOL *PciIo,
88 IN UINT32 Offset,
89 IN UINT32 AndData
90 )
91 {
92 UINT32 Data;
93
94 ASSERT (PciIo != NULL);
95
96 Data = AhciReadReg (PciIo, Offset);
97
98 Data &= AndData;
99
100 AhciWriteReg (PciIo, Offset, Data);
101 }
102
103 /**
104 Do OR operation with the value of AHCI Operation register.
105
106 @param PciIo The PCI IO protocol instance.
107 @param Offset The operation register offset.
108 @param OrData The data used to do OR operation.
109
110 **/
111 VOID
112 EFIAPI
113 AhciOrReg (
114 IN EFI_PCI_IO_PROTOCOL *PciIo,
115 IN UINT32 Offset,
116 IN UINT32 OrData
117 )
118 {
119 UINT32 Data;
120
121 ASSERT (PciIo != NULL);
122
123 Data = AhciReadReg (PciIo, Offset);
124
125 Data |= OrData;
126
127 AhciWriteReg (PciIo, Offset, Data);
128 }
129
130 /**
131 Wait for the value of the specified MMIO register set to the test value.
132
133 @param PciIo The PCI IO protocol instance.
134 @param Offset The MMIO address to test.
135 @param MaskValue The mask value of memory.
136 @param TestValue The test value of memory.
137 @param Timeout The time out value for wait memory set, uses 100ns as a unit.
138
139 @retval EFI_TIMEOUT The MMIO setting is time out.
140 @retval EFI_SUCCESS The MMIO is correct set.
141
142 **/
143 EFI_STATUS
144 EFIAPI
145 AhciWaitMmioSet (
146 IN EFI_PCI_IO_PROTOCOL *PciIo,
147 IN UINTN Offset,
148 IN UINT32 MaskValue,
149 IN UINT32 TestValue,
150 IN UINT64 Timeout
151 )
152 {
153 UINT32 Value;
154 UINT64 Delay;
155 BOOLEAN InfiniteWait;
156
157 if (Timeout == 0) {
158 InfiniteWait = TRUE;
159 } else {
160 InfiniteWait = FALSE;
161 }
162
163 Delay = DivU64x32 (Timeout, 1000) + 1;
164
165 do {
166 //
167 // Access PCI MMIO space to see if the value is the tested one.
168 //
169 Value = AhciReadReg (PciIo, (UINT32) Offset) & MaskValue;
170
171 if (Value == TestValue) {
172 return EFI_SUCCESS;
173 }
174
175 //
176 // Stall for 100 microseconds.
177 //
178 MicroSecondDelay (100);
179
180 Delay--;
181
182 } while (InfiniteWait || (Delay > 0));
183
184 return EFI_TIMEOUT;
185 }
186
187 /**
188 Wait for the value of the specified system memory set to the test value.
189
190 @param Address The system memory address to test.
191 @param MaskValue The mask value of memory.
192 @param TestValue The test value of memory.
193 @param Timeout The time out value for wait memory set, uses 100ns as a unit.
194
195 @retval EFI_TIMEOUT The system memory setting is time out.
196 @retval EFI_SUCCESS The system memory is correct set.
197
198 **/
199 EFI_STATUS
200 EFIAPI
201 AhciWaitMemSet (
202 IN EFI_PHYSICAL_ADDRESS Address,
203 IN UINT32 MaskValue,
204 IN UINT32 TestValue,
205 IN UINT64 Timeout
206 )
207 {
208 UINT32 Value;
209 UINT64 Delay;
210 BOOLEAN InfiniteWait;
211
212 if (Timeout == 0) {
213 InfiniteWait = TRUE;
214 } else {
215 InfiniteWait = FALSE;
216 }
217
218 Delay = DivU64x32 (Timeout, 1000) + 1;
219
220 do {
221 //
222 // Access system memory to see if the value is the tested one.
223 //
224 // The system memory pointed by Address will be updated by the
225 // SATA Host Controller, "volatile" is introduced to prevent
226 // compiler from optimizing the access to the memory address
227 // to only read once.
228 //
229 Value = *(volatile UINT32 *) (UINTN) Address;
230 Value &= MaskValue;
231
232 if (Value == TestValue) {
233 return EFI_SUCCESS;
234 }
235
236 //
237 // Stall for 100 microseconds.
238 //
239 MicroSecondDelay (100);
240
241 Delay--;
242
243 } while (InfiniteWait || (Delay > 0));
244
245 return EFI_TIMEOUT;
246 }
247
248 /**
249 Check the memory status to the test value.
250
251 @param[in] Address The memory address to test.
252 @param[in] MaskValue The mask value of memory.
253 @param[in] TestValue The test value of memory.
254
255 @retval EFI_NOT_READY The memory is not set.
256 @retval EFI_SUCCESS The memory is correct set.
257 **/
258 EFI_STATUS
259 EFIAPI
260 AhciCheckMemSet (
261 IN UINTN Address,
262 IN UINT32 MaskValue,
263 IN UINT32 TestValue
264 )
265 {
266 UINT32 Value;
267
268 Value = *(volatile UINT32 *) Address;
269 Value &= MaskValue;
270
271 if (Value == TestValue) {
272 return EFI_SUCCESS;
273 }
274
275 return EFI_NOT_READY;
276 }
277
278
279 /**
280
281 Clear the port interrupt and error status. It will also clear
282 HBA interrupt status.
283
284 @param PciIo The PCI IO protocol instance.
285 @param Port The number of port.
286
287 **/
288 VOID
289 EFIAPI
290 AhciClearPortStatus (
291 IN EFI_PCI_IO_PROTOCOL *PciIo,
292 IN UINT8 Port
293 )
294 {
295 UINT32 Offset;
296
297 //
298 // Clear any error status
299 //
300 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
301 AhciWriteReg (PciIo, Offset, AhciReadReg (PciIo, Offset));
302
303 //
304 // Clear any port interrupt status
305 //
306 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
307 AhciWriteReg (PciIo, Offset, AhciReadReg (PciIo, Offset));
308
309 //
310 // Clear any HBA interrupt status
311 //
312 AhciWriteReg (PciIo, EFI_AHCI_IS_OFFSET, AhciReadReg (PciIo, EFI_AHCI_IS_OFFSET));
313 }
314
315 /**
316 This function is used to dump the Status Registers and if there is ERR bit set
317 in the Status Register, the Error Register's value is also be dumped.
318
319 @param PciIo The PCI IO protocol instance.
320 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
321 @param Port The number of port.
322 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
323
324 **/
325 VOID
326 EFIAPI
327 AhciDumpPortStatus (
328 IN EFI_PCI_IO_PROTOCOL *PciIo,
329 IN EFI_AHCI_REGISTERS *AhciRegisters,
330 IN UINT8 Port,
331 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
332 )
333 {
334 UINTN Offset;
335 UINT32 Data;
336 UINTN FisBaseAddr;
337 EFI_STATUS Status;
338
339 ASSERT (PciIo != NULL);
340
341 if (AtaStatusBlock != NULL) {
342 ZeroMem (AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
343
344 FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
345 Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
346
347 Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H);
348 if (!EFI_ERROR (Status)) {
349 //
350 // If D2H FIS is received, update StatusBlock with its content.
351 //
352 CopyMem (AtaStatusBlock, (UINT8 *)Offset, sizeof (EFI_ATA_STATUS_BLOCK));
353 } else {
354 //
355 // If D2H FIS is not received, only update Status & Error field through PxTFD
356 // as there is no other way to get the content of the Shadow Register Block.
357 //
358 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
359 Data = AhciReadReg (PciIo, (UINT32)Offset);
360
361 AtaStatusBlock->AtaStatus = (UINT8)Data;
362 if ((AtaStatusBlock->AtaStatus & BIT0) != 0) {
363 AtaStatusBlock->AtaError = (UINT8)(Data >> 8);
364 }
365 }
366 }
367 }
368
369
370 /**
371 Enable the FIS running for giving port.
372
373 @param PciIo The PCI IO protocol instance.
374 @param Port The number of port.
375 @param Timeout The timeout value of enabling FIS, uses 100ns as a unit.
376
377 @retval EFI_DEVICE_ERROR The FIS enable setting fails.
378 @retval EFI_TIMEOUT The FIS enable setting is time out.
379 @retval EFI_SUCCESS The FIS enable successfully.
380
381 **/
382 EFI_STATUS
383 EFIAPI
384 AhciEnableFisReceive (
385 IN EFI_PCI_IO_PROTOCOL *PciIo,
386 IN UINT8 Port,
387 IN UINT64 Timeout
388 )
389 {
390 UINT32 Offset;
391
392 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
393 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);
394
395 return EFI_SUCCESS;
396 }
397
398 /**
399 Disable the FIS running for giving port.
400
401 @param PciIo The PCI IO protocol instance.
402 @param Port The number of port.
403 @param Timeout The timeout value of disabling FIS, uses 100ns as a unit.
404
405 @retval EFI_DEVICE_ERROR The FIS disable setting fails.
406 @retval EFI_TIMEOUT The FIS disable setting is time out.
407 @retval EFI_UNSUPPORTED The port is in running state.
408 @retval EFI_SUCCESS The FIS disable successfully.
409
410 **/
411 EFI_STATUS
412 EFIAPI
413 AhciDisableFisReceive (
414 IN EFI_PCI_IO_PROTOCOL *PciIo,
415 IN UINT8 Port,
416 IN UINT64 Timeout
417 )
418 {
419 UINT32 Offset;
420 UINT32 Data;
421
422 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
423 Data = AhciReadReg (PciIo, Offset);
424
425 //
426 // Before disabling Fis receive, the DMA engine of the port should NOT be in running status.
427 //
428 if ((Data & (EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_CR)) != 0) {
429 return EFI_UNSUPPORTED;
430 }
431
432 //
433 // Check if the Fis receive DMA engine for the port is running.
434 //
435 if ((Data & EFI_AHCI_PORT_CMD_FR) != EFI_AHCI_PORT_CMD_FR) {
436 return EFI_SUCCESS;
437 }
438
439 AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_FRE));
440
441 return AhciWaitMmioSet (
442 PciIo,
443 Offset,
444 EFI_AHCI_PORT_CMD_FR,
445 0,
446 Timeout
447 );
448 }
449
450
451
452 /**
453 Build the command list, command table and prepare the fis receiver.
454
455 @param PciIo The PCI IO protocol instance.
456 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
457 @param Port The number of port.
458 @param PortMultiplier The timeout value of stop.
459 @param CommandFis The control fis will be used for the transfer.
460 @param CommandList The command list will be used for the transfer.
461 @param AtapiCommand The atapi command will be used for the transfer.
462 @param AtapiCommandLength The length of the atapi command.
463 @param CommandSlotNumber The command slot will be used for the transfer.
464 @param DataPhysicalAddr The pointer to the data buffer pci bus master address.
465 @param DataLength The data count to be transferred.
466
467 **/
468 VOID
469 EFIAPI
470 AhciBuildCommand (
471 IN EFI_PCI_IO_PROTOCOL *PciIo,
472 IN EFI_AHCI_REGISTERS *AhciRegisters,
473 IN UINT8 Port,
474 IN UINT8 PortMultiplier,
475 IN EFI_AHCI_COMMAND_FIS *CommandFis,
476 IN EFI_AHCI_COMMAND_LIST *CommandList,
477 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
478 IN UINT8 AtapiCommandLength,
479 IN UINT8 CommandSlotNumber,
480 IN OUT VOID *DataPhysicalAddr,
481 IN UINT32 DataLength
482 )
483 {
484 UINT64 BaseAddr;
485 UINT32 PrdtNumber;
486 UINT32 PrdtIndex;
487 UINTN RemainedData;
488 UINTN MemAddr;
489 DATA_64 Data64;
490 UINT32 Offset;
491
492 //
493 // Filling the PRDT
494 //
495 PrdtNumber = (UINT32)DivU64x32 (((UINT64)DataLength + EFI_AHCI_MAX_DATA_PER_PRDT - 1), EFI_AHCI_MAX_DATA_PER_PRDT);
496
497 //
498 // According to AHCI 1.3 spec, a PRDT entry can point to a maximum 4MB data block.
499 // It also limits that the maximum amount of the PRDT entry in the command table
500 // is 65535.
501 //
502 ASSERT (PrdtNumber <= 65535);
503
504 Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFis) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
505
506 BaseAddr = Data64.Uint64;
507
508 ZeroMem ((VOID *)((UINTN) BaseAddr), sizeof (EFI_AHCI_RECEIVED_FIS));
509
510 ZeroMem (AhciRegisters->AhciCommandTable, sizeof (EFI_AHCI_COMMAND_TABLE));
511
512 CommandFis->AhciCFisPmNum = PortMultiplier;
513
514 CopyMem (&AhciRegisters->AhciCommandTable->CommandFis, CommandFis, sizeof (EFI_AHCI_COMMAND_FIS));
515
516 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
517 if (AtapiCommand != NULL) {
518 CopyMem (
519 &AhciRegisters->AhciCommandTable->AtapiCmd,
520 AtapiCommand,
521 AtapiCommandLength
522 );
523
524 CommandList->AhciCmdA = 1;
525 CommandList->AhciCmdP = 1;
526
527 AhciOrReg (PciIo, Offset, (EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
528 } else {
529 AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
530 }
531
532 RemainedData = (UINTN) DataLength;
533 MemAddr = (UINTN) DataPhysicalAddr;
534 CommandList->AhciCmdPrdtl = PrdtNumber;
535
536 for (PrdtIndex = 0; PrdtIndex < PrdtNumber; PrdtIndex++) {
537 if (RemainedData < EFI_AHCI_MAX_DATA_PER_PRDT) {
538 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = (UINT32)RemainedData - 1;
539 } else {
540 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = EFI_AHCI_MAX_DATA_PER_PRDT - 1;
541 }
542
543 Data64.Uint64 = (UINT64)MemAddr;
544 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDba = Data64.Uint32.Lower32;
545 AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbau = Data64.Uint32.Upper32;
546 RemainedData -= EFI_AHCI_MAX_DATA_PER_PRDT;
547 MemAddr += EFI_AHCI_MAX_DATA_PER_PRDT;
548 }
549
550 //
551 // Set the last PRDT to Interrupt On Complete
552 //
553 if (PrdtNumber > 0) {
554 AhciRegisters->AhciCommandTable->PrdtTable[PrdtNumber - 1].AhciPrdtIoc = 1;
555 }
556
557 CopyMem (
558 (VOID *) ((UINTN) AhciRegisters->AhciCmdList + (UINTN) CommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST)),
559 CommandList,
560 sizeof (EFI_AHCI_COMMAND_LIST)
561 );
562
563 Data64.Uint64 = (UINT64)(UINTN) AhciRegisters->AhciCommandTablePciAddr;
564 AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtba = Data64.Uint32.Lower32;
565 AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtbau = Data64.Uint32.Upper32;
566 AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdPmp = PortMultiplier;
567
568 }
569
570 /**
571 Build a command FIS.
572
573 @param CmdFis A pointer to the EFI_AHCI_COMMAND_FIS data structure.
574 @param AtaCommandBlock A pointer to the AhciBuildCommandFis data structure.
575
576 **/
577 VOID
578 EFIAPI
579 AhciBuildCommandFis (
580 IN OUT EFI_AHCI_COMMAND_FIS *CmdFis,
581 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock
582 )
583 {
584 ZeroMem (CmdFis, sizeof (EFI_AHCI_COMMAND_FIS));
585
586 CmdFis->AhciCFisType = EFI_AHCI_FIS_REGISTER_H2D;
587 //
588 // Indicator it's a command
589 //
590 CmdFis->AhciCFisCmdInd = 0x1;
591 CmdFis->AhciCFisCmd = AtaCommandBlock->AtaCommand;
592
593 CmdFis->AhciCFisFeature = AtaCommandBlock->AtaFeatures;
594 CmdFis->AhciCFisFeatureExp = AtaCommandBlock->AtaFeaturesExp;
595
596 CmdFis->AhciCFisSecNum = AtaCommandBlock->AtaSectorNumber;
597 CmdFis->AhciCFisSecNumExp = AtaCommandBlock->AtaSectorNumberExp;
598
599 CmdFis->AhciCFisClyLow = AtaCommandBlock->AtaCylinderLow;
600 CmdFis->AhciCFisClyLowExp = AtaCommandBlock->AtaCylinderLowExp;
601
602 CmdFis->AhciCFisClyHigh = AtaCommandBlock->AtaCylinderHigh;
603 CmdFis->AhciCFisClyHighExp = AtaCommandBlock->AtaCylinderHighExp;
604
605 CmdFis->AhciCFisSecCount = AtaCommandBlock->AtaSectorCount;
606 CmdFis->AhciCFisSecCountExp = AtaCommandBlock->AtaSectorCountExp;
607
608 CmdFis->AhciCFisDevHead = (UINT8) (AtaCommandBlock->AtaDeviceHead | 0xE0);
609 }
610
611 /**
612 Wait until SATA device reports it is ready for operation.
613
614 @param[in] PciIo Pointer to AHCI controller PciIo.
615 @param[in] Port SATA port index on which to reset.
616
617 @retval EFI_SUCCESS Device ready for operation.
618 @retval EFI_TIMEOUT Device failed to get ready within required period.
619 **/
620 EFI_STATUS
621 AhciWaitDeviceReady (
622 IN EFI_PCI_IO_PROTOCOL *PciIo,
623 IN UINT8 Port
624 )
625 {
626 UINT32 PhyDetectDelay;
627 UINT32 Data;
628 UINT32 Offset;
629
630 //
631 // According to SATA1.0a spec section 5.2, we need to wait for PxTFD.BSY and PxTFD.DRQ
632 // and PxTFD.ERR to be zero. The maximum wait time is 16s which is defined at ATA spec.
633 //
634 PhyDetectDelay = 16 * 1000;
635 do {
636 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
637 if (AhciReadReg(PciIo, Offset) != 0) {
638 AhciWriteReg (PciIo, Offset, AhciReadReg(PciIo, Offset));
639 }
640 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
641
642 Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_TFD_MASK;
643 if (Data == 0) {
644 break;
645 }
646
647 MicroSecondDelay (1000);
648 PhyDetectDelay--;
649 } while (PhyDetectDelay > 0);
650
651 if (PhyDetectDelay == 0) {
652 DEBUG ((DEBUG_ERROR, "Port %d Device not ready (TFD=0x%X)\n", Port, Data));
653 return EFI_TIMEOUT;
654 } else {
655 return EFI_SUCCESS;
656 }
657 }
658
659
660 /**
661 Reset the SATA port. Algorithm follows AHCI spec 1.3.1 section 10.4.2
662
663 @param[in] PciIo Pointer to AHCI controller PciIo.
664 @param[in] Port SATA port index on which to reset.
665
666 @retval EFI_SUCCESS Port reset.
667 @retval Others Failed to reset the port.
668 **/
669 EFI_STATUS
670 AhciResetPort (
671 IN EFI_PCI_IO_PROTOCOL *PciIo,
672 IN UINT8 Port
673 )
674 {
675 UINT32 Offset;
676 EFI_STATUS Status;
677
678 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;
679 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_SCTL_DET_INIT);
680 //
681 // SW is required to keep DET set to 0x1 at least for 1 milisecond to ensure that
682 // at least one COMRESET signal is sent.
683 //
684 MicroSecondDelay(1000);
685 AhciAndReg (PciIo, Offset, ~(UINT32)EFI_AHCI_PORT_SSTS_DET_MASK);
686
687 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
688 Status = AhciWaitMmioSet (PciIo, Offset, EFI_AHCI_PORT_SSTS_DET_MASK, EFI_AHCI_PORT_SSTS_DET_PCE, ATA_ATAPI_TIMEOUT);
689 if (EFI_ERROR (Status)) {
690 return Status;
691 }
692
693 return AhciWaitDeviceReady (PciIo, Port);
694 }
695
696 /**
697 Recovers the SATA port from error condition.
698 This function implements algorithm described in
699 AHCI spec 1.3.1 section 6.2.2
700
701 @param[in] PciIo Pointer to AHCI controller PciIo.
702 @param[in] Port SATA port index on which to check.
703
704 @retval EFI_SUCCESS Port recovered.
705 @retval Others Failed to recover port.
706 **/
707 EFI_STATUS
708 AhciRecoverPortError (
709 IN EFI_PCI_IO_PROTOCOL *PciIo,
710 IN UINT8 Port
711 )
712 {
713 UINT32 Offset;
714 UINT32 PortInterrupt;
715 UINT32 PortTfd;
716 EFI_STATUS Status;
717
718 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
719 PortInterrupt = AhciReadReg (PciIo, Offset);
720 if ((PortInterrupt & EFI_AHCI_PORT_IS_FATAL_ERROR_MASK) == 0) {
721 //
722 // No fatal error detected. Exit with success as port should still be operational.
723 // No need to clear IS as it will be cleared when the next command starts.
724 //
725 return EFI_SUCCESS;
726 }
727
728 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
729 AhciAndReg (PciIo, Offset, ~(UINT32)EFI_AHCI_PORT_CMD_ST);
730
731 Status = AhciWaitMmioSet (PciIo, Offset, EFI_AHCI_PORT_CMD_CR, 0, ATA_ATAPI_TIMEOUT);
732 if (EFI_ERROR (Status)) {
733 DEBUG ((DEBUG_ERROR, "Ahci port %d is in hung state, aborting recovery\n", Port));
734 return Status;
735 }
736
737 //
738 // If TFD.BSY or TFD.DRQ is still set it means that drive is hung and software has
739 // to reset it before sending any additional commands.
740 //
741 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
742 PortTfd = AhciReadReg (PciIo, Offset);
743 if ((PortTfd & (EFI_AHCI_PORT_TFD_BSY | EFI_AHCI_PORT_TFD_DRQ)) != 0) {
744 Status = AhciResetPort (PciIo, Port);
745 if (EFI_ERROR (Status)) {
746 DEBUG ((DEBUG_ERROR, "Failed to reset the port %d\n", Port));
747 }
748 }
749
750 return EFI_SUCCESS;
751 }
752
753 /**
754 Checks if specified FIS has been received.
755
756 @param[in] PciIo Pointer to AHCI controller PciIo.
757 @param[in] Port SATA port index on which to check.
758 @param[in] FisType FIS type for which to check.
759
760 @retval EFI_SUCCESS FIS received.
761 @retval EFI_NOT_READY FIS not received yet.
762 @retval EFI_DEVICE_ERROR AHCI controller reported an error on port.
763 **/
764 EFI_STATUS
765 AhciCheckFisReceived (
766 IN EFI_PCI_IO_PROTOCOL *PciIo,
767 IN UINT8 Port,
768 IN SATA_FIS_TYPE FisType
769 )
770 {
771 UINT32 Offset;
772 UINT32 PortInterrupt;
773 UINT32 PortTfd;
774
775 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
776 PortInterrupt = AhciReadReg (PciIo, Offset);
777 if ((PortInterrupt & EFI_AHCI_PORT_IS_ERROR_MASK) != 0) {
778 DEBUG ((DEBUG_ERROR, "AHCI: Error interrupt reported PxIS: %X\n", PortInterrupt));
779 return EFI_DEVICE_ERROR;
780 }
781 //
782 // For PIO setup FIS - According to SATA 2.6 spec section 11.7, D2h FIS means an error encountered.
783 // But Qemu and Marvel 9230 sata controller may just receive a D2h FIS from device
784 // after the transaction is finished successfully.
785 // To get better device compatibilities, we further check if the PxTFD's ERR bit is set.
786 // By this way, we can know if there is a real error happened.
787 //
788 if (((FisType == SataFisD2H) && ((PortInterrupt & EFI_AHCI_PORT_IS_DHRS) != 0)) ||
789 ((FisType == SataFisPioSetup) && (PortInterrupt & (EFI_AHCI_PORT_IS_PSS | EFI_AHCI_PORT_IS_DHRS)) != 0) ||
790 ((FisType == SataFisDmaSetup) && (PortInterrupt & (EFI_AHCI_PORT_IS_DSS | EFI_AHCI_PORT_IS_DHRS)) != 0)) {
791 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
792 PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
793 if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
794 return EFI_DEVICE_ERROR;
795 } else {
796 return EFI_SUCCESS;
797 }
798 }
799
800 return EFI_NOT_READY;
801 }
802
803 /**
804 Waits until specified FIS has been received.
805
806 @param[in] PciIo Pointer to AHCI controller PciIo.
807 @param[in] Port SATA port index on which to check.
808 @param[in] Timeout Time after which function should stop polling.
809 @param[in] FisType FIS type for which to check.
810
811 @retval EFI_SUCCESS FIS received.
812 @retval EFI_TIMEOUT FIS failed to arrive within a specified time period.
813 @retval EFI_DEVICE_ERROR AHCI controller reported an error on port.
814 **/
815 EFI_STATUS
816 AhciWaitUntilFisReceived (
817 IN EFI_PCI_IO_PROTOCOL *PciIo,
818 IN UINT8 Port,
819 IN UINT64 Timeout,
820 IN SATA_FIS_TYPE FisType
821 )
822 {
823 EFI_STATUS Status;
824 BOOLEAN InfiniteWait;
825 UINT64 Delay;
826
827 Delay = DivU64x32 (Timeout, 1000) + 1;
828 if (Timeout == 0) {
829 InfiniteWait = TRUE;
830 } else {
831 InfiniteWait = FALSE;
832 }
833
834 do {
835 Status = AhciCheckFisReceived (PciIo, Port, FisType);
836 if (Status != EFI_NOT_READY) {
837 return Status;
838 }
839 //
840 // Stall for 100 microseconds.
841 //
842 MicroSecondDelay (100);
843 Delay--;
844 } while (InfiniteWait || (Delay > 0));
845
846 return EFI_TIMEOUT;
847 }
848
849 /**
850 Prints contents of the ATA command block into the debug port.
851
852 @param[in] AtaCommandBlock AtaCommandBlock to print.
853 @param[in] DebugLevel Debug level on which to print.
854 **/
855 VOID
856 AhciPrintCommandBlock (
857 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
858 IN UINT32 DebugLevel
859 )
860 {
861 DEBUG ((DebugLevel, "ATA COMMAND BLOCK:\n"));
862 DEBUG ((DebugLevel, "AtaCommand: %d\n", AtaCommandBlock->AtaCommand));
863 DEBUG ((DebugLevel, "AtaFeatures: %X\n", AtaCommandBlock->AtaFeatures));
864 DEBUG ((DebugLevel, "AtaSectorNumber: %d\n", AtaCommandBlock->AtaSectorNumber));
865 DEBUG ((DebugLevel, "AtaCylinderLow: %X\n", AtaCommandBlock->AtaCylinderHigh));
866 DEBUG ((DebugLevel, "AtaCylinderHigh: %X\n", AtaCommandBlock->AtaCylinderHigh));
867 DEBUG ((DebugLevel, "AtaDeviceHead: %d\n", AtaCommandBlock->AtaDeviceHead));
868 DEBUG ((DebugLevel, "AtaSectorNumberExp: %d\n", AtaCommandBlock->AtaSectorNumberExp));
869 DEBUG ((DebugLevel, "AtaCylinderLowExp: %X\n", AtaCommandBlock->AtaCylinderLowExp));
870 DEBUG ((DebugLevel, "AtaCylinderHighExp: %X\n", AtaCommandBlock->AtaCylinderHighExp));
871 DEBUG ((DebugLevel, "AtaFeaturesExp: %X\n", AtaCommandBlock->AtaFeaturesExp));
872 DEBUG ((DebugLevel, "AtaSectorCount: %d\n", AtaCommandBlock->AtaSectorCount));
873 DEBUG ((DebugLevel, "AtaSectorCountExp: %d\n", AtaCommandBlock->AtaSectorCountExp));
874 }
875
876 /**
877 Prints contents of the ATA status block into the debug port.
878
879 @param[in] AtaStatusBlock AtaStatusBlock to print.
880 @param[in] DebugLevel Debug level on which to print.
881 **/
882 VOID
883 AhciPrintStatusBlock (
884 IN EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
885 IN UINT32 DebugLevel
886 )
887 {
888 //
889 // Only print status and error since we have all of the rest printed as
890 // a part of command block print.
891 //
892 DEBUG ((DebugLevel, "ATA STATUS BLOCK:\n"));
893 DEBUG ((DebugLevel, "AtaStatus: %d\n", AtaStatusBlock->AtaStatus));
894 DEBUG ((DebugLevel, "AtaError: %d\n", AtaStatusBlock->AtaError));
895 }
896
897 /**
898 Start a PIO data transfer on specific port.
899
900 @param[in] PciIo The PCI IO protocol instance.
901 @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
902 @param[in] Port The number of port.
903 @param[in] PortMultiplier The timeout value of stop.
904 @param[in] AtapiCommand The atapi command will be used for the
905 transfer.
906 @param[in] AtapiCommandLength The length of the atapi command.
907 @param[in] Read The transfer direction.
908 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
909 @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
910 @param[in, out] MemoryAddr The pointer to the data buffer.
911 @param[in] DataCount The data count to be transferred.
912 @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
913 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
914 used by non-blocking mode.
915
916 @retval EFI_DEVICE_ERROR The PIO data transfer abort with error occurs.
917 @retval EFI_TIMEOUT The operation is time out.
918 @retval EFI_UNSUPPORTED The device is not ready for transfer.
919 @retval EFI_SUCCESS The PIO data transfer executes successfully.
920
921 **/
922 EFI_STATUS
923 EFIAPI
924 AhciPioTransfer (
925 IN EFI_PCI_IO_PROTOCOL *PciIo,
926 IN EFI_AHCI_REGISTERS *AhciRegisters,
927 IN UINT8 Port,
928 IN UINT8 PortMultiplier,
929 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
930 IN UINT8 AtapiCommandLength,
931 IN BOOLEAN Read,
932 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
933 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
934 IN OUT VOID *MemoryAddr,
935 IN UINT32 DataCount,
936 IN UINT64 Timeout,
937 IN ATA_NONBLOCK_TASK *Task
938 )
939 {
940 EFI_STATUS Status;
941 EFI_PHYSICAL_ADDRESS PhyAddr;
942 VOID *Map;
943 UINTN MapLength;
944 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
945 EFI_AHCI_COMMAND_FIS CFis;
946 EFI_AHCI_COMMAND_LIST CmdList;
947 UINT32 PrdCount;
948 UINT32 Retry;
949
950 if (Read) {
951 Flag = EfiPciIoOperationBusMasterWrite;
952 } else {
953 Flag = EfiPciIoOperationBusMasterRead;
954 }
955
956 //
957 // construct command list and command table with pci bus address
958 //
959 MapLength = DataCount;
960 Status = PciIo->Map (
961 PciIo,
962 Flag,
963 MemoryAddr,
964 &MapLength,
965 &PhyAddr,
966 &Map
967 );
968
969 if (EFI_ERROR (Status) || (DataCount != MapLength)) {
970 return EFI_BAD_BUFFER_SIZE;
971 }
972
973 //
974 // Package read needed
975 //
976 AhciBuildCommandFis (&CFis, AtaCommandBlock);
977
978 ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
979
980 CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
981 CmdList.AhciCmdW = Read ? 0 : 1;
982
983 for (Retry = 0; Retry < AHCI_COMMAND_RETRIES; Retry++) {
984 AhciBuildCommand (
985 PciIo,
986 AhciRegisters,
987 Port,
988 PortMultiplier,
989 &CFis,
990 &CmdList,
991 AtapiCommand,
992 AtapiCommandLength,
993 0,
994 (VOID *)(UINTN)PhyAddr,
995 DataCount
996 );
997
998 DEBUG ((DEBUG_VERBOSE, "Starting command for PIO transfer:\n"));
999 AhciPrintCommandBlock (AtaCommandBlock, DEBUG_VERBOSE);
1000 Status = AhciStartCommand (
1001 PciIo,
1002 Port,
1003 0,
1004 Timeout
1005 );
1006 if (EFI_ERROR (Status)) {
1007 break;
1008 }
1009
1010 if (Read && (AtapiCommand == 0)) {
1011 Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisPioSetup);
1012 if (Status == EFI_SUCCESS) {
1013 PrdCount = *(volatile UINT32 *) (&(AhciRegisters->AhciCmdList[0].AhciCmdPrdbc));
1014 if (PrdCount == DataCount) {
1015 Status = EFI_SUCCESS;
1016 } else {
1017 Status = EFI_DEVICE_ERROR;
1018 }
1019 }
1020 } else {
1021 Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisD2H);
1022 }
1023
1024 if (Status == EFI_DEVICE_ERROR) {
1025 DEBUG ((DEBUG_ERROR, "PIO command failed at retry %d\n", Retry));
1026 Status = AhciRecoverPortError (PciIo, Port);
1027 if (EFI_ERROR (Status)) {
1028 break;
1029 }
1030 } else {
1031 break;
1032 }
1033 }
1034
1035 AhciStopCommand (
1036 PciIo,
1037 Port,
1038 Timeout
1039 );
1040
1041 AhciDisableFisReceive (
1042 PciIo,
1043 Port,
1044 Timeout
1045 );
1046
1047 PciIo->Unmap (
1048 PciIo,
1049 Map
1050 );
1051
1052 AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);
1053
1054 if (Status == EFI_DEVICE_ERROR) {
1055 DEBUG ((DEBUG_ERROR, "Failed to execute command for PIO transfer:\n"));
1056 //
1057 // Repeat command block here to make sure it is printed on
1058 // device error debug level.
1059 //
1060 AhciPrintCommandBlock (AtaCommandBlock, DEBUG_ERROR);
1061 AhciPrintStatusBlock (AtaStatusBlock, DEBUG_ERROR);
1062 } else {
1063 AhciPrintStatusBlock (AtaStatusBlock, DEBUG_VERBOSE);
1064 }
1065
1066 return Status;
1067 }
1068
1069 /**
1070 Start a DMA data transfer on specific port
1071
1072 @param[in] Instance The ATA_ATAPI_PASS_THRU_INSTANCE protocol instance.
1073 @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1074 @param[in] Port The number of port.
1075 @param[in] PortMultiplier The timeout value of stop.
1076 @param[in] AtapiCommand The atapi command will be used for the
1077 transfer.
1078 @param[in] AtapiCommandLength The length of the atapi command.
1079 @param[in] Read The transfer direction.
1080 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
1081 @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
1082 @param[in, out] MemoryAddr The pointer to the data buffer.
1083 @param[in] DataCount The data count to be transferred.
1084 @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
1085 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1086 used by non-blocking mode.
1087
1088 @retval EFI_DEVICE_ERROR The DMA data transfer abort with error occurs.
1089 @retval EFI_TIMEOUT The operation is time out.
1090 @retval EFI_UNSUPPORTED The device is not ready for transfer.
1091 @retval EFI_SUCCESS The DMA data transfer executes successfully.
1092
1093 **/
1094 EFI_STATUS
1095 EFIAPI
1096 AhciDmaTransfer (
1097 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
1098 IN EFI_AHCI_REGISTERS *AhciRegisters,
1099 IN UINT8 Port,
1100 IN UINT8 PortMultiplier,
1101 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
1102 IN UINT8 AtapiCommandLength,
1103 IN BOOLEAN Read,
1104 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1105 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
1106 IN OUT VOID *MemoryAddr,
1107 IN UINT32 DataCount,
1108 IN UINT64 Timeout,
1109 IN ATA_NONBLOCK_TASK *Task
1110 )
1111 {
1112 EFI_STATUS Status;
1113 EFI_PHYSICAL_ADDRESS PhyAddr;
1114 VOID *Map;
1115 UINTN MapLength;
1116 EFI_PCI_IO_PROTOCOL_OPERATION Flag;
1117 EFI_AHCI_COMMAND_FIS CFis;
1118 EFI_AHCI_COMMAND_LIST CmdList;
1119 EFI_PCI_IO_PROTOCOL *PciIo;
1120 EFI_TPL OldTpl;
1121 UINT32 Retry;
1122
1123 Map = NULL;
1124 PciIo = Instance->PciIo;
1125
1126 if (PciIo == NULL) {
1127 return EFI_INVALID_PARAMETER;
1128 }
1129
1130 //
1131 // Set Status to suppress incorrect compiler/analyzer warnings
1132 //
1133 Status = EFI_SUCCESS;
1134
1135 //
1136 // DMA buffer allocation. Needs to be done only once for both sync and async
1137 // DMA transfers irrespective of number of retries.
1138 //
1139 if ((Task == NULL) || ((Task != NULL) && (Task->Map == NULL))) {
1140 if (Read) {
1141 Flag = EfiPciIoOperationBusMasterWrite;
1142 } else {
1143 Flag = EfiPciIoOperationBusMasterRead;
1144 }
1145
1146 MapLength = DataCount;
1147 Status = PciIo->Map (
1148 PciIo,
1149 Flag,
1150 MemoryAddr,
1151 &MapLength,
1152 &PhyAddr,
1153 &Map
1154 );
1155
1156 if (EFI_ERROR (Status) || (DataCount != MapLength)) {
1157 return EFI_BAD_BUFFER_SIZE;
1158 }
1159 if (Task != NULL) {
1160 Task->Map = Map;
1161 }
1162 }
1163
1164 if (Task == NULL || (Task != NULL && !Task->IsStart)) {
1165 AhciBuildCommandFis (&CFis, AtaCommandBlock);
1166
1167 ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
1168
1169 CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
1170 CmdList.AhciCmdW = Read ? 0 : 1;
1171 }
1172
1173 if (Task == NULL) {
1174 //
1175 // Before starting the Blocking BlockIO operation, push to finish all non-blocking
1176 // BlockIO tasks.
1177 // Delay 100us to simulate the blocking time out checking.
1178 //
1179 OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
1180 while (!IsListEmpty (&Instance->NonBlockingTaskList)) {
1181 AsyncNonBlockingTransferRoutine (NULL, Instance);
1182 //
1183 // Stall for 100us.
1184 //
1185 MicroSecondDelay (100);
1186 }
1187 gBS->RestoreTPL (OldTpl);
1188 for (Retry = 0; Retry < AHCI_COMMAND_RETRIES; Retry++) {
1189 AhciBuildCommand (
1190 PciIo,
1191 AhciRegisters,
1192 Port,
1193 PortMultiplier,
1194 &CFis,
1195 &CmdList,
1196 AtapiCommand,
1197 AtapiCommandLength,
1198 0,
1199 (VOID *)(UINTN)PhyAddr,
1200 DataCount
1201 );
1202
1203 DEBUG ((DEBUG_VERBOSE, "Starting command for sync DMA transfer:\n"));
1204 AhciPrintCommandBlock (AtaCommandBlock, DEBUG_VERBOSE);
1205 Status = AhciStartCommand (
1206 PciIo,
1207 Port,
1208 0,
1209 Timeout
1210 );
1211 if (EFI_ERROR (Status)) {
1212 break;
1213 }
1214 Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisD2H);
1215 if (Status == EFI_DEVICE_ERROR) {
1216 DEBUG ((DEBUG_ERROR, "DMA command failed at retry: %d\n", Retry));
1217 Status = AhciRecoverPortError (PciIo, Port);
1218 if (EFI_ERROR (Status)) {
1219 break;
1220 }
1221 } else {
1222 break;
1223 }
1224 }
1225 } else {
1226 if (!Task->IsStart) {
1227 AhciBuildCommand (
1228 PciIo,
1229 AhciRegisters,
1230 Port,
1231 PortMultiplier,
1232 &CFis,
1233 &CmdList,
1234 AtapiCommand,
1235 AtapiCommandLength,
1236 0,
1237 (VOID *)(UINTN)PhyAddr,
1238 DataCount
1239 );
1240
1241 DEBUG ((DEBUG_VERBOSE, "Starting command for async DMA transfer:\n"));
1242 AhciPrintCommandBlock (AtaCommandBlock, DEBUG_VERBOSE);
1243 Status = AhciStartCommand (
1244 PciIo,
1245 Port,
1246 0,
1247 Timeout
1248 );
1249 if (!EFI_ERROR (Status)) {
1250 Task->IsStart = TRUE;
1251 }
1252 }
1253 if (Task->IsStart) {
1254 Status = AhciCheckFisReceived (PciIo, Port, SataFisD2H);
1255 if (Status == EFI_DEVICE_ERROR) {
1256 DEBUG ((DEBUG_ERROR, "DMA command failed at retry: %d\n", Task->RetryTimes));
1257 Status = AhciRecoverPortError (PciIo, Port);
1258 //
1259 // If recovery passed mark the Task as not started and change the status
1260 // to EFI_NOT_READY. This will make the higher level call this function again
1261 // and on next call the command will be re-issued due to IsStart being FALSE.
1262 // This also makes the next condition decrement the RetryTimes.
1263 //
1264 if (Status == EFI_SUCCESS) {
1265 Task->IsStart = FALSE;
1266 Status = EFI_NOT_READY;
1267 }
1268 }
1269
1270 if (Status == EFI_NOT_READY) {
1271 if (!Task->InfiniteWait && Task->RetryTimes == 0) {
1272 Status = EFI_TIMEOUT;
1273 } else {
1274 Task->RetryTimes--;
1275 }
1276 }
1277 }
1278 }
1279
1280 //
1281 // For Blocking mode, the command should be stopped, the Fis should be disabled
1282 // and the PciIo should be unmapped.
1283 // For non-blocking mode, only when a error is happened (if the return status is
1284 // EFI_NOT_READY that means the command doesn't finished, try again.), first do the
1285 // context cleanup, then set the packet's Asb status.
1286 //
1287 if (Task == NULL ||
1288 ((Task != NULL) && (Status != EFI_NOT_READY))
1289 ) {
1290 AhciStopCommand (
1291 PciIo,
1292 Port,
1293 Timeout
1294 );
1295
1296 AhciDisableFisReceive (
1297 PciIo,
1298 Port,
1299 Timeout
1300 );
1301
1302 PciIo->Unmap (
1303 PciIo,
1304 (Task != NULL) ? Task->Map : Map
1305 );
1306
1307 if (Task != NULL) {
1308 Task->Packet->Asb->AtaStatus = 0x01;
1309 }
1310 }
1311
1312 AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);
1313
1314 if (Status == EFI_DEVICE_ERROR) {
1315 DEBUG ((DEBUG_ERROR, "Failed to execute command for DMA transfer:\n"));
1316 //
1317 // Repeat command block here to make sure it is printed on
1318 // device error debug level.
1319 //
1320 AhciPrintCommandBlock (AtaCommandBlock, DEBUG_ERROR);
1321 AhciPrintStatusBlock (AtaStatusBlock, DEBUG_ERROR);
1322 } else {
1323 AhciPrintStatusBlock (AtaStatusBlock, DEBUG_VERBOSE);
1324 }
1325
1326 return Status;
1327 }
1328
1329 /**
1330 Start a non data transfer on specific port.
1331
1332 @param[in] PciIo The PCI IO protocol instance.
1333 @param[in] AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1334 @param[in] Port The number of port.
1335 @param[in] PortMultiplier The timeout value of stop.
1336 @param[in] AtapiCommand The atapi command will be used for the
1337 transfer.
1338 @param[in] AtapiCommandLength The length of the atapi command.
1339 @param[in] AtaCommandBlock The EFI_ATA_COMMAND_BLOCK data.
1340 @param[in, out] AtaStatusBlock The EFI_ATA_STATUS_BLOCK data.
1341 @param[in] Timeout The timeout value of non data transfer, uses 100ns as a unit.
1342 @param[in] Task Optional. Pointer to the ATA_NONBLOCK_TASK
1343 used by non-blocking mode.
1344
1345 @retval EFI_DEVICE_ERROR The non data transfer abort with error occurs.
1346 @retval EFI_TIMEOUT The operation is time out.
1347 @retval EFI_UNSUPPORTED The device is not ready for transfer.
1348 @retval EFI_SUCCESS The non data transfer executes successfully.
1349
1350 **/
1351 EFI_STATUS
1352 EFIAPI
1353 AhciNonDataTransfer (
1354 IN EFI_PCI_IO_PROTOCOL *PciIo,
1355 IN EFI_AHCI_REGISTERS *AhciRegisters,
1356 IN UINT8 Port,
1357 IN UINT8 PortMultiplier,
1358 IN EFI_AHCI_ATAPI_COMMAND *AtapiCommand OPTIONAL,
1359 IN UINT8 AtapiCommandLength,
1360 IN EFI_ATA_COMMAND_BLOCK *AtaCommandBlock,
1361 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock,
1362 IN UINT64 Timeout,
1363 IN ATA_NONBLOCK_TASK *Task
1364 )
1365 {
1366 EFI_STATUS Status;
1367 EFI_AHCI_COMMAND_FIS CFis;
1368 EFI_AHCI_COMMAND_LIST CmdList;
1369 UINT32 Retry;
1370
1371 //
1372 // Package read needed
1373 //
1374 AhciBuildCommandFis (&CFis, AtaCommandBlock);
1375
1376 ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
1377
1378 CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
1379
1380 for (Retry = 0; Retry < AHCI_COMMAND_RETRIES; Retry++) {
1381 AhciBuildCommand (
1382 PciIo,
1383 AhciRegisters,
1384 Port,
1385 PortMultiplier,
1386 &CFis,
1387 &CmdList,
1388 AtapiCommand,
1389 AtapiCommandLength,
1390 0,
1391 NULL,
1392 0
1393 );
1394
1395 DEBUG ((DEBUG_VERBOSE, "Starting command for non data transfer:\n"));
1396 AhciPrintCommandBlock (AtaCommandBlock, DEBUG_VERBOSE);
1397 Status = AhciStartCommand (
1398 PciIo,
1399 Port,
1400 0,
1401 Timeout
1402 );
1403 if (EFI_ERROR (Status)) {
1404 break;
1405 }
1406
1407 Status = AhciWaitUntilFisReceived (PciIo, Port, Timeout, SataFisD2H);
1408 if (Status == EFI_DEVICE_ERROR) {
1409 DEBUG ((DEBUG_ERROR, "Non data transfer failed at retry %d\n", Retry));
1410 Status = AhciRecoverPortError (PciIo, Port);
1411 if (EFI_ERROR (Status)) {
1412 break;
1413 }
1414 } else {
1415 break;
1416 }
1417 }
1418
1419 AhciStopCommand (
1420 PciIo,
1421 Port,
1422 Timeout
1423 );
1424
1425 AhciDisableFisReceive (
1426 PciIo,
1427 Port,
1428 Timeout
1429 );
1430
1431 AhciDumpPortStatus (PciIo, AhciRegisters, Port, AtaStatusBlock);
1432
1433 if (Status == EFI_DEVICE_ERROR) {
1434 DEBUG ((DEBUG_ERROR, "Failed to execute command for non data transfer:\n"));
1435 //
1436 // Repeat command block here to make sure it is printed on
1437 // device error debug level.
1438 //
1439 AhciPrintCommandBlock (AtaCommandBlock, DEBUG_ERROR);
1440 AhciPrintStatusBlock (AtaStatusBlock, DEBUG_ERROR);
1441 } else {
1442 AhciPrintStatusBlock (AtaStatusBlock, DEBUG_VERBOSE);
1443 }
1444
1445 return Status;
1446 }
1447
1448 /**
1449 Stop command running for giving port
1450
1451 @param PciIo The PCI IO protocol instance.
1452 @param Port The number of port.
1453 @param Timeout The timeout value of stop, uses 100ns as a unit.
1454
1455 @retval EFI_DEVICE_ERROR The command stop unsuccessfully.
1456 @retval EFI_TIMEOUT The operation is time out.
1457 @retval EFI_SUCCESS The command stop successfully.
1458
1459 **/
1460 EFI_STATUS
1461 EFIAPI
1462 AhciStopCommand (
1463 IN EFI_PCI_IO_PROTOCOL *PciIo,
1464 IN UINT8 Port,
1465 IN UINT64 Timeout
1466 )
1467 {
1468 UINT32 Offset;
1469 UINT32 Data;
1470
1471 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1472 Data = AhciReadReg (PciIo, Offset);
1473
1474 if ((Data & (EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_CR)) == 0) {
1475 return EFI_SUCCESS;
1476 }
1477
1478 if ((Data & EFI_AHCI_PORT_CMD_ST) != 0) {
1479 AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_ST));
1480 }
1481
1482 return AhciWaitMmioSet (
1483 PciIo,
1484 Offset,
1485 EFI_AHCI_PORT_CMD_CR,
1486 0,
1487 Timeout
1488 );
1489 }
1490
1491 /**
1492 Start command for give slot on specific port.
1493
1494 @param PciIo The PCI IO protocol instance.
1495 @param Port The number of port.
1496 @param CommandSlot The number of Command Slot.
1497 @param Timeout The timeout value of start, uses 100ns as a unit.
1498
1499 @retval EFI_DEVICE_ERROR The command start unsuccessfully.
1500 @retval EFI_TIMEOUT The operation is time out.
1501 @retval EFI_SUCCESS The command start successfully.
1502
1503 **/
1504 EFI_STATUS
1505 EFIAPI
1506 AhciStartCommand (
1507 IN EFI_PCI_IO_PROTOCOL *PciIo,
1508 IN UINT8 Port,
1509 IN UINT8 CommandSlot,
1510 IN UINT64 Timeout
1511 )
1512 {
1513 UINT32 CmdSlotBit;
1514 EFI_STATUS Status;
1515 UINT32 PortStatus;
1516 UINT32 StartCmd;
1517 UINT32 PortTfd;
1518 UINT32 Offset;
1519 UINT32 Capability;
1520
1521 //
1522 // Collect AHCI controller information
1523 //
1524 Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
1525
1526 CmdSlotBit = (UINT32) (1 << CommandSlot);
1527
1528 AhciClearPortStatus (
1529 PciIo,
1530 Port
1531 );
1532
1533 Status = AhciEnableFisReceive (
1534 PciIo,
1535 Port,
1536 Timeout
1537 );
1538
1539 if (EFI_ERROR (Status)) {
1540 return Status;
1541 }
1542
1543 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1544 PortStatus = AhciReadReg (PciIo, Offset);
1545
1546 StartCmd = 0;
1547 if ((PortStatus & EFI_AHCI_PORT_CMD_ALPE) != 0) {
1548 StartCmd = AhciReadReg (PciIo, Offset);
1549 StartCmd &= ~EFI_AHCI_PORT_CMD_ICC_MASK;
1550 StartCmd |= EFI_AHCI_PORT_CMD_ACTIVE;
1551 }
1552
1553 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
1554 PortTfd = AhciReadReg (PciIo, Offset);
1555
1556 if ((PortTfd & (EFI_AHCI_PORT_TFD_BSY | EFI_AHCI_PORT_TFD_DRQ)) != 0) {
1557 if ((Capability & BIT24) != 0) {
1558 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1559 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_CLO);
1560
1561 AhciWaitMmioSet (
1562 PciIo,
1563 Offset,
1564 EFI_AHCI_PORT_CMD_CLO,
1565 0,
1566 Timeout
1567 );
1568 }
1569 }
1570
1571 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1572 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_ST | StartCmd);
1573
1574 //
1575 // Setting the command
1576 //
1577 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;
1578 AhciAndReg (PciIo, Offset, 0);
1579 AhciOrReg (PciIo, Offset, CmdSlotBit);
1580
1581 return EFI_SUCCESS;
1582 }
1583
1584
1585 /**
1586 Do AHCI HBA reset.
1587
1588 @param PciIo The PCI IO protocol instance.
1589 @param Timeout The timeout value of reset, uses 100ns as a unit.
1590
1591 @retval EFI_DEVICE_ERROR AHCI controller is failed to complete hardware reset.
1592 @retval EFI_TIMEOUT The reset operation is time out.
1593 @retval EFI_SUCCESS AHCI controller is reset successfully.
1594
1595 **/
1596 EFI_STATUS
1597 EFIAPI
1598 AhciReset (
1599 IN EFI_PCI_IO_PROTOCOL *PciIo,
1600 IN UINT64 Timeout
1601 )
1602 {
1603 UINT64 Delay;
1604 UINT32 Value;
1605
1606 //
1607 // Make sure that GHC.AE bit is set before accessing any AHCI registers.
1608 //
1609 Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
1610
1611 if ((Value & EFI_AHCI_GHC_ENABLE) == 0) {
1612 AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
1613 }
1614
1615 AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);
1616
1617 Delay = DivU64x32(Timeout, 1000) + 1;
1618
1619 do {
1620 Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
1621
1622 if ((Value & EFI_AHCI_GHC_RESET) == 0) {
1623 break;
1624 }
1625
1626 //
1627 // Stall for 100 microseconds.
1628 //
1629 MicroSecondDelay(100);
1630
1631 Delay--;
1632 } while (Delay > 0);
1633
1634 if (Delay == 0) {
1635 return EFI_TIMEOUT;
1636 }
1637
1638 return EFI_SUCCESS;
1639 }
1640
1641 /**
1642 Send SMART Return Status command to check if the execution of SMART cmd is successful or not.
1643
1644 @param PciIo The PCI IO protocol instance.
1645 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1646 @param Port The number of port.
1647 @param PortMultiplier The port multiplier port number.
1648 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1649
1650 @retval EFI_SUCCESS Successfully get the return status of S.M.A.R.T command execution.
1651 @retval Others Fail to get return status data.
1652
1653 **/
1654 EFI_STATUS
1655 EFIAPI
1656 AhciAtaSmartReturnStatusCheck (
1657 IN EFI_PCI_IO_PROTOCOL *PciIo,
1658 IN EFI_AHCI_REGISTERS *AhciRegisters,
1659 IN UINT8 Port,
1660 IN UINT8 PortMultiplier,
1661 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
1662 )
1663 {
1664 EFI_STATUS Status;
1665 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1666 UINT8 LBAMid;
1667 UINT8 LBAHigh;
1668 UINTN FisBaseAddr;
1669 UINT32 Value;
1670
1671 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1672
1673 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
1674 AtaCommandBlock.AtaFeatures = ATA_SMART_RETURN_STATUS;
1675 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
1676 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
1677
1678 //
1679 // Send S.M.A.R.T Read Return Status command to device
1680 //
1681 Status = AhciNonDataTransfer (
1682 PciIo,
1683 AhciRegisters,
1684 (UINT8)Port,
1685 (UINT8)PortMultiplier,
1686 NULL,
1687 0,
1688 &AtaCommandBlock,
1689 AtaStatusBlock,
1690 ATA_ATAPI_TIMEOUT,
1691 NULL
1692 );
1693
1694 if (EFI_ERROR (Status)) {
1695 REPORT_STATUS_CODE (
1696 EFI_ERROR_CODE | EFI_ERROR_MINOR,
1697 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLED)
1698 );
1699 return EFI_DEVICE_ERROR;
1700 }
1701
1702 REPORT_STATUS_CODE (
1703 EFI_PROGRESS_CODE,
1704 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_ENABLE)
1705 );
1706
1707 FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
1708
1709 Value = *(UINT32 *) (FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET);
1710
1711 if ((Value & EFI_AHCI_FIS_TYPE_MASK) == EFI_AHCI_FIS_REGISTER_D2H) {
1712 LBAMid = ((UINT8 *)(UINTN)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET))[5];
1713 LBAHigh = ((UINT8 *)(UINTN)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET))[6];
1714
1715 if ((LBAMid == 0x4f) && (LBAHigh == 0xc2)) {
1716 //
1717 // The threshold exceeded condition is not detected by the device
1718 //
1719 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is not detected\n"));
1720 REPORT_STATUS_CODE (
1721 EFI_PROGRESS_CODE,
1722 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD)
1723 );
1724 } else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {
1725 //
1726 // The threshold exceeded condition is detected by the device
1727 //
1728 DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is detected\n"));
1729 REPORT_STATUS_CODE (
1730 EFI_PROGRESS_CODE,
1731 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD)
1732 );
1733 }
1734 }
1735
1736 return EFI_SUCCESS;
1737 }
1738
1739 /**
1740 Enable SMART command of the disk if supported.
1741
1742 @param PciIo The PCI IO protocol instance.
1743 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1744 @param Port The number of port.
1745 @param PortMultiplier The port multiplier port number.
1746 @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
1747 @param AtaStatusBlock A pointer to EFI_ATA_STATUS_BLOCK data structure.
1748
1749 **/
1750 VOID
1751 EFIAPI
1752 AhciAtaSmartSupport (
1753 IN EFI_PCI_IO_PROTOCOL *PciIo,
1754 IN EFI_AHCI_REGISTERS *AhciRegisters,
1755 IN UINT8 Port,
1756 IN UINT8 PortMultiplier,
1757 IN EFI_IDENTIFY_DATA *IdentifyData,
1758 IN OUT EFI_ATA_STATUS_BLOCK *AtaStatusBlock
1759 )
1760 {
1761 EFI_STATUS Status;
1762 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1763
1764 //
1765 // Detect if the device supports S.M.A.R.T.
1766 //
1767 if ((IdentifyData->AtaData.command_set_supported_82 & 0x0001) != 0x0001) {
1768 //
1769 // S.M.A.R.T is not supported by the device
1770 //
1771 DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at port [%d] PortMultiplier [%d]!\n",
1772 Port, PortMultiplier));
1773 REPORT_STATUS_CODE (
1774 EFI_ERROR_CODE | EFI_ERROR_MINOR,
1775 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED)
1776 );
1777 } else {
1778 //
1779 // Check if the feature is enabled. If not, then enable S.M.A.R.T.
1780 //
1781 if ((IdentifyData->AtaData.command_set_feature_enb_85 & 0x0001) != 0x0001) {
1782
1783 REPORT_STATUS_CODE (
1784 EFI_PROGRESS_CODE,
1785 (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLE)
1786 );
1787
1788 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1789
1790 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
1791 AtaCommandBlock.AtaFeatures = ATA_SMART_ENABLE_OPERATION;
1792 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
1793 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
1794
1795 //
1796 // Send S.M.A.R.T Enable command to device
1797 //
1798 Status = AhciNonDataTransfer (
1799 PciIo,
1800 AhciRegisters,
1801 (UINT8)Port,
1802 (UINT8)PortMultiplier,
1803 NULL,
1804 0,
1805 &AtaCommandBlock,
1806 AtaStatusBlock,
1807 ATA_ATAPI_TIMEOUT,
1808 NULL
1809 );
1810
1811
1812 if (!EFI_ERROR (Status)) {
1813 //
1814 // Send S.M.A.R.T AutoSave command to device
1815 //
1816 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1817
1818 AtaCommandBlock.AtaCommand = ATA_CMD_SMART;
1819 AtaCommandBlock.AtaFeatures = 0xD2;
1820 AtaCommandBlock.AtaSectorCount = 0xF1;
1821 AtaCommandBlock.AtaCylinderLow = ATA_CONSTANT_4F;
1822 AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
1823
1824 Status = AhciNonDataTransfer (
1825 PciIo,
1826 AhciRegisters,
1827 (UINT8)Port,
1828 (UINT8)PortMultiplier,
1829 NULL,
1830 0,
1831 &AtaCommandBlock,
1832 AtaStatusBlock,
1833 ATA_ATAPI_TIMEOUT,
1834 NULL
1835 );
1836 }
1837 }
1838
1839 AhciAtaSmartReturnStatusCheck (
1840 PciIo,
1841 AhciRegisters,
1842 (UINT8)Port,
1843 (UINT8)PortMultiplier,
1844 AtaStatusBlock
1845 );
1846
1847 DEBUG ((EFI_D_INFO, "Enabled S.M.A.R.T feature at port [%d] PortMultiplier [%d]!\n",
1848 Port, PortMultiplier));
1849 }
1850
1851 return ;
1852 }
1853
1854 /**
1855 Send Buffer cmd to specific device.
1856
1857 @param PciIo The PCI IO protocol instance.
1858 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1859 @param Port The number of port.
1860 @param PortMultiplier The port multiplier port number.
1861 @param Buffer The data buffer to store IDENTIFY PACKET data.
1862
1863 @retval EFI_DEVICE_ERROR The cmd abort with error occurs.
1864 @retval EFI_TIMEOUT The operation is time out.
1865 @retval EFI_UNSUPPORTED The device is not ready for executing.
1866 @retval EFI_SUCCESS The cmd executes successfully.
1867
1868 **/
1869 EFI_STATUS
1870 EFIAPI
1871 AhciIdentify (
1872 IN EFI_PCI_IO_PROTOCOL *PciIo,
1873 IN EFI_AHCI_REGISTERS *AhciRegisters,
1874 IN UINT8 Port,
1875 IN UINT8 PortMultiplier,
1876 IN OUT EFI_IDENTIFY_DATA *Buffer
1877 )
1878 {
1879 EFI_STATUS Status;
1880 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1881 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
1882
1883 if (PciIo == NULL || AhciRegisters == NULL || Buffer == NULL) {
1884 return EFI_INVALID_PARAMETER;
1885 }
1886
1887 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1888 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1889
1890 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DRIVE;
1891 AtaCommandBlock.AtaSectorCount = 1;
1892
1893 Status = AhciPioTransfer (
1894 PciIo,
1895 AhciRegisters,
1896 Port,
1897 PortMultiplier,
1898 NULL,
1899 0,
1900 TRUE,
1901 &AtaCommandBlock,
1902 &AtaStatusBlock,
1903 Buffer,
1904 sizeof (EFI_IDENTIFY_DATA),
1905 ATA_ATAPI_TIMEOUT,
1906 NULL
1907 );
1908
1909 return Status;
1910 }
1911
1912 /**
1913 Send Buffer cmd to specific device.
1914
1915 @param PciIo The PCI IO protocol instance.
1916 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1917 @param Port The number of port.
1918 @param PortMultiplier The port multiplier port number.
1919 @param Buffer The data buffer to store IDENTIFY PACKET data.
1920
1921 @retval EFI_DEVICE_ERROR The cmd abort with error occurs.
1922 @retval EFI_TIMEOUT The operation is time out.
1923 @retval EFI_UNSUPPORTED The device is not ready for executing.
1924 @retval EFI_SUCCESS The cmd executes successfully.
1925
1926 **/
1927 EFI_STATUS
1928 EFIAPI
1929 AhciIdentifyPacket (
1930 IN EFI_PCI_IO_PROTOCOL *PciIo,
1931 IN EFI_AHCI_REGISTERS *AhciRegisters,
1932 IN UINT8 Port,
1933 IN UINT8 PortMultiplier,
1934 IN OUT EFI_IDENTIFY_DATA *Buffer
1935 )
1936 {
1937 EFI_STATUS Status;
1938 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
1939 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
1940
1941 if (PciIo == NULL || AhciRegisters == NULL) {
1942 return EFI_INVALID_PARAMETER;
1943 }
1944
1945 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1946 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1947
1948 AtaCommandBlock.AtaCommand = ATA_CMD_IDENTIFY_DEVICE;
1949 AtaCommandBlock.AtaSectorCount = 1;
1950
1951 Status = AhciPioTransfer (
1952 PciIo,
1953 AhciRegisters,
1954 Port,
1955 PortMultiplier,
1956 NULL,
1957 0,
1958 TRUE,
1959 &AtaCommandBlock,
1960 &AtaStatusBlock,
1961 Buffer,
1962 sizeof (EFI_IDENTIFY_DATA),
1963 ATA_ATAPI_TIMEOUT,
1964 NULL
1965 );
1966
1967 return Status;
1968 }
1969
1970 /**
1971 Send SET FEATURE cmd on specific device.
1972
1973 @param PciIo The PCI IO protocol instance.
1974 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
1975 @param Port The number of port.
1976 @param PortMultiplier The port multiplier port number.
1977 @param Feature The data to send Feature register.
1978 @param FeatureSpecificData The specific data for SET FEATURE cmd.
1979 @param Timeout The timeout value of SET FEATURE cmd, uses 100ns as a unit.
1980
1981 @retval EFI_DEVICE_ERROR The cmd abort with error occurs.
1982 @retval EFI_TIMEOUT The operation is time out.
1983 @retval EFI_UNSUPPORTED The device is not ready for executing.
1984 @retval EFI_SUCCESS The cmd executes successfully.
1985
1986 **/
1987 EFI_STATUS
1988 EFIAPI
1989 AhciDeviceSetFeature (
1990 IN EFI_PCI_IO_PROTOCOL *PciIo,
1991 IN EFI_AHCI_REGISTERS *AhciRegisters,
1992 IN UINT8 Port,
1993 IN UINT8 PortMultiplier,
1994 IN UINT16 Feature,
1995 IN UINT32 FeatureSpecificData,
1996 IN UINT64 Timeout
1997 )
1998 {
1999 EFI_STATUS Status;
2000 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2001 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
2002
2003 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2004 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
2005
2006 AtaCommandBlock.AtaCommand = ATA_CMD_SET_FEATURES;
2007 AtaCommandBlock.AtaFeatures = (UINT8) Feature;
2008 AtaCommandBlock.AtaFeaturesExp = (UINT8) (Feature >> 8);
2009 AtaCommandBlock.AtaSectorCount = (UINT8) FeatureSpecificData;
2010 AtaCommandBlock.AtaSectorNumber = (UINT8) (FeatureSpecificData >> 8);
2011 AtaCommandBlock.AtaCylinderLow = (UINT8) (FeatureSpecificData >> 16);
2012 AtaCommandBlock.AtaCylinderHigh = (UINT8) (FeatureSpecificData >> 24);
2013
2014 Status = AhciNonDataTransfer (
2015 PciIo,
2016 AhciRegisters,
2017 (UINT8)Port,
2018 (UINT8)PortMultiplier,
2019 NULL,
2020 0,
2021 &AtaCommandBlock,
2022 &AtaStatusBlock,
2023 Timeout,
2024 NULL
2025 );
2026
2027 return Status;
2028 }
2029
2030 /**
2031 This function is used to send out ATAPI commands conforms to the Packet Command
2032 with PIO Protocol.
2033
2034 @param PciIo The PCI IO protocol instance.
2035 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2036 @param Port The number of port.
2037 @param PortMultiplier The number of port multiplier.
2038 @param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
2039
2040 @retval EFI_SUCCESS send out the ATAPI packet command successfully
2041 and device sends data successfully.
2042 @retval EFI_DEVICE_ERROR the device failed to send data.
2043
2044 **/
2045 EFI_STATUS
2046 EFIAPI
2047 AhciPacketCommandExecute (
2048 IN EFI_PCI_IO_PROTOCOL *PciIo,
2049 IN EFI_AHCI_REGISTERS *AhciRegisters,
2050 IN UINT8 Port,
2051 IN UINT8 PortMultiplier,
2052 IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet
2053 )
2054 {
2055 EFI_STATUS Status;
2056 VOID *Buffer;
2057 UINT32 Length;
2058 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2059 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
2060 BOOLEAN Read;
2061
2062 if (Packet == NULL || Packet->Cdb == NULL) {
2063 return EFI_INVALID_PARAMETER;
2064 }
2065
2066 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2067 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
2068 AtaCommandBlock.AtaCommand = ATA_CMD_PACKET;
2069 //
2070 // No OVL; No DMA
2071 //
2072 AtaCommandBlock.AtaFeatures = 0x00;
2073 //
2074 // set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device
2075 // determine how many data should be transferred.
2076 //
2077 AtaCommandBlock.AtaCylinderLow = (UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff);
2078 AtaCommandBlock.AtaCylinderHigh = (UINT8) (ATAPI_MAX_BYTE_COUNT >> 8);
2079
2080 if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) {
2081 Buffer = Packet->InDataBuffer;
2082 Length = Packet->InTransferLength;
2083 Read = TRUE;
2084 } else {
2085 Buffer = Packet->OutDataBuffer;
2086 Length = Packet->OutTransferLength;
2087 Read = FALSE;
2088 }
2089
2090 if (Length == 0) {
2091 Status = AhciNonDataTransfer (
2092 PciIo,
2093 AhciRegisters,
2094 Port,
2095 PortMultiplier,
2096 Packet->Cdb,
2097 Packet->CdbLength,
2098 &AtaCommandBlock,
2099 &AtaStatusBlock,
2100 Packet->Timeout,
2101 NULL
2102 );
2103 } else {
2104 Status = AhciPioTransfer (
2105 PciIo,
2106 AhciRegisters,
2107 Port,
2108 PortMultiplier,
2109 Packet->Cdb,
2110 Packet->CdbLength,
2111 Read,
2112 &AtaCommandBlock,
2113 &AtaStatusBlock,
2114 Buffer,
2115 Length,
2116 Packet->Timeout,
2117 NULL
2118 );
2119 }
2120 return Status;
2121 }
2122
2123 /**
2124 Allocate transfer-related data struct which is used at AHCI mode.
2125
2126 @param PciIo The PCI IO protocol instance.
2127 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2128
2129 **/
2130 EFI_STATUS
2131 EFIAPI
2132 AhciCreateTransferDescriptor (
2133 IN EFI_PCI_IO_PROTOCOL *PciIo,
2134 IN OUT EFI_AHCI_REGISTERS *AhciRegisters
2135 )
2136 {
2137 EFI_STATUS Status;
2138 UINTN Bytes;
2139 VOID *Buffer;
2140
2141 UINT32 Capability;
2142 UINT32 PortImplementBitMap;
2143 UINT8 MaxPortNumber;
2144 UINT8 MaxCommandSlotNumber;
2145 BOOLEAN Support64Bit;
2146 UINT64 MaxReceiveFisSize;
2147 UINT64 MaxCommandListSize;
2148 UINT64 MaxCommandTableSize;
2149 EFI_PHYSICAL_ADDRESS AhciRFisPciAddr;
2150 EFI_PHYSICAL_ADDRESS AhciCmdListPciAddr;
2151 EFI_PHYSICAL_ADDRESS AhciCommandTablePciAddr;
2152
2153 Buffer = NULL;
2154 //
2155 // Collect AHCI controller information
2156 //
2157 Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
2158 //
2159 // Get the number of command slots per port supported by this HBA.
2160 //
2161 MaxCommandSlotNumber = (UINT8) (((Capability & 0x1F00) >> 8) + 1);
2162 Support64Bit = (BOOLEAN) (((Capability & BIT31) != 0) ? TRUE : FALSE);
2163
2164 PortImplementBitMap = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);
2165 //
2166 // Get the highest bit of implemented ports which decides how many bytes are allocated for received FIS.
2167 //
2168 MaxPortNumber = (UINT8)(UINTN)(HighBitSet32(PortImplementBitMap) + 1);
2169 if (MaxPortNumber == 0) {
2170 return EFI_DEVICE_ERROR;
2171 }
2172
2173 MaxReceiveFisSize = MaxPortNumber * sizeof (EFI_AHCI_RECEIVED_FIS);
2174 Status = PciIo->AllocateBuffer (
2175 PciIo,
2176 AllocateAnyPages,
2177 EfiBootServicesData,
2178 EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),
2179 &Buffer,
2180 0
2181 );
2182
2183 if (EFI_ERROR (Status)) {
2184 return EFI_OUT_OF_RESOURCES;
2185 }
2186
2187 ZeroMem (Buffer, (UINTN)MaxReceiveFisSize);
2188
2189 AhciRegisters->AhciRFis = Buffer;
2190 AhciRegisters->MaxReceiveFisSize = MaxReceiveFisSize;
2191 Bytes = (UINTN)MaxReceiveFisSize;
2192
2193 Status = PciIo->Map (
2194 PciIo,
2195 EfiPciIoOperationBusMasterCommonBuffer,
2196 Buffer,
2197 &Bytes,
2198 &AhciRFisPciAddr,
2199 &AhciRegisters->MapRFis
2200 );
2201
2202 if (EFI_ERROR (Status) || (Bytes != MaxReceiveFisSize)) {
2203 //
2204 // Map error or unable to map the whole RFis buffer into a contiguous region.
2205 //
2206 Status = EFI_OUT_OF_RESOURCES;
2207 goto Error6;
2208 }
2209
2210 if ((!Support64Bit) && (AhciRFisPciAddr > 0x100000000ULL)) {
2211 //
2212 // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2213 //
2214 Status = EFI_DEVICE_ERROR;
2215 goto Error5;
2216 }
2217 AhciRegisters->AhciRFisPciAddr = (EFI_AHCI_RECEIVED_FIS *)(UINTN)AhciRFisPciAddr;
2218
2219 //
2220 // Allocate memory for command list
2221 // Note that the implementation is a single task model which only use a command list for all ports.
2222 //
2223 Buffer = NULL;
2224 MaxCommandListSize = MaxCommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST);
2225 Status = PciIo->AllocateBuffer (
2226 PciIo,
2227 AllocateAnyPages,
2228 EfiBootServicesData,
2229 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),
2230 &Buffer,
2231 0
2232 );
2233
2234 if (EFI_ERROR (Status)) {
2235 //
2236 // Free mapped resource.
2237 //
2238 Status = EFI_OUT_OF_RESOURCES;
2239 goto Error5;
2240 }
2241
2242 ZeroMem (Buffer, (UINTN)MaxCommandListSize);
2243
2244 AhciRegisters->AhciCmdList = Buffer;
2245 AhciRegisters->MaxCommandListSize = MaxCommandListSize;
2246 Bytes = (UINTN)MaxCommandListSize;
2247
2248 Status = PciIo->Map (
2249 PciIo,
2250 EfiPciIoOperationBusMasterCommonBuffer,
2251 Buffer,
2252 &Bytes,
2253 &AhciCmdListPciAddr,
2254 &AhciRegisters->MapCmdList
2255 );
2256
2257 if (EFI_ERROR (Status) || (Bytes != MaxCommandListSize)) {
2258 //
2259 // Map error or unable to map the whole cmd list buffer into a contiguous region.
2260 //
2261 Status = EFI_OUT_OF_RESOURCES;
2262 goto Error4;
2263 }
2264
2265 if ((!Support64Bit) && (AhciCmdListPciAddr > 0x100000000ULL)) {
2266 //
2267 // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2268 //
2269 Status = EFI_DEVICE_ERROR;
2270 goto Error3;
2271 }
2272 AhciRegisters->AhciCmdListPciAddr = (EFI_AHCI_COMMAND_LIST *)(UINTN)AhciCmdListPciAddr;
2273
2274 //
2275 // Allocate memory for command table
2276 // According to AHCI 1.3 spec, a PRD table can contain maximum 65535 entries.
2277 //
2278 Buffer = NULL;
2279 MaxCommandTableSize = sizeof (EFI_AHCI_COMMAND_TABLE);
2280
2281 Status = PciIo->AllocateBuffer (
2282 PciIo,
2283 AllocateAnyPages,
2284 EfiBootServicesData,
2285 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),
2286 &Buffer,
2287 0
2288 );
2289
2290 if (EFI_ERROR (Status)) {
2291 //
2292 // Free mapped resource.
2293 //
2294 Status = EFI_OUT_OF_RESOURCES;
2295 goto Error3;
2296 }
2297
2298 ZeroMem (Buffer, (UINTN)MaxCommandTableSize);
2299
2300 AhciRegisters->AhciCommandTable = Buffer;
2301 AhciRegisters->MaxCommandTableSize = MaxCommandTableSize;
2302 Bytes = (UINTN)MaxCommandTableSize;
2303
2304 Status = PciIo->Map (
2305 PciIo,
2306 EfiPciIoOperationBusMasterCommonBuffer,
2307 Buffer,
2308 &Bytes,
2309 &AhciCommandTablePciAddr,
2310 &AhciRegisters->MapCommandTable
2311 );
2312
2313 if (EFI_ERROR (Status) || (Bytes != MaxCommandTableSize)) {
2314 //
2315 // Map error or unable to map the whole cmd list buffer into a contiguous region.
2316 //
2317 Status = EFI_OUT_OF_RESOURCES;
2318 goto Error2;
2319 }
2320
2321 if ((!Support64Bit) && (AhciCommandTablePciAddr > 0x100000000ULL)) {
2322 //
2323 // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2324 //
2325 Status = EFI_DEVICE_ERROR;
2326 goto Error1;
2327 }
2328 AhciRegisters->AhciCommandTablePciAddr = (EFI_AHCI_COMMAND_TABLE *)(UINTN)AhciCommandTablePciAddr;
2329
2330 return EFI_SUCCESS;
2331 //
2332 // Map error or unable to map the whole CmdList buffer into a contiguous region.
2333 //
2334 Error1:
2335 PciIo->Unmap (
2336 PciIo,
2337 AhciRegisters->MapCommandTable
2338 );
2339 Error2:
2340 PciIo->FreeBuffer (
2341 PciIo,
2342 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),
2343 AhciRegisters->AhciCommandTable
2344 );
2345 Error3:
2346 PciIo->Unmap (
2347 PciIo,
2348 AhciRegisters->MapCmdList
2349 );
2350 Error4:
2351 PciIo->FreeBuffer (
2352 PciIo,
2353 EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),
2354 AhciRegisters->AhciCmdList
2355 );
2356 Error5:
2357 PciIo->Unmap (
2358 PciIo,
2359 AhciRegisters->MapRFis
2360 );
2361 Error6:
2362 PciIo->FreeBuffer (
2363 PciIo,
2364 EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),
2365 AhciRegisters->AhciRFis
2366 );
2367
2368 return Status;
2369 }
2370
2371 /**
2372 Read logs from SATA device.
2373
2374 @param PciIo The PCI IO protocol instance.
2375 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2376 @param Port The number of port.
2377 @param PortMultiplier The multiplier of port.
2378 @param Buffer The data buffer to store SATA logs.
2379 @param LogNumber The address of the log.
2380 @param PageNumber The page number of the log.
2381
2382 @retval EFI_INVALID_PARAMETER PciIo, AhciRegisters or Buffer is NULL.
2383 @retval others Return status of AhciPioTransfer().
2384 **/
2385 EFI_STATUS
2386 AhciReadLogExt (
2387 IN EFI_PCI_IO_PROTOCOL *PciIo,
2388 IN EFI_AHCI_REGISTERS *AhciRegisters,
2389 IN UINT8 Port,
2390 IN UINT8 PortMultiplier,
2391 IN OUT UINT8 *Buffer,
2392 IN UINT8 LogNumber,
2393 IN UINT8 PageNumber
2394 )
2395 {
2396 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2397 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
2398
2399 if (PciIo == NULL || AhciRegisters == NULL || Buffer == NULL) {
2400 return EFI_INVALID_PARAMETER;
2401 }
2402
2403 ///
2404 /// Read log from device
2405 ///
2406 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2407 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
2408 ZeroMem (Buffer, 512);
2409
2410 AtaCommandBlock.AtaCommand = ATA_CMD_READ_LOG_EXT;
2411 AtaCommandBlock.AtaSectorCount = 1;
2412 AtaCommandBlock.AtaSectorNumber = LogNumber;
2413 AtaCommandBlock.AtaCylinderLow = PageNumber;
2414
2415 return AhciPioTransfer (
2416 PciIo,
2417 AhciRegisters,
2418 Port,
2419 PortMultiplier,
2420 NULL,
2421 0,
2422 TRUE,
2423 &AtaCommandBlock,
2424 &AtaStatusBlock,
2425 Buffer,
2426 512,
2427 ATA_ATAPI_TIMEOUT,
2428 NULL
2429 );
2430 }
2431
2432 /**
2433 Enable DEVSLP of the disk if supported.
2434
2435 @param PciIo The PCI IO protocol instance.
2436 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2437 @param Port The number of port.
2438 @param PortMultiplier The multiplier of port.
2439 @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
2440
2441 @retval EFI_SUCCESS The DEVSLP is enabled per policy successfully.
2442 @retval EFI_UNSUPPORTED The DEVSLP isn't supported by the controller/device and policy requires to enable it.
2443 **/
2444 EFI_STATUS
2445 AhciEnableDevSlp (
2446 IN EFI_PCI_IO_PROTOCOL *PciIo,
2447 IN EFI_AHCI_REGISTERS *AhciRegisters,
2448 IN UINT8 Port,
2449 IN UINT8 PortMultiplier,
2450 IN EFI_IDENTIFY_DATA *IdentifyData
2451 )
2452 {
2453 EFI_STATUS Status;
2454 UINT32 Offset;
2455 UINT32 Capability2;
2456 UINT8 LogData[512];
2457 DEVSLP_TIMING_VARIABLES DevSlpTiming;
2458 UINT32 PortCmd;
2459 UINT32 PortDevSlp;
2460
2461 if (mAtaAtapiPolicy->DeviceSleepEnable != 1) {
2462 return EFI_SUCCESS;
2463 }
2464
2465 //
2466 // Do not enable DevSlp if DevSlp is not supported.
2467 //
2468 Capability2 = AhciReadReg (PciIo, AHCI_CAPABILITY2_OFFSET);
2469 DEBUG ((DEBUG_INFO, "AHCI CAPABILITY2 = %08x\n", Capability2));
2470 if ((Capability2 & AHCI_CAP2_SDS) == 0) {
2471 return EFI_UNSUPPORTED;
2472 }
2473
2474 //
2475 // Do not enable DevSlp if DevSlp is not present
2476 // Do not enable DevSlp if Hot Plug or Mechanical Presence Switch is supported
2477 //
2478 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH;
2479 PortCmd = AhciReadReg (PciIo, Offset + EFI_AHCI_PORT_CMD);
2480 PortDevSlp = AhciReadReg (PciIo, Offset + AHCI_PORT_DEVSLP);
2481 DEBUG ((DEBUG_INFO, "Port CMD/DEVSLP = %08x / %08x\n", PortCmd, PortDevSlp));
2482 if (((PortDevSlp & AHCI_PORT_DEVSLP_DSP) == 0) ||
2483 ((PortCmd & (EFI_AHCI_PORT_CMD_HPCP | EFI_AHCI_PORT_CMD_MPSP)) != 0)
2484 ) {
2485 return EFI_UNSUPPORTED;
2486 }
2487
2488 //
2489 // Do not enable DevSlp if the device doesn't support DevSlp
2490 //
2491 DEBUG ((DEBUG_INFO, "IDENTIFY DEVICE: [77] = %04x, [78] = %04x, [79] = %04x\n",
2492 IdentifyData->AtaData.reserved_77,
2493 IdentifyData->AtaData.serial_ata_features_supported, IdentifyData->AtaData.serial_ata_features_enabled));
2494 if ((IdentifyData->AtaData.serial_ata_features_supported & BIT8) == 0) {
2495 DEBUG ((DEBUG_INFO, "DevSlp feature is not supported for device at port [%d] PortMultiplier [%d]!\n",
2496 Port, PortMultiplier));
2497 return EFI_UNSUPPORTED;
2498 }
2499
2500 //
2501 // Enable DevSlp when it is not enabled.
2502 //
2503 if ((IdentifyData->AtaData.serial_ata_features_enabled & BIT8) != 0) {
2504 Status = AhciDeviceSetFeature (
2505 PciIo, AhciRegisters, Port, 0, ATA_SUB_CMD_ENABLE_SATA_FEATURE, 0x09, ATA_ATAPI_TIMEOUT
2506 );
2507 DEBUG ((DEBUG_INFO, "DevSlp set feature for device at port [%d] PortMultiplier [%d] - %r\n",
2508 Port, PortMultiplier, Status));
2509 if (EFI_ERROR (Status)) {
2510 return Status;
2511 }
2512 }
2513
2514 Status = AhciReadLogExt(PciIo, AhciRegisters, Port, PortMultiplier, LogData, 0x30, 0x08);
2515
2516 //
2517 // Clear PxCMD.ST and PxDEVSLP.ADSE before updating PxDEVSLP.DITO and PxDEVSLP.MDAT.
2518 //
2519 AhciWriteReg (PciIo, Offset + EFI_AHCI_PORT_CMD, PortCmd & ~EFI_AHCI_PORT_CMD_ST);
2520 PortDevSlp &= ~AHCI_PORT_DEVSLP_ADSE;
2521 AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
2522
2523 //
2524 // Set PxDEVSLP.DETO and PxDEVSLP.MDAT to 0.
2525 //
2526 PortDevSlp &= ~AHCI_PORT_DEVSLP_DETO_MASK;
2527 PortDevSlp &= ~AHCI_PORT_DEVSLP_MDAT_MASK;
2528 AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
2529 DEBUG ((DEBUG_INFO, "Read Log Ext at port [%d] PortMultiplier [%d] - %r\n", Port, PortMultiplier, Status));
2530 if (EFI_ERROR (Status)) {
2531 //
2532 // Assume DEVSLP TIMING VARIABLES is not supported if the Identify Device Data log (30h, 8) fails
2533 //
2534 ZeroMem (&DevSlpTiming, sizeof (DevSlpTiming));
2535 } else {
2536 CopyMem (&DevSlpTiming, &LogData[48], sizeof (DevSlpTiming));
2537 DEBUG ((DEBUG_INFO, "DevSlpTiming: Supported(%d), Deto(%d), Madt(%d)\n",
2538 DevSlpTiming.Supported, DevSlpTiming.Deto, DevSlpTiming.Madt));
2539 }
2540
2541 //
2542 // Use 20ms as default DETO when DEVSLP TIMING VARIABLES is not supported or the DETO is 0.
2543 //
2544 if ((DevSlpTiming.Supported == 0) || (DevSlpTiming.Deto == 0)) {
2545 DevSlpTiming.Deto = 20;
2546 }
2547
2548 //
2549 // Use 10ms as default MADT when DEVSLP TIMING VARIABLES is not supported or the MADT is 0.
2550 //
2551 if ((DevSlpTiming.Supported == 0) || (DevSlpTiming.Madt == 0)) {
2552 DevSlpTiming.Madt = 10;
2553 }
2554
2555 PortDevSlp |= DevSlpTiming.Deto << 2;
2556 PortDevSlp |= DevSlpTiming.Madt << 10;
2557 AhciOrReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
2558
2559 if (mAtaAtapiPolicy->AggressiveDeviceSleepEnable == 1) {
2560 if ((Capability2 & AHCI_CAP2_SADM) != 0) {
2561 PortDevSlp &= ~AHCI_PORT_DEVSLP_DITO_MASK;
2562 PortDevSlp |= (625 << 15);
2563 AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
2564
2565 PortDevSlp |= AHCI_PORT_DEVSLP_ADSE;
2566 AhciWriteReg (PciIo, Offset + AHCI_PORT_DEVSLP, PortDevSlp);
2567 }
2568 }
2569
2570
2571 AhciWriteReg (PciIo, Offset + EFI_AHCI_PORT_CMD, PortCmd);
2572
2573 DEBUG ((DEBUG_INFO, "Enabled DevSlp feature at port [%d] PortMultiplier [%d], Port CMD/DEVSLP = %08x / %08x\n",
2574 Port, PortMultiplier, PortCmd, PortDevSlp));
2575
2576 return EFI_SUCCESS;
2577 }
2578
2579 /**
2580 Spin-up disk if IDD was incomplete or PUIS feature is enabled
2581
2582 @param PciIo The PCI IO protocol instance.
2583 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2584 @param Port The number of port.
2585 @param PortMultiplier The multiplier of port.
2586 @param IdentifyData A pointer to data buffer which is used to contain IDENTIFY data.
2587
2588 **/
2589 EFI_STATUS
2590 AhciSpinUpDisk (
2591 IN EFI_PCI_IO_PROTOCOL *PciIo,
2592 IN EFI_AHCI_REGISTERS *AhciRegisters,
2593 IN UINT8 Port,
2594 IN UINT8 PortMultiplier,
2595 IN OUT EFI_IDENTIFY_DATA *IdentifyData
2596 )
2597 {
2598 EFI_STATUS Status;
2599 EFI_ATA_COMMAND_BLOCK AtaCommandBlock;
2600 EFI_ATA_STATUS_BLOCK AtaStatusBlock;
2601 UINT8 Buffer[512];
2602
2603 if (IdentifyData->AtaData.specific_config == ATA_SPINUP_CFG_REQUIRED_IDD_INCOMPLETE) {
2604 //
2605 // Use SET_FEATURE subcommand to spin up the device.
2606 //
2607 Status = AhciDeviceSetFeature (
2608 PciIo, AhciRegisters, Port, PortMultiplier,
2609 ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP, 0x00, ATA_SPINUP_TIMEOUT
2610 );
2611 DEBUG ((DEBUG_INFO, "CMD_PUIS_SET_DEVICE_SPINUP for device at port [%d] PortMultiplier [%d] - %r!\n",
2612 Port, PortMultiplier, Status));
2613 if (EFI_ERROR (Status)) {
2614 return Status;
2615 }
2616 } else {
2617 ASSERT (IdentifyData->AtaData.specific_config == ATA_SPINUP_CFG_NOT_REQUIRED_IDD_INCOMPLETE);
2618
2619 //
2620 // Use READ_SECTORS to spin up the device if SpinUp SET FEATURE subcommand is not supported
2621 //
2622 ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
2623 ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
2624 //
2625 // Perform READ SECTORS PIO Data-In command to Read LBA 0
2626 //
2627 AtaCommandBlock.AtaCommand = ATA_CMD_READ_SECTORS;
2628 AtaCommandBlock.AtaSectorCount = 0x1;
2629
2630 Status = AhciPioTransfer (
2631 PciIo,
2632 AhciRegisters,
2633 Port,
2634 PortMultiplier,
2635 NULL,
2636 0,
2637 TRUE,
2638 &AtaCommandBlock,
2639 &AtaStatusBlock,
2640 &Buffer,
2641 sizeof (Buffer),
2642 ATA_SPINUP_TIMEOUT,
2643 NULL
2644 );
2645 DEBUG ((DEBUG_INFO, "Read LBA 0 for device at port [%d] PortMultiplier [%d] - %r!\n",
2646 Port, PortMultiplier, Status));
2647 if (EFI_ERROR (Status)) {
2648 return Status;
2649 }
2650 }
2651
2652 //
2653 // Read the complete IDENTIFY DEVICE data.
2654 //
2655 ZeroMem (IdentifyData, sizeof (*IdentifyData));
2656 Status = AhciIdentify (PciIo, AhciRegisters, Port, PortMultiplier, IdentifyData);
2657 if (EFI_ERROR (Status)) {
2658 DEBUG ((DEBUG_ERROR, "Read IDD failed for device at port [%d] PortMultiplier [%d] - %r!\n",
2659 Port, PortMultiplier, Status));
2660 return Status;
2661 }
2662
2663 DEBUG ((DEBUG_INFO, "IDENTIFY DEVICE: [0] = %016x, [2] = %016x, [83] = %016x, [86] = %016x\n",
2664 IdentifyData->AtaData.config, IdentifyData->AtaData.specific_config,
2665 IdentifyData->AtaData.command_set_supported_83, IdentifyData->AtaData.command_set_feature_enb_86));
2666 //
2667 // Check if IDD is incomplete
2668 //
2669 if ((IdentifyData->AtaData.config & BIT2) != 0) {
2670 return EFI_DEVICE_ERROR;
2671 }
2672
2673 return EFI_SUCCESS;
2674 }
2675
2676 /**
2677 Enable/disable/skip PUIS of the disk according to policy.
2678
2679 @param PciIo The PCI IO protocol instance.
2680 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
2681 @param Port The number of port.
2682 @param PortMultiplier The multiplier of port.
2683
2684 **/
2685 EFI_STATUS
2686 AhciPuisEnable (
2687 IN EFI_PCI_IO_PROTOCOL *PciIo,
2688 IN EFI_AHCI_REGISTERS *AhciRegisters,
2689 IN UINT8 Port,
2690 IN UINT8 PortMultiplier
2691 )
2692 {
2693 EFI_STATUS Status;
2694
2695 Status = EFI_SUCCESS;
2696 if (mAtaAtapiPolicy->PuisEnable == 0) {
2697 Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, PortMultiplier, ATA_SUB_CMD_DISABLE_PUIS, 0x00, ATA_ATAPI_TIMEOUT);
2698 } else if (mAtaAtapiPolicy->PuisEnable == 1) {
2699 Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, PortMultiplier, ATA_SUB_CMD_ENABLE_PUIS, 0x00, ATA_ATAPI_TIMEOUT);
2700 }
2701 DEBUG ((DEBUG_INFO, "%a PUIS feature at port [%d] PortMultiplier [%d] - %r!\n",
2702 (mAtaAtapiPolicy->PuisEnable == 0) ? "Disable" : (
2703 (mAtaAtapiPolicy->PuisEnable == 1) ? "Enable" : "Skip"
2704 ), Port, PortMultiplier, Status));
2705 return Status;
2706 }
2707
2708 /**
2709 Initialize ATA host controller at AHCI mode.
2710
2711 The function is designed to initialize ATA host controller.
2712
2713 @param[in] Instance A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
2714
2715 **/
2716 EFI_STATUS
2717 EFIAPI
2718 AhciModeInitialization (
2719 IN ATA_ATAPI_PASS_THRU_INSTANCE *Instance
2720 )
2721 {
2722 EFI_STATUS Status;
2723 EFI_PCI_IO_PROTOCOL *PciIo;
2724 EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
2725 UINT32 Capability;
2726 UINT8 MaxPortNumber;
2727 UINT32 PortImplementBitMap;
2728
2729 EFI_AHCI_REGISTERS *AhciRegisters;
2730
2731 UINT8 Port;
2732 DATA_64 Data64;
2733 UINT32 Offset;
2734 UINT32 Data;
2735 EFI_IDENTIFY_DATA Buffer;
2736 EFI_ATA_DEVICE_TYPE DeviceType;
2737 EFI_ATA_COLLECTIVE_MODE *SupportedModes;
2738 EFI_ATA_TRANSFER_MODE TransferMode;
2739 UINT32 PhyDetectDelay;
2740 UINT32 Value;
2741
2742 if (Instance == NULL) {
2743 return EFI_INVALID_PARAMETER;
2744 }
2745
2746 PciIo = Instance->PciIo;
2747 IdeInit = Instance->IdeControllerInit;
2748
2749 Status = AhciReset (PciIo, EFI_AHCI_BUS_RESET_TIMEOUT);
2750
2751 if (EFI_ERROR (Status)) {
2752 return EFI_DEVICE_ERROR;
2753 }
2754
2755 //
2756 // Collect AHCI controller information
2757 //
2758 Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET);
2759
2760 //
2761 // Make sure that GHC.AE bit is set before accessing any AHCI registers.
2762 //
2763 Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
2764
2765 if ((Value & EFI_AHCI_GHC_ENABLE) == 0) {
2766 AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
2767 }
2768
2769 //
2770 // Enable 64-bit DMA support in the PCI layer if this controller
2771 // supports it.
2772 //
2773 if ((Capability & EFI_AHCI_CAP_S64A) != 0) {
2774 Status = PciIo->Attributes (
2775 PciIo,
2776 EfiPciIoAttributeOperationEnable,
2777 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE,
2778 NULL
2779 );
2780 if (EFI_ERROR (Status)) {
2781 DEBUG ((EFI_D_WARN,
2782 "AhciModeInitialization: failed to enable 64-bit DMA on 64-bit capable controller (%r)\n",
2783 Status));
2784 }
2785 }
2786
2787 //
2788 // Get the number of command slots per port supported by this HBA.
2789 //
2790 MaxPortNumber = (UINT8) ((Capability & 0x1F) + 1);
2791
2792 //
2793 // Get the bit map of those ports exposed by this HBA.
2794 // It indicates which ports that the HBA supports are available for software to use.
2795 //
2796 PortImplementBitMap = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);
2797
2798 AhciRegisters = &Instance->AhciRegisters;
2799 Status = AhciCreateTransferDescriptor (PciIo, AhciRegisters);
2800
2801 if (EFI_ERROR (Status)) {
2802 return EFI_OUT_OF_RESOURCES;
2803 }
2804
2805 for (Port = 0; Port < EFI_AHCI_MAX_PORTS; Port ++) {
2806 if ((PortImplementBitMap & (((UINT32)BIT0) << Port)) != 0) {
2807 //
2808 // According to AHCI spec, MaxPortNumber should be equal or greater than the number of implemented ports.
2809 //
2810 if ((MaxPortNumber--) == 0) {
2811 //
2812 // Should never be here.
2813 //
2814 ASSERT (FALSE);
2815 return EFI_SUCCESS;
2816 }
2817
2818 IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelEnumeration, Port);
2819
2820 //
2821 // Initialize FIS Base Address Register and Command List Base Address Register for use.
2822 //
2823 Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFisPciAddr) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
2824 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FB;
2825 AhciWriteReg (PciIo, Offset, Data64.Uint32.Lower32);
2826 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FBU;
2827 AhciWriteReg (PciIo, Offset, Data64.Uint32.Upper32);
2828
2829 Data64.Uint64 = (UINTN) (AhciRegisters->AhciCmdListPciAddr);
2830 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLB;
2831 AhciWriteReg (PciIo, Offset, Data64.Uint32.Lower32);
2832 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLBU;
2833 AhciWriteReg (PciIo, Offset, Data64.Uint32.Upper32);
2834
2835 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
2836 Data = AhciReadReg (PciIo, Offset);
2837 if ((Data & EFI_AHCI_PORT_CMD_CPD) != 0) {
2838 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_POD);
2839 }
2840
2841 if ((Capability & EFI_AHCI_CAP_SSS) != 0) {
2842 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_SUD);
2843 }
2844
2845 //
2846 // Disable aggressive power management.
2847 //
2848 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;
2849 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_SCTL_IPM_INIT);
2850 //
2851 // Disable the reporting of the corresponding interrupt to system software.
2852 //
2853 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IE;
2854 AhciAndReg (PciIo, Offset, 0);
2855
2856 //
2857 // Now inform the IDE Controller Init Module.
2858 //
2859 IdeInit->NotifyPhase (IdeInit, EfiIdeBusBeforeDevicePresenceDetection, Port);
2860
2861 //
2862 // Enable FIS Receive DMA engine for the first D2H FIS.
2863 //
2864 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
2865 AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);
2866
2867 //
2868 // Wait for the Phy to detect the presence of a device.
2869 //
2870 PhyDetectDelay = EFI_AHCI_BUS_PHY_DETECT_TIMEOUT;
2871 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
2872 do {
2873 Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_SSTS_DET_MASK;
2874 if ((Data == EFI_AHCI_PORT_SSTS_DET_PCE) || (Data == EFI_AHCI_PORT_SSTS_DET)) {
2875 break;
2876 }
2877
2878 MicroSecondDelay (1000);
2879 PhyDetectDelay--;
2880 } while (PhyDetectDelay > 0);
2881
2882 if (PhyDetectDelay == 0) {
2883 //
2884 // No device detected at this port.
2885 // Clear PxCMD.SUD for those ports at which there are no device present.
2886 //
2887 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
2888 AhciAndReg (PciIo, Offset, (UINT32) ~(EFI_AHCI_PORT_CMD_SUD));
2889 continue;
2890 }
2891
2892 Status = AhciWaitDeviceReady (PciIo, Port);
2893 if (EFI_ERROR (Status)) {
2894 continue;
2895 }
2896
2897 //
2898 // When the first D2H register FIS is received, the content of PxSIG register is updated.
2899 //
2900 Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SIG;
2901 Status = AhciWaitMmioSet (
2902 PciIo,
2903 Offset,
2904 0x0000FFFF,
2905 0x00000101,
2906 EFI_TIMER_PERIOD_SECONDS(16)
2907 );
2908 if (EFI_ERROR (Status)) {
2909 continue;
2910 }
2911
2912 Data = AhciReadReg (PciIo, Offset);
2913 if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATAPI_DEVICE_SIG) {
2914 Status = AhciIdentifyPacket (PciIo, AhciRegisters, Port, 0, &Buffer);
2915
2916 if (EFI_ERROR (Status)) {
2917 continue;
2918 }
2919
2920 DeviceType = EfiIdeCdrom;
2921 } else if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATA_DEVICE_SIG) {
2922 Status = AhciIdentify (PciIo, AhciRegisters, Port, 0, &Buffer);
2923
2924 if (EFI_ERROR (Status)) {
2925 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED));
2926 continue;
2927 }
2928
2929 DEBUG ((
2930 DEBUG_INFO, "IDENTIFY DEVICE: [0] = %016x, [2] = %016x, [83] = %016x, [86] = %016x\n",
2931 Buffer.AtaData.config, Buffer.AtaData.specific_config,
2932 Buffer.AtaData.command_set_supported_83, Buffer.AtaData.command_set_feature_enb_86
2933 ));
2934 if ((Buffer.AtaData.config & BIT2) != 0) {
2935 //
2936 // SpinUp disk if device reported incomplete IDENTIFY DEVICE.
2937 //
2938 Status = AhciSpinUpDisk (
2939 PciIo,
2940 AhciRegisters,
2941 Port,
2942 0,
2943 &Buffer
2944 );
2945 if (EFI_ERROR (Status)) {
2946 DEBUG ((DEBUG_ERROR, "Spin up standby device failed - %r\n", Status));
2947 continue;
2948 }
2949 }
2950
2951 DeviceType = EfiIdeHarddisk;
2952 } else {
2953 continue;
2954 }
2955 DEBUG ((DEBUG_INFO, "port [%d] port multitplier [%d] has a [%a]\n",
2956 Port, 0, DeviceType == EfiIdeCdrom ? "cdrom" : "harddisk"));
2957
2958 //
2959 // If the device is a hard disk, then try to enable S.M.A.R.T feature
2960 //
2961 if ((DeviceType == EfiIdeHarddisk) && PcdGetBool (PcdAtaSmartEnable)) {
2962 AhciAtaSmartSupport (
2963 PciIo,
2964 AhciRegisters,
2965 Port,
2966 0,
2967 &Buffer,
2968 NULL
2969 );
2970 }
2971
2972 //
2973 // Submit identify data to IDE controller init driver
2974 //
2975 IdeInit->SubmitData (IdeInit, Port, 0, &Buffer);
2976
2977 //
2978 // Now start to config ide device parameter and transfer mode.
2979 //
2980 Status = IdeInit->CalculateMode (
2981 IdeInit,
2982 Port,
2983 0,
2984 &SupportedModes
2985 );
2986 if (EFI_ERROR (Status)) {
2987 DEBUG ((EFI_D_ERROR, "Calculate Mode Fail, Status = %r\n", Status));
2988 continue;
2989 }
2990
2991 //
2992 // Set best supported PIO mode on this IDE device
2993 //
2994 if (SupportedModes->PioMode.Mode <= EfiAtaPioMode2) {
2995 TransferMode.ModeCategory = EFI_ATA_MODE_DEFAULT_PIO;
2996 } else {
2997 TransferMode.ModeCategory = EFI_ATA_MODE_FLOW_PIO;
2998 }
2999
3000 TransferMode.ModeNumber = (UINT8) (SupportedModes->PioMode.Mode);
3001
3002 //
3003 // Set supported DMA mode on this IDE device. Note that UDMA & MDMA can't
3004 // be set together. Only one DMA mode can be set to a device. If setting
3005 // DMA mode operation fails, we can continue moving on because we only use
3006 // PIO mode at boot time. DMA modes are used by certain kind of OS booting
3007 //
3008 if (SupportedModes->UdmaMode.Valid) {
3009 TransferMode.ModeCategory = EFI_ATA_MODE_UDMA;
3010 TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);
3011 } else if (SupportedModes->MultiWordDmaMode.Valid) {
3012 TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;
3013 TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;
3014 }
3015
3016 Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, 0, 0x03, (UINT32)(*(UINT8 *)&TransferMode), ATA_ATAPI_TIMEOUT);
3017 if (EFI_ERROR (Status)) {
3018 DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
3019 continue;
3020 }
3021
3022 //
3023 // Found a ATA or ATAPI device, add it into the device list.
3024 //
3025 CreateNewDeviceInfo (Instance, Port, 0xFFFF, DeviceType, &Buffer);
3026 if (DeviceType == EfiIdeHarddisk) {
3027 REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));
3028 AhciEnableDevSlp (
3029 PciIo,
3030 AhciRegisters,
3031 Port,
3032 0,
3033 &Buffer
3034 );
3035 }
3036
3037 //
3038 // Enable/disable PUIS according to policy setting if PUIS is capable (Word[83].BIT5 is set).
3039 //
3040 if ((Buffer.AtaData.command_set_supported_83 & BIT5) != 0) {
3041 Status = AhciPuisEnable (
3042 PciIo,
3043 AhciRegisters,
3044 Port,
3045 0
3046 );
3047 if (EFI_ERROR (Status)) {
3048 DEBUG ((DEBUG_ERROR, "PUIS enable/disable failed, Status = %r\n", Status));
3049 continue;
3050 }
3051 }
3052 }
3053 }
3054
3055 return EFI_SUCCESS;
3056 }
3057
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