MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c

   1 /** @file
   2   The file for AHCI mode of ATA host controller.
   3
   4   Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14
  15 #include "AtaAtapiPassThru.h"
  16
  17 /**
  18   Read AHCI Operation register.
  19
  20   @param  PciIo        The PCI IO protocol instance.
  21   @param  Offset       The operation register offset.
  22
  23   @return The register content read.
  24
  25 **/
  26 UINT32
  27 EFIAPI
  28 AhciReadReg (
  29   IN EFI_PCI_IO_PROTOCOL  *PciIo,
  30   IN  UINT32              Offset
  31   )
  32 {
  33   UINT32                  Data;
  34
  35   ASSERT (PciIo != NULL);
  36
  37   Data = 0;
  38
  39   PciIo->Mem.Read (
  40                PciIo,
  41                EfiPciIoWidthUint32,
  42                EFI_AHCI_BAR_INDEX,
  43                (UINT64) Offset,
  44                1,
  45                &Data
  46                );
  47
  48   return Data;
  49 }
  50
  51 /**
  52   Write AHCI Operation register.
  53
  54   @param  PciIo        The PCI IO protocol instance.
  55   @param  Offset       The operation register offset.
  56   @param  Data         The data used to write down.
  57
  58 **/
  59 VOID
  60 EFIAPI
  61 AhciWriteReg (
  62   IN EFI_PCI_IO_PROTOCOL  *PciIo,
  63   IN UINT32               Offset,
  64   IN UINT32               Data
  65   )
  66 {
  67   ASSERT (PciIo != NULL);
  68
  69   PciIo->Mem.Write (
  70                PciIo,
  71                EfiPciIoWidthUint32,
  72                EFI_AHCI_BAR_INDEX,
  73                (UINT64) Offset,
  74                1,
  75                &Data
  76                );
  77
  78   return ;
  79 }
  80
  81 /**
  82   Do AND operation with the value of AHCI Operation register.
  83
  84   @param  PciIo        The PCI IO protocol instance.
  85   @param  Offset       The operation register offset.
  86   @param  AndData      The data used to do AND operation.
  87
  88 **/
  89 VOID
  90 EFIAPI
  91 AhciAndReg (
  92   IN EFI_PCI_IO_PROTOCOL  *PciIo,
  93   IN UINT32               Offset,
  94   IN UINT32               AndData
  95   )
  96 {
  97   UINT32 Data;
  98
  99   ASSERT (PciIo != NULL);
 100
 101   Data  = AhciReadReg (PciIo, Offset);
 102
 103   Data &= AndData;
 104
 105   AhciWriteReg (PciIo, Offset, Data);
 106 }
 107
 108 /**
 109   Do OR operation with the value of AHCI Operation register.
 110
 111   @param  PciIo        The PCI IO protocol instance.
 112   @param  Offset       The operation register offset.
 113   @param  OrData       The data used to do OR operation.
 114
 115 **/
 116 VOID
 117 EFIAPI
 118 AhciOrReg (
 119   IN EFI_PCI_IO_PROTOCOL  *PciIo,
 120   IN UINT32               Offset,
 121   IN UINT32               OrData
 122   )
 123 {
 124   UINT32 Data;
 125
 126   ASSERT (PciIo != NULL);
 127
 128   Data  = AhciReadReg (PciIo, Offset);
 129
 130   Data |= OrData;
 131
 132   AhciWriteReg (PciIo, Offset, Data);
 133 }
 134
 135 /**
 136   Wait for the value of the specified MMIO register set to the test value.
 137
 138   @param  PciIo             The PCI IO protocol instance.
 139   @param  Offset            The MMIO address to test.
 140   @param  MaskValue         The mask value of memory.
 141   @param  TestValue         The test value of memory.
 142   @param  Timeout           The time out value for wait memory set, uses 100ns as a unit.
 143
 144   @retval EFI_TIMEOUT       The MMIO setting is time out.
 145   @retval EFI_SUCCESS       The MMIO is correct set.
 146
 147 **/
 148 EFI_STATUS
 149 EFIAPI
 150 AhciWaitMmioSet (
 151   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 152   IN  UINTN                     Offset,
 153   IN  UINT32                    MaskValue,
 154   IN  UINT32                    TestValue,
 155   IN  UINT64                    Timeout
 156   )
 157 {
 158   UINT32     Value;
 159   UINT64     Delay;
 160   BOOLEAN    InfiniteWait;
 161
 162   if (Timeout == 0) {
 163     InfiniteWait = TRUE;
 164   } else {
 165     InfiniteWait = FALSE;
 166   }
 167
 168   Delay = DivU64x32 (Timeout, 1000) + 1;
 169
 170   do {
 171     //
 172     // Access PCI MMIO space to see if the value is the tested one.
 173     //
 174     Value = AhciReadReg (PciIo, (UINT32) Offset) & MaskValue;
 175
 176     if (Value == TestValue) {
 177       return EFI_SUCCESS;
 178     }
 179
 180     //
 181     // Stall for 100 microseconds.
 182     //
 183     MicroSecondDelay (100);
 184
 185     Delay--;
 186
 187   } while (InfiniteWait || (Delay > 0));
 188
 189   return EFI_TIMEOUT;
 190 }
 191
 192 /**
 193   Wait for the value of the specified system memory set to the test value.
 194
 195   @param  Address           The system memory address to test.
 196   @param  MaskValue         The mask value of memory.
 197   @param  TestValue         The test value of memory.
 198   @param  Timeout           The time out value for wait memory set, uses 100ns as a unit.
 199
 200   @retval EFI_TIMEOUT       The system memory setting is time out.
 201   @retval EFI_SUCCESS       The system memory is correct set.
 202
 203 **/
 204 EFI_STATUS
 205 EFIAPI
 206 AhciWaitMemSet (
 207   IN  EFI_PHYSICAL_ADDRESS      Address,
 208   IN  UINT32                    MaskValue,
 209   IN  UINT32                    TestValue,
 210   IN  UINT64                    Timeout
 211   )
 212 {
 213   UINT32     Value;
 214   UINT64     Delay;
 215   BOOLEAN    InfiniteWait;
 216
 217   if (Timeout == 0) {
 218     InfiniteWait = TRUE;
 219   } else {
 220     InfiniteWait = FALSE;
 221   }
 222
 223   Delay =  DivU64x32 (Timeout, 1000) + 1;
 224
 225   do {
 226     //
 227     // Access sytem memory to see if the value is the tested one.
 228     //
 229     // The system memory pointed by Address will be updated by the
 230     // SATA Host Controller, "volatile" is introduced to prevent
 231     // compiler from optimizing the access to the memory address
 232     // to only read once.
 233     //
 234     Value  = *(volatile UINT32 *) (UINTN) Address;
 235     Value &= MaskValue;
 236
 237     if (Value == TestValue) {
 238       return EFI_SUCCESS;
 239     }
 240
 241     //
 242     // Stall for 100 microseconds.
 243     //
 244     MicroSecondDelay (100);
 245
 246     Delay--;
 247
 248   } while (InfiniteWait || (Delay > 0));
 249
 250   return EFI_TIMEOUT;
 251 }
 252
 253 /**
 254   Check the memory status to the test value.
 255
 256   @param[in]       Address           The memory address to test.
 257   @param[in]       MaskValue         The mask value of memory.
 258   @param[in]       TestValue         The test value of memory.
 259   @param[in, out]  Task              Optional. Pointer to the ATA_NONBLOCK_TASK used by
 260                                      non-blocking mode. If NULL, then just try once.
 261
 262   @retval EFI_NOTREADY      The memory is not set.
 263   @retval EFI_TIMEOUT       The memory setting retry times out.
 264   @retval EFI_SUCCESS       The memory is correct set.
 265
 266 **/
 267 EFI_STATUS
 268 EFIAPI
 269 AhciCheckMemSet (
 270   IN     UINTN                     Address,
 271   IN     UINT32                    MaskValue,
 272   IN     UINT32                    TestValue,
 273   IN OUT ATA_NONBLOCK_TASK         *Task
 274   )
 275 {
 276   UINT32     Value;
 277
 278   if (Task != NULL) {
 279     Task->RetryTimes--;
 280   }
 281
 282   Value  = *(volatile UINT32 *) Address;
 283   Value &= MaskValue;
 284
 285   if (Value == TestValue) {
 286     return EFI_SUCCESS;
 287   }
 288
 289   if ((Task != NULL) && !Task->InfiniteWait && (Task->RetryTimes == 0)) {
 290     return EFI_TIMEOUT;
 291   } else {
 292     return EFI_NOT_READY;
 293   }
 294 }
 295
 296 /**
 297   Check if the device is still on port. It also checks if the AHCI controller
 298   supports the address and data count will be transferred.
 299
 300   @param  PciIo            The PCI IO protocol instance.
 301   @param  Port             The number of port.
 302
 303   @retval EFI_SUCCESS      The device is attached to port and the transfer data is
 304                            supported by AHCI controller.
 305   @retval EFI_UNSUPPORTED  The transfer address and count is not supported by AHCI
 306                            controller.
 307   @retval EFI_NOT_READY    The physical communication between AHCI controller and device
 308                            is not ready.
 309
 310 **/
 311 EFI_STATUS
 312 EFIAPI
 313 AhciCheckDeviceStatus (
 314   IN  EFI_PCI_IO_PROTOCOL    *PciIo,
 315   IN  UINT8                  Port
 316   )
 317 {
 318   UINT32      Data;
 319   UINT32      Offset;
 320
 321   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
 322
 323   Data   = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_SSTS_DET_MASK;
 324
 325   if (Data == EFI_AHCI_PORT_SSTS_DET_PCE) {
 326     return EFI_SUCCESS;
 327   }
 328
 329   return EFI_NOT_READY;
 330 }
 331
 332 /**
 333
 334   Clear the port interrupt and error status. It will also clear
 335   HBA interrupt status.
 336
 337   @param      PciIo          The PCI IO protocol instance.
 338   @param      Port           The number of port.
 339
 340 **/
 341 VOID
 342 EFIAPI
 343 AhciClearPortStatus (
 344   IN  EFI_PCI_IO_PROTOCOL    *PciIo,
 345   IN  UINT8                  Port
 346   )
 347 {
 348   UINT32 Offset;
 349
 350   //
 351   // Clear any error status
 352   //
 353   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
 354   AhciWriteReg (PciIo, Offset, AhciReadReg (PciIo, Offset));
 355
 356   //
 357   // Clear any port interrupt status
 358   //
 359   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IS;
 360   AhciWriteReg (PciIo, Offset, AhciReadReg (PciIo, Offset));
 361
 362   //
 363   // Clear any HBA interrupt status
 364   //
 365   AhciWriteReg (PciIo, EFI_AHCI_IS_OFFSET, AhciReadReg (PciIo, EFI_AHCI_IS_OFFSET));
 366 }
 367
 368 /**
 369   This function is used to dump the Status Registers and if there is ERR bit set
 370   in the Status Register, the Error Register's value is also be dumped.
 371
 372   @param  PciIo            The PCI IO protocol instance.
 373   @param  Port             The number of port.
 374   @param  AtaStatusBlock   A pointer to EFI_ATA_STATUS_BLOCK data structure.
 375
 376 **/
 377 VOID
 378 EFIAPI
 379 AhciDumpPortStatus (
 380   IN     EFI_PCI_IO_PROTOCOL        *PciIo,
 381   IN     UINT8                      Port,
 382   IN OUT EFI_ATA_STATUS_BLOCK       *AtaStatusBlock
 383   )
 384 {
 385   UINT32               Offset;
 386   UINT32               Data;
 387
 388   ASSERT (PciIo != NULL);
 389
 390   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
 391   Data   = AhciReadReg (PciIo, Offset);
 392
 393   if (AtaStatusBlock != NULL) {
 394     ZeroMem (AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
 395
 396     AtaStatusBlock->AtaStatus  = (UINT8)Data;
 397     if ((AtaStatusBlock->AtaStatus & BIT0) != 0) {
 398       AtaStatusBlock->AtaError = (UINT8)(Data >> 8);
 399     }
 400   }
 401 }
 402
 403
 404 /**
 405   Enable the FIS running for giving port.
 406
 407   @param      PciIo          The PCI IO protocol instance.
 408   @param      Port           The number of port.
 409   @param      Timeout        The timeout value of enabling FIS, uses 100ns as a unit.
 410
 411   @retval EFI_DEVICE_ERROR   The FIS enable setting fails.
 412   @retval EFI_TIMEOUT        The FIS enable setting is time out.
 413   @retval EFI_SUCCESS        The FIS enable successfully.
 414
 415 **/
 416 EFI_STATUS
 417 EFIAPI
 418 AhciEnableFisReceive (
 419   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 420   IN  UINT8                     Port,
 421   IN  UINT64                    Timeout
 422   )
 423 {
 424   UINT32 Offset;
 425
 426   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
 427   AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);
 428
 429   return AhciWaitMmioSet (
 430            PciIo,
 431            Offset,
 432            EFI_AHCI_PORT_CMD_FR,
 433            EFI_AHCI_PORT_CMD_FR,
 434            Timeout
 435            );
 436 }
 437
 438 /**
 439   Disable the FIS running for giving port.
 440
 441   @param      PciIo          The PCI IO protocol instance.
 442   @param      Port           The number of port.
 443   @param      Timeout        The timeout value of disabling FIS, uses 100ns as a unit.
 444
 445   @retval EFI_DEVICE_ERROR   The FIS disable setting fails.
 446   @retval EFI_TIMEOUT        The FIS disable setting is time out.
 447   @retval EFI_UNSUPPORTED    The port is in running state.
 448   @retval EFI_SUCCESS        The FIS disable successfully.
 449
 450 **/
 451 EFI_STATUS
 452 EFIAPI
 453 AhciDisableFisReceive (
 454   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 455   IN  UINT8                     Port,
 456   IN  UINT64                    Timeout
 457   )
 458 {
 459   UINT32 Offset;
 460   UINT32 Data;
 461
 462   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
 463   Data   = AhciReadReg (PciIo, Offset);
 464
 465   //
 466   // Before disabling Fis receive, the DMA engine of the port should NOT be in running status.
 467   //
 468   if ((Data & (EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_CR)) != 0) {
 469     return EFI_UNSUPPORTED;
 470   }
 471
 472   //
 473   // Check if the Fis receive DMA engine for the port is running.
 474   //
 475   if ((Data & EFI_AHCI_PORT_CMD_FR) != EFI_AHCI_PORT_CMD_FR) {
 476     return EFI_SUCCESS;
 477   }
 478
 479   AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_FRE));
 480
 481   return AhciWaitMmioSet (
 482            PciIo,
 483            Offset,
 484            EFI_AHCI_PORT_CMD_FR,
 485            0,
 486            Timeout
 487            );
 488 }
 489
 490
 491
 492 /**
 493   Build the command list, command table and prepare the fis receiver.
 494
 495   @param    PciIo                 The PCI IO protocol instance.
 496   @param    AhciRegisters         The pointer to the EFI_AHCI_REGISTERS.
 497   @param    Port                  The number of port.
 498   @param    PortMultiplier        The timeout value of stop.
 499   @param    CommandFis            The control fis will be used for the transfer.
 500   @param    CommandList           The command list will be used for the transfer.
 501   @param    AtapiCommand          The atapi command will be used for the transfer.
 502   @param    AtapiCommandLength    The length of the atapi command.
 503   @param    CommandSlotNumber     The command slot will be used for the transfer.
 504   @param    DataPhysicalAddr      The pointer to the data buffer pci bus master address.
 505   @param    DataLength            The data count to be transferred.
 506
 507 **/
 508 VOID
 509 EFIAPI
 510 AhciBuildCommand (
 511   IN     EFI_PCI_IO_PROTOCOL        *PciIo,
 512   IN     EFI_AHCI_REGISTERS         *AhciRegisters,
 513   IN     UINT8                      Port,
 514   IN     UINT8                      PortMultiplier,
 515   IN     EFI_AHCI_COMMAND_FIS       *CommandFis,
 516   IN     EFI_AHCI_COMMAND_LIST      *CommandList,
 517   IN     EFI_AHCI_ATAPI_COMMAND     *AtapiCommand OPTIONAL,
 518   IN     UINT8                      AtapiCommandLength,
 519   IN     UINT8                      CommandSlotNumber,
 520   IN OUT VOID                       *DataPhysicalAddr,
 521   IN     UINT32                     DataLength
 522   )
 523 {
 524   UINT64     BaseAddr;
 525   UINT32     PrdtNumber;
 526   UINT32     PrdtIndex;
 527   UINTN      RemainedData;
 528   UINTN      MemAddr;
 529   DATA_64    Data64;
 530   UINT32     Offset;
 531
 532   //
 533   // Filling the PRDT
 534   //
 535   PrdtNumber = (UINT32)DivU64x32 (((UINT64)DataLength + EFI_AHCI_MAX_DATA_PER_PRDT - 1), EFI_AHCI_MAX_DATA_PER_PRDT);
 536
 537   //
 538   // According to AHCI 1.3 spec, a PRDT entry can point to a maximum 4MB data block.
 539   // It also limits that the maximum amount of the PRDT entry in the command table
 540   // is 65535.
 541   //
 542   ASSERT (PrdtNumber <= 65535);
 543
 544   Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFis) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
 545
 546   BaseAddr = Data64.Uint64;
 547
 548   ZeroMem ((VOID *)((UINTN) BaseAddr), sizeof (EFI_AHCI_RECEIVED_FIS));
 549
 550   ZeroMem (AhciRegisters->AhciCommandTable, sizeof (EFI_AHCI_COMMAND_TABLE));
 551
 552   CommandFis->AhciCFisPmNum = PortMultiplier;
 553
 554   CopyMem (&AhciRegisters->AhciCommandTable->CommandFis, CommandFis, sizeof (EFI_AHCI_COMMAND_FIS));
 555
 556   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
 557   if (AtapiCommand != NULL) {
 558     CopyMem (
 559       &AhciRegisters->AhciCommandTable->AtapiCmd,
 560       AtapiCommand,
 561       AtapiCommandLength
 562       );
 563
 564     CommandList->AhciCmdA = 1;
 565     CommandList->AhciCmdP = 1;
 566
 567     AhciOrReg (PciIo, Offset, (EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
 568   } else {
 569     AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_DLAE | EFI_AHCI_PORT_CMD_ATAPI));
 570   }
 571
 572   RemainedData = (UINTN) DataLength;
 573   MemAddr      = (UINTN) DataPhysicalAddr;
 574   CommandList->AhciCmdPrdtl = PrdtNumber;
 575
 576   for (PrdtIndex = 0; PrdtIndex < PrdtNumber; PrdtIndex++) {
 577     if (RemainedData < EFI_AHCI_MAX_DATA_PER_PRDT) {
 578       AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = (UINT32)RemainedData - 1;
 579     } else {
 580       AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbc = EFI_AHCI_MAX_DATA_PER_PRDT - 1;
 581     }
 582
 583     Data64.Uint64 = (UINT64)MemAddr;
 584     AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDba  = Data64.Uint32.Lower32;
 585     AhciRegisters->AhciCommandTable->PrdtTable[PrdtIndex].AhciPrdtDbau = Data64.Uint32.Upper32;
 586     RemainedData -= EFI_AHCI_MAX_DATA_PER_PRDT;
 587     MemAddr      += EFI_AHCI_MAX_DATA_PER_PRDT;
 588   }
 589
 590   //
 591   // Set the last PRDT to Interrupt On Complete
 592   //
 593   if (PrdtNumber > 0) {
 594     AhciRegisters->AhciCommandTable->PrdtTable[PrdtNumber - 1].AhciPrdtIoc = 1;
 595   }
 596
 597   CopyMem (
 598     (VOID *) ((UINTN) AhciRegisters->AhciCmdList + (UINTN) CommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST)),
 599     CommandList,
 600     sizeof (EFI_AHCI_COMMAND_LIST)
 601     );
 602
 603   Data64.Uint64 = (UINT64)(UINTN) AhciRegisters->AhciCommandTablePciAddr;
 604   AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtba  = Data64.Uint32.Lower32;
 605   AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdCtbau = Data64.Uint32.Upper32;
 606   AhciRegisters->AhciCmdList[CommandSlotNumber].AhciCmdPmp   = PortMultiplier;
 607
 608 }
 609
 610 /**
 611   Buid a command FIS.
 612
 613   @param  CmdFis            A pointer to the EFI_AHCI_COMMAND_FIS data structure.
 614   @param  AtaCommandBlock   A pointer to the AhciBuildCommandFis data structure.
 615
 616 **/
 617 VOID
 618 EFIAPI
 619 AhciBuildCommandFis (
 620   IN OUT EFI_AHCI_COMMAND_FIS    *CmdFis,
 621   IN     EFI_ATA_COMMAND_BLOCK   *AtaCommandBlock
 622   )
 623 {
 624   ZeroMem (CmdFis, sizeof (EFI_AHCI_COMMAND_FIS));
 625
 626   CmdFis->AhciCFisType = EFI_AHCI_FIS_REGISTER_H2D;
 627   //
 628   // Indicator it's a command
 629   //
 630   CmdFis->AhciCFisCmdInd      = 0x1;
 631   CmdFis->AhciCFisCmd         = AtaCommandBlock->AtaCommand;
 632
 633   CmdFis->AhciCFisFeature     = AtaCommandBlock->AtaFeatures;
 634   CmdFis->AhciCFisFeatureExp  = AtaCommandBlock->AtaFeaturesExp;
 635
 636   CmdFis->AhciCFisSecNum      = AtaCommandBlock->AtaSectorNumber;
 637   CmdFis->AhciCFisSecNumExp   = AtaCommandBlock->AtaSectorNumberExp;
 638
 639   CmdFis->AhciCFisClyLow      = AtaCommandBlock->AtaCylinderLow;
 640   CmdFis->AhciCFisClyLowExp   = AtaCommandBlock->AtaCylinderLowExp;
 641
 642   CmdFis->AhciCFisClyHigh     = AtaCommandBlock->AtaCylinderHigh;
 643   CmdFis->AhciCFisClyHighExp  = AtaCommandBlock->AtaCylinderHighExp;
 644
 645   CmdFis->AhciCFisSecCount    = AtaCommandBlock->AtaSectorCount;
 646   CmdFis->AhciCFisSecCountExp = AtaCommandBlock->AtaSectorCountExp;
 647
 648   CmdFis->AhciCFisDevHead     = (UINT8) (AtaCommandBlock->AtaDeviceHead | 0xE0);
 649 }
 650
 651 /**
 652   Start a PIO data transfer on specific port.
 653
 654   @param[in]       PciIo               The PCI IO protocol instance.
 655   @param[in]       AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
 656   @param[in]       Port                The number of port.
 657   @param[in]       PortMultiplier      The timeout value of stop.
 658   @param[in]       AtapiCommand        The atapi command will be used for the
 659                                        transfer.
 660   @param[in]       AtapiCommandLength  The length of the atapi command.
 661   @param[in]       Read                The transfer direction.
 662   @param[in]       AtaCommandBlock     The EFI_ATA_COMMAND_BLOCK data.
 663   @param[in, out]  AtaStatusBlock      The EFI_ATA_STATUS_BLOCK data.
 664   @param[in, out]  MemoryAddr          The pointer to the data buffer.
 665   @param[in]       DataCount           The data count to be transferred.
 666   @param[in]       Timeout             The timeout value of non data transfer, uses 100ns as a unit.
 667   @param[in]       Task                Optional. Pointer to the ATA_NONBLOCK_TASK
 668                                        used by non-blocking mode.
 669
 670   @retval EFI_DEVICE_ERROR    The PIO data transfer abort with error occurs.
 671   @retval EFI_TIMEOUT         The operation is time out.
 672   @retval EFI_UNSUPPORTED     The device is not ready for transfer.
 673   @retval EFI_SUCCESS         The PIO data transfer executes successfully.
 674
 675 **/
 676 EFI_STATUS
 677 EFIAPI
 678 AhciPioTransfer (
 679   IN     EFI_PCI_IO_PROTOCOL        *PciIo,
 680   IN     EFI_AHCI_REGISTERS         *AhciRegisters,
 681   IN     UINT8                      Port,
 682   IN     UINT8                      PortMultiplier,
 683   IN     EFI_AHCI_ATAPI_COMMAND     *AtapiCommand OPTIONAL,
 684   IN     UINT8                      AtapiCommandLength,
 685   IN     BOOLEAN                    Read,
 686   IN     EFI_ATA_COMMAND_BLOCK      *AtaCommandBlock,
 687   IN OUT EFI_ATA_STATUS_BLOCK       *AtaStatusBlock,
 688   IN OUT VOID                       *MemoryAddr,
 689   IN     UINT32                     DataCount,
 690   IN     UINT64                     Timeout,
 691   IN     ATA_NONBLOCK_TASK          *Task
 692   )
 693 {
 694   EFI_STATUS                    Status;
 695   UINTN                         FisBaseAddr;
 696   UINTN                         Offset;
 697   EFI_PHYSICAL_ADDRESS          PhyAddr;
 698   VOID                          *Map;
 699   UINTN                         MapLength;
 700   EFI_PCI_IO_PROTOCOL_OPERATION Flag;
 701   UINT64                        Delay;
 702   EFI_AHCI_COMMAND_FIS          CFis;
 703   EFI_AHCI_COMMAND_LIST         CmdList;
 704   UINT32                        PortTfd;
 705   UINT32                        PrdCount;
 706   BOOLEAN                       InfiniteWait;
 707   BOOLEAN                       PioFisReceived;
 708   BOOLEAN                       D2hFisReceived;
 709
 710   if (Timeout == 0) {
 711     InfiniteWait = TRUE;
 712   } else {
 713     InfiniteWait = FALSE;
 714   }
 715
 716   if (Read) {
 717     Flag = EfiPciIoOperationBusMasterWrite;
 718   } else {
 719     Flag = EfiPciIoOperationBusMasterRead;
 720   }
 721
 722   //
 723   // construct command list and command table with pci bus address
 724   //
 725   MapLength = DataCount;
 726   Status = PciIo->Map (
 727                     PciIo,
 728                     Flag,
 729                     MemoryAddr,
 730                     &MapLength,
 731                     &PhyAddr,
 732                     &Map
 733                     );
 734
 735   if (EFI_ERROR (Status) || (DataCount != MapLength)) {
 736     return EFI_BAD_BUFFER_SIZE;
 737   }
 738
 739   //
 740   // Package read needed
 741   //
 742   AhciBuildCommandFis (&CFis, AtaCommandBlock);
 743
 744   ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
 745
 746   CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
 747   CmdList.AhciCmdW   = Read ? 0 : 1;
 748
 749   AhciBuildCommand (
 750     PciIo,
 751     AhciRegisters,
 752     Port,
 753     PortMultiplier,
 754     &CFis,
 755     &CmdList,
 756     AtapiCommand,
 757     AtapiCommandLength,
 758     0,
 759     (VOID *)(UINTN)PhyAddr,
 760     DataCount
 761     );
 762
 763   Status = AhciStartCommand (
 764              PciIo,
 765              Port,
 766              0,
 767              Timeout
 768              );
 769   if (EFI_ERROR (Status)) {
 770     goto Exit;
 771   }
 772
 773   //
 774   // Check the status and wait the driver sending data
 775   //
 776   FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
 777
 778   if (Read && (AtapiCommand == 0)) {
 779     //
 780     // Wait device sends the PIO setup fis before data transfer
 781     //
 782     Status = EFI_TIMEOUT;
 783     Delay  = DivU64x32 (Timeout, 1000) + 1;
 784     do {
 785       PioFisReceived = FALSE;
 786       D2hFisReceived = FALSE;
 787       Offset = FisBaseAddr + EFI_AHCI_PIO_FIS_OFFSET;
 788       Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_PIO_SETUP, NULL);
 789       if (!EFI_ERROR (Status)) {
 790         PioFisReceived = TRUE;
 791       }
 792       //
 793       // According to SATA 2.6 spec section 11.7, D2h FIS means an error encountered.
 794       // But Qemu and Marvel 9230 sata controller may just receive a D2h FIS from device
 795       // after the transaction is finished successfully.
 796       // To get better device compatibilities, we further check if the PxTFD's ERR bit is set.
 797       // By this way, we can know if there is a real error happened.
 798       //
 799       Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
 800       Status = AhciCheckMemSet (Offset, EFI_AHCI_FIS_TYPE_MASK, EFI_AHCI_FIS_REGISTER_D2H, NULL);
 801       if (!EFI_ERROR (Status)) {
 802         D2hFisReceived = TRUE;
 803       }
 804
 805       if (PioFisReceived || D2hFisReceived) {
 806         Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
 807         PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
 808         //
 809         // PxTFD will be updated if there is a D2H or SetupFIS received.
 810         //
 811         if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
 812           Status = EFI_DEVICE_ERROR;
 813           break;
 814         }
 815
 816         PrdCount = *(volatile UINT32 *) (&(AhciRegisters->AhciCmdList[0].AhciCmdPrdbc));
 817         if (PrdCount == DataCount) {
 818           Status = EFI_SUCCESS;
 819           break;
 820         }
 821       }
 822
 823       //
 824       // Stall for 100 microseconds.
 825       //
 826       MicroSecondDelay(100);
 827
 828       Delay--;
 829       if (Delay == 0) {
 830         Status = EFI_TIMEOUT;
 831       }
 832     } while (InfiniteWait || (Delay > 0));
 833   } else {
 834     //
 835     // Wait for D2H Fis is received
 836     //
 837     Offset = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
 838     Status = AhciWaitMemSet (
 839                Offset,
 840                EFI_AHCI_FIS_TYPE_MASK,
 841                EFI_AHCI_FIS_REGISTER_D2H,
 842                Timeout
 843                );
 844
 845     if (EFI_ERROR (Status)) {
 846       goto Exit;
 847     }
 848
 849     Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
 850     PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
 851     if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
 852       Status = EFI_DEVICE_ERROR;
 853     }
 854   }
 855
 856 Exit:
 857   AhciStopCommand (
 858     PciIo,
 859     Port,
 860     Timeout
 861     );
 862
 863   AhciDisableFisReceive (
 864     PciIo,
 865     Port,
 866     Timeout
 867     );
 868
 869   PciIo->Unmap (
 870     PciIo,
 871     Map
 872     );
 873
 874   AhciDumpPortStatus (PciIo, Port, AtaStatusBlock);
 875
 876   return Status;
 877 }
 878
 879 /**
 880   Start a DMA data transfer on specific port
 881
 882   @param[in]       Instance            The ATA_ATAPI_PASS_THRU_INSTANCE protocol instance.
 883   @param[in]       AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
 884   @param[in]       Port                The number of port.
 885   @param[in]       PortMultiplier      The timeout value of stop.
 886   @param[in]       AtapiCommand        The atapi command will be used for the
 887                                        transfer.
 888   @param[in]       AtapiCommandLength  The length of the atapi command.
 889   @param[in]       Read                The transfer direction.
 890   @param[in]       AtaCommandBlock     The EFI_ATA_COMMAND_BLOCK data.
 891   @param[in, out]  AtaStatusBlock      The EFI_ATA_STATUS_BLOCK data.
 892   @param[in, out]  MemoryAddr          The pointer to the data buffer.
 893   @param[in]       DataCount           The data count to be transferred.
 894   @param[in]       Timeout             The timeout value of non data transfer, uses 100ns as a unit.
 895   @param[in]       Task                Optional. Pointer to the ATA_NONBLOCK_TASK
 896                                        used by non-blocking mode.
 897
 898   @retval EFI_DEVICE_ERROR    The DMA data transfer abort with error occurs.
 899   @retval EFI_TIMEOUT         The operation is time out.
 900   @retval EFI_UNSUPPORTED     The device is not ready for transfer.
 901   @retval EFI_SUCCESS         The DMA data transfer executes successfully.
 902
 903 **/
 904 EFI_STATUS
 905 EFIAPI
 906 AhciDmaTransfer (
 907   IN     ATA_ATAPI_PASS_THRU_INSTANCE *Instance,
 908   IN     EFI_AHCI_REGISTERS         *AhciRegisters,
 909   IN     UINT8                      Port,
 910   IN     UINT8                      PortMultiplier,
 911   IN     EFI_AHCI_ATAPI_COMMAND     *AtapiCommand OPTIONAL,
 912   IN     UINT8                      AtapiCommandLength,
 913   IN     BOOLEAN                    Read,
 914   IN     EFI_ATA_COMMAND_BLOCK      *AtaCommandBlock,
 915   IN OUT EFI_ATA_STATUS_BLOCK       *AtaStatusBlock,
 916   IN OUT VOID                       *MemoryAddr,
 917   IN     UINT32                     DataCount,
 918   IN     UINT64                     Timeout,
 919   IN     ATA_NONBLOCK_TASK          *Task
 920   )
 921 {
 922   EFI_STATUS                    Status;
 923   UINTN                         Offset;
 924   EFI_PHYSICAL_ADDRESS          PhyAddr;
 925   VOID                          *Map;
 926   UINTN                         MapLength;
 927   EFI_PCI_IO_PROTOCOL_OPERATION Flag;
 928   EFI_AHCI_COMMAND_FIS          CFis;
 929   EFI_AHCI_COMMAND_LIST         CmdList;
 930   UINTN                         FisBaseAddr;
 931   UINT32                        PortTfd;
 932
 933   EFI_PCI_IO_PROTOCOL           *PciIo;
 934   EFI_TPL                       OldTpl;
 935
 936   Map   = NULL;
 937   PciIo = Instance->PciIo;
 938
 939   if (PciIo == NULL) {
 940     return EFI_INVALID_PARAMETER;
 941   }
 942
 943   //
 944   // Before starting the Blocking BlockIO operation, push to finish all non-blocking
 945   // BlockIO tasks.
 946   // Delay 100us to simulate the blocking time out checking.
 947   //
 948   OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
 949   while ((Task == NULL) && (!IsListEmpty (&Instance->NonBlockingTaskList))) {
 950     AsyncNonBlockingTransferRoutine (NULL, Instance);
 951     //
 952     // Stall for 100us.
 953     //
 954     MicroSecondDelay (100);
 955   }
 956   gBS->RestoreTPL (OldTpl);
 957
 958   if ((Task == NULL) || ((Task != NULL) && (!Task->IsStart))) {
 959     //
 960     // Mark the Task to indicate that it has been started.
 961     //
 962     if (Task != NULL) {
 963       Task->IsStart      = TRUE;
 964     }
 965     if (Read) {
 966       Flag = EfiPciIoOperationBusMasterWrite;
 967     } else {
 968       Flag = EfiPciIoOperationBusMasterRead;
 969     }
 970
 971     //
 972     // Construct command list and command table with pci bus address.
 973     //
 974     MapLength = DataCount;
 975     Status = PciIo->Map (
 976                       PciIo,
 977                       Flag,
 978                       MemoryAddr,
 979                       &MapLength,
 980                       &PhyAddr,
 981                       &Map
 982                       );
 983
 984     if (EFI_ERROR (Status) || (DataCount != MapLength)) {
 985       return EFI_BAD_BUFFER_SIZE;
 986     }
 987
 988     if (Task != NULL) {
 989       Task->Map = Map;
 990     }
 991     //
 992     // Package read needed
 993     //
 994     AhciBuildCommandFis (&CFis, AtaCommandBlock);
 995
 996     ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
 997
 998     CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
 999     CmdList.AhciCmdW   = Read ? 0 : 1;
1000
1001     AhciBuildCommand (
1002       PciIo,
1003       AhciRegisters,
1004       Port,
1005       PortMultiplier,
1006       &CFis,
1007       &CmdList,
1008       AtapiCommand,
1009       AtapiCommandLength,
1010       0,
1011       (VOID *)(UINTN)PhyAddr,
1012       DataCount
1013       );
1014
1015     Status = AhciStartCommand (
1016                PciIo,
1017                Port,
1018                0,
1019                Timeout
1020                );
1021     if (EFI_ERROR (Status)) {
1022       goto Exit;
1023     }
1024   }
1025
1026   //
1027   // Wait for command compelte
1028   //
1029   FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
1030   Offset      = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
1031   if (Task != NULL) {
1032     //
1033     // For Non-blocking
1034     //
1035     Status = AhciCheckMemSet (
1036                Offset,
1037                EFI_AHCI_FIS_TYPE_MASK,
1038                EFI_AHCI_FIS_REGISTER_D2H,
1039                Task
1040                );
1041   } else {
1042     Status = AhciWaitMemSet (
1043                Offset,
1044                EFI_AHCI_FIS_TYPE_MASK,
1045                EFI_AHCI_FIS_REGISTER_D2H,
1046                Timeout
1047                );
1048   }
1049
1050   if (EFI_ERROR (Status)) {
1051     goto Exit;
1052   }
1053
1054   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
1055   PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
1056   if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
1057     Status = EFI_DEVICE_ERROR;
1058   }
1059
1060 Exit:
1061   //
1062   // For Blocking mode, the command should be stopped, the Fis should be disabled
1063   // and the PciIo should be unmapped.
1064   // For non-blocking mode, only when a error is happened (if the return status is
1065   // EFI_NOT_READY that means the command doesn't finished, try again.), first do the
1066   // context cleanup, then set the packet's Asb status.
1067   //
1068   if (Task == NULL ||
1069       ((Task != NULL) && (Status != EFI_NOT_READY))
1070      ) {
1071     AhciStopCommand (
1072       PciIo,
1073       Port,
1074       Timeout
1075       );
1076
1077     AhciDisableFisReceive (
1078       PciIo,
1079       Port,
1080       Timeout
1081       );
1082
1083     PciIo->Unmap (
1084              PciIo,
1085              (Task != NULL) ? Task->Map : Map
1086              );
1087
1088     if (Task != NULL) {
1089       Task->Packet->Asb->AtaStatus = 0x01;
1090     }
1091   }
1092
1093   AhciDumpPortStatus (PciIo, Port, AtaStatusBlock);
1094   return Status;
1095 }
1096
1097 /**
1098   Start a non data transfer on specific port.
1099
1100   @param[in]       PciIo               The PCI IO protocol instance.
1101   @param[in]       AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
1102   @param[in]       Port                The number of port.
1103   @param[in]       PortMultiplier      The timeout value of stop.
1104   @param[in]       AtapiCommand        The atapi command will be used for the
1105                                        transfer.
1106   @param[in]       AtapiCommandLength  The length of the atapi command.
1107   @param[in]       AtaCommandBlock     The EFI_ATA_COMMAND_BLOCK data.
1108   @param[in, out]  AtaStatusBlock      The EFI_ATA_STATUS_BLOCK data.
1109   @param[in]       Timeout             The timeout value of non data transfer, uses 100ns as a unit.
1110   @param[in]       Task                Optional. Pointer to the ATA_NONBLOCK_TASK
1111                                        used by non-blocking mode.
1112
1113   @retval EFI_DEVICE_ERROR    The non data transfer abort with error occurs.
1114   @retval EFI_TIMEOUT         The operation is time out.
1115   @retval EFI_UNSUPPORTED     The device is not ready for transfer.
1116   @retval EFI_SUCCESS         The non data transfer executes successfully.
1117
1118 **/
1119 EFI_STATUS
1120 EFIAPI
1121 AhciNonDataTransfer (
1122   IN     EFI_PCI_IO_PROTOCOL           *PciIo,
1123   IN     EFI_AHCI_REGISTERS            *AhciRegisters,
1124   IN     UINT8                         Port,
1125   IN     UINT8                         PortMultiplier,
1126   IN     EFI_AHCI_ATAPI_COMMAND        *AtapiCommand OPTIONAL,
1127   IN     UINT8                         AtapiCommandLength,
1128   IN     EFI_ATA_COMMAND_BLOCK         *AtaCommandBlock,
1129   IN OUT EFI_ATA_STATUS_BLOCK          *AtaStatusBlock,
1130   IN     UINT64                        Timeout,
1131   IN     ATA_NONBLOCK_TASK             *Task
1132   )
1133 {
1134   EFI_STATUS                   Status;
1135   UINTN                        FisBaseAddr;
1136   UINTN                        Offset;
1137   UINT32                       PortTfd;
1138   EFI_AHCI_COMMAND_FIS         CFis;
1139   EFI_AHCI_COMMAND_LIST        CmdList;
1140
1141   //
1142   // Package read needed
1143   //
1144   AhciBuildCommandFis (&CFis, AtaCommandBlock);
1145
1146   ZeroMem (&CmdList, sizeof (EFI_AHCI_COMMAND_LIST));
1147
1148   CmdList.AhciCmdCfl = EFI_AHCI_FIS_REGISTER_H2D_LENGTH / 4;
1149
1150   AhciBuildCommand (
1151     PciIo,
1152     AhciRegisters,
1153     Port,
1154     PortMultiplier,
1155     &CFis,
1156     &CmdList,
1157     AtapiCommand,
1158     AtapiCommandLength,
1159     0,
1160     NULL,
1161     0
1162     );
1163
1164   Status = AhciStartCommand (
1165              PciIo,
1166              Port,
1167              0,
1168              Timeout
1169              );
1170   if (EFI_ERROR (Status)) {
1171     goto Exit;
1172   }
1173
1174   //
1175   // Wait device sends the Response Fis
1176   //
1177   FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
1178   Offset      = FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET;
1179   Status      = AhciWaitMemSet (
1180                   Offset,
1181                   EFI_AHCI_FIS_TYPE_MASK,
1182                   EFI_AHCI_FIS_REGISTER_D2H,
1183                   Timeout
1184                   );
1185
1186   if (EFI_ERROR (Status)) {
1187     goto Exit;
1188   }
1189
1190   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
1191   PortTfd = AhciReadReg (PciIo, (UINT32) Offset);
1192   if ((PortTfd & EFI_AHCI_PORT_TFD_ERR) != 0) {
1193     Status = EFI_DEVICE_ERROR;
1194   }
1195
1196 Exit:
1197   AhciStopCommand (
1198     PciIo,
1199     Port,
1200     Timeout
1201     );
1202
1203   AhciDisableFisReceive (
1204     PciIo,
1205     Port,
1206     Timeout
1207     );
1208
1209   AhciDumpPortStatus (PciIo, Port, AtaStatusBlock);
1210
1211   return Status;
1212 }
1213
1214 /**
1215   Stop command running for giving port
1216
1217   @param  PciIo              The PCI IO protocol instance.
1218   @param  Port               The number of port.
1219   @param  Timeout            The timeout value of stop, uses 100ns as a unit.
1220
1221   @retval EFI_DEVICE_ERROR   The command stop unsuccessfully.
1222   @retval EFI_TIMEOUT        The operation is time out.
1223   @retval EFI_SUCCESS        The command stop successfully.
1224
1225 **/
1226 EFI_STATUS
1227 EFIAPI
1228 AhciStopCommand (
1229   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
1230   IN  UINT8                     Port,
1231   IN  UINT64                    Timeout
1232   )
1233 {
1234   UINT32 Offset;
1235   UINT32 Data;
1236
1237   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1238   Data   = AhciReadReg (PciIo, Offset);
1239
1240   if ((Data & (EFI_AHCI_PORT_CMD_ST |  EFI_AHCI_PORT_CMD_CR)) == 0) {
1241     return EFI_SUCCESS;
1242   }
1243
1244   if ((Data & EFI_AHCI_PORT_CMD_ST) != 0) {
1245     AhciAndReg (PciIo, Offset, (UINT32)~(EFI_AHCI_PORT_CMD_ST));
1246   }
1247
1248   return AhciWaitMmioSet (
1249            PciIo,
1250            Offset,
1251            EFI_AHCI_PORT_CMD_CR,
1252            0,
1253            Timeout
1254            );
1255 }
1256
1257 /**
1258   Start command for give slot on specific port.
1259
1260   @param  PciIo              The PCI IO protocol instance.
1261   @param  Port               The number of port.
1262   @param  CommandSlot        The number of Command Slot.
1263   @param  Timeout            The timeout value of start, uses 100ns as a unit.
1264
1265   @retval EFI_DEVICE_ERROR   The command start unsuccessfully.
1266   @retval EFI_TIMEOUT        The operation is time out.
1267   @retval EFI_SUCCESS        The command start successfully.
1268
1269 **/
1270 EFI_STATUS
1271 EFIAPI
1272 AhciStartCommand (
1273   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
1274   IN  UINT8                     Port,
1275   IN  UINT8                     CommandSlot,
1276   IN  UINT64                    Timeout
1277   )
1278 {
1279   UINT32     CmdSlotBit;
1280   EFI_STATUS Status;
1281   UINT32     PortStatus;
1282   UINT32     StartCmd;
1283   UINT32     PortTfd;
1284   UINT32     Offset;
1285   UINT32     Capability;
1286
1287   //
1288   // Collect AHCI controller information
1289   //
1290   Capability = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
1291
1292   CmdSlotBit = (UINT32) (1 << CommandSlot);
1293
1294   AhciClearPortStatus (
1295     PciIo,
1296     Port
1297     );
1298
1299   Status = AhciEnableFisReceive (
1300              PciIo,
1301              Port,
1302              Timeout
1303              );
1304
1305   if (EFI_ERROR (Status)) {
1306     return Status;
1307   }
1308
1309   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1310   PortStatus = AhciReadReg (PciIo, Offset);
1311
1312   StartCmd = 0;
1313   if ((PortStatus & EFI_AHCI_PORT_CMD_ALPE) != 0) {
1314     StartCmd = AhciReadReg (PciIo, Offset);
1315     StartCmd &= ~EFI_AHCI_PORT_CMD_ICC_MASK;
1316     StartCmd |= EFI_AHCI_PORT_CMD_ACTIVE;
1317   }
1318
1319   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
1320   PortTfd = AhciReadReg (PciIo, Offset);
1321
1322   if ((PortTfd & (EFI_AHCI_PORT_TFD_BSY | EFI_AHCI_PORT_TFD_DRQ)) != 0) {
1323     if ((Capability & BIT24) != 0) {
1324       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1325       AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_CLO);
1326
1327       AhciWaitMmioSet (
1328         PciIo,
1329         Offset,
1330         EFI_AHCI_PORT_CMD_CLO,
1331         0,
1332         Timeout
1333         );
1334     }
1335   }
1336
1337   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
1338   AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_ST | StartCmd);
1339
1340   //
1341   // Setting the command
1342   //
1343   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SACT;
1344   AhciAndReg (PciIo, Offset, 0);
1345   AhciOrReg (PciIo, Offset, CmdSlotBit);
1346
1347   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CI;
1348   AhciAndReg (PciIo, Offset, 0);
1349   AhciOrReg (PciIo, Offset, CmdSlotBit);
1350
1351   return EFI_SUCCESS;
1352 }
1353
1354 /**
1355   Do AHCI port reset.
1356
1357   @param  PciIo              The PCI IO protocol instance.
1358   @param  Port               The number of port.
1359   @param  Timeout            The timeout value of reset, uses 100ns as a unit.
1360
1361   @retval EFI_DEVICE_ERROR   The port reset unsuccessfully
1362   @retval EFI_TIMEOUT        The reset operation is time out.
1363   @retval EFI_SUCCESS        The port reset successfully.
1364
1365 **/
1366 EFI_STATUS
1367 EFIAPI
1368 AhciPortReset (
1369   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
1370   IN  UINT8                     Port,
1371   IN  UINT64                    Timeout
1372   )
1373 {
1374   EFI_STATUS      Status;
1375   UINT32          Offset;
1376
1377   AhciClearPortStatus (PciIo, Port);
1378
1379   AhciStopCommand (PciIo, Port, Timeout);
1380
1381   AhciDisableFisReceive (PciIo, Port, Timeout);
1382
1383   AhciEnableFisReceive (PciIo, Port, Timeout);
1384
1385   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;
1386
1387   AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_SCTL_DET_INIT);
1388
1389   //
1390   // wait 5 millisecond before de-assert DET
1391   //
1392   MicroSecondDelay (5000);
1393
1394   AhciAndReg (PciIo, Offset, (UINT32)EFI_AHCI_PORT_SCTL_MASK);
1395
1396   //
1397   // wait 5 millisecond before de-assert DET
1398   //
1399   MicroSecondDelay (5000);
1400
1401   //
1402   // Wait for communication to be re-established
1403   //
1404   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
1405   Status = AhciWaitMmioSet (
1406              PciIo,
1407              Offset,
1408              EFI_AHCI_PORT_SSTS_DET_MASK,
1409              EFI_AHCI_PORT_SSTS_DET_PCE,
1410              Timeout
1411              );
1412
1413   if (EFI_ERROR (Status)) {
1414     return Status;
1415   }
1416
1417   Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
1418   AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_ERR_CLEAR);
1419
1420   return EFI_SUCCESS;
1421 }
1422
1423 /**
1424   Do AHCI HBA reset.
1425
1426   @param  PciIo              The PCI IO protocol instance.
1427   @param  Timeout            The timeout value of reset, uses 100ns as a unit.
1428
1429   @retval EFI_DEVICE_ERROR   AHCI controller is failed to complete hardware reset.
1430   @retval EFI_TIMEOUT        The reset operation is time out.
1431   @retval EFI_SUCCESS        AHCI controller is reset successfully.
1432
1433 **/
1434 EFI_STATUS
1435 EFIAPI
1436 AhciReset (
1437   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
1438   IN  UINT64                    Timeout
1439   )
1440 {
1441   UINT64                 Delay;
1442   UINT32                 Value;
1443
1444   AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
1445
1446   AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_RESET);
1447
1448   Delay = DivU64x32(Timeout, 1000) + 1;
1449
1450   do {
1451     Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET);
1452
1453     if ((Value & EFI_AHCI_GHC_RESET) == 0) {
1454       break;
1455     }
1456
1457     //
1458     // Stall for 100 microseconds.
1459     //
1460     MicroSecondDelay(100);
1461
1462     Delay--;
1463   } while (Delay > 0);
1464
1465   if (Delay == 0) {
1466     return EFI_TIMEOUT;
1467   }
1468
1469   return EFI_SUCCESS;
1470 }
1471
1472 /**
1473   Send SMART Return Status command to check if the execution of SMART cmd is successful or not.
1474
1475   @param  PciIo               The PCI IO protocol instance.
1476   @param  AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
1477   @param  Port                The number of port.
1478   @param  PortMultiplier      The timeout value of stop.
1479   @param  AtaStatusBlock      A pointer to EFI_ATA_STATUS_BLOCK data structure.
1480
1481   @retval EFI_SUCCESS     Successfully get the return status of S.M.A.R.T command execution.
1482   @retval Others          Fail to get return status data.
1483
1484 **/
1485 EFI_STATUS
1486 EFIAPI
1487 AhciAtaSmartReturnStatusCheck (
1488   IN EFI_PCI_IO_PROTOCOL         *PciIo,
1489   IN EFI_AHCI_REGISTERS          *AhciRegisters,
1490   IN UINT8                       Port,
1491   IN UINT8                       PortMultiplier,
1492   IN OUT EFI_ATA_STATUS_BLOCK    *AtaStatusBlock
1493   )
1494 {
1495   EFI_STATUS              Status;
1496   EFI_ATA_COMMAND_BLOCK   AtaCommandBlock;
1497   UINT8                   LBAMid;
1498   UINT8                   LBAHigh;
1499   UINTN                   FisBaseAddr;
1500   UINT32                  Value;
1501
1502   ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1503
1504   AtaCommandBlock.AtaCommand      = ATA_CMD_SMART;
1505   AtaCommandBlock.AtaFeatures     = ATA_SMART_RETURN_STATUS;
1506   AtaCommandBlock.AtaCylinderLow  = ATA_CONSTANT_4F;
1507   AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
1508
1509   //
1510   // Send S.M.A.R.T Read Return Status command to device
1511   //
1512   Status = AhciNonDataTransfer (
1513              PciIo,
1514              AhciRegisters,
1515              (UINT8)Port,
1516              (UINT8)PortMultiplier,
1517              NULL,
1518              0,
1519              &AtaCommandBlock,
1520              AtaStatusBlock,
1521              ATA_ATAPI_TIMEOUT,
1522              NULL
1523              );
1524
1525   if (EFI_ERROR (Status)) {
1526     REPORT_STATUS_CODE (
1527       EFI_ERROR_CODE | EFI_ERROR_MINOR,
1528       (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLED)
1529       );
1530     return EFI_DEVICE_ERROR;
1531   }
1532
1533   REPORT_STATUS_CODE (
1534     EFI_PROGRESS_CODE,
1535     (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_ENABLE)
1536     );
1537
1538   FisBaseAddr = (UINTN)AhciRegisters->AhciRFis + Port * sizeof (EFI_AHCI_RECEIVED_FIS);
1539
1540   Value = *(UINT32 *) (FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET);
1541
1542   if ((Value & EFI_AHCI_FIS_TYPE_MASK) == EFI_AHCI_FIS_REGISTER_D2H) {
1543     LBAMid  = ((UINT8 *)(UINTN)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET))[5];
1544     LBAHigh = ((UINT8 *)(UINTN)(FisBaseAddr + EFI_AHCI_D2H_FIS_OFFSET))[6];
1545
1546     if ((LBAMid == 0x4f) && (LBAHigh == 0xc2)) {
1547       //
1548       // The threshold exceeded condition is not detected by the device
1549       //
1550       DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is not detected\n"));
1551       REPORT_STATUS_CODE (
1552             EFI_PROGRESS_CODE,
1553             (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_UNDERTHRESHOLD)
1554             );
1555     } else if ((LBAMid == 0xf4) && (LBAHigh == 0x2c)) {
1556       //
1557       // The threshold exceeded condition is detected by the device
1558       //
1559       DEBUG ((EFI_D_INFO, "The S.M.A.R.T threshold exceeded condition is detected\n"));
1560       REPORT_STATUS_CODE (
1561            EFI_PROGRESS_CODE,
1562            (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_OVERTHRESHOLD)
1563            );
1564     }
1565   }
1566
1567   return EFI_SUCCESS;
1568 }
1569
1570 /**
1571   Enable SMART command of the disk if supported.
1572
1573   @param  PciIo               The PCI IO protocol instance.
1574   @param  AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
1575   @param  Port                The number of port.
1576   @param  PortMultiplier      The timeout value of stop.
1577   @param  IdentifyData        A pointer to data buffer which is used to contain IDENTIFY data.
1578   @param  AtaStatusBlock      A pointer to EFI_ATA_STATUS_BLOCK data structure.
1579
1580 **/
1581 VOID
1582 EFIAPI
1583 AhciAtaSmartSupport (
1584   IN EFI_PCI_IO_PROTOCOL           *PciIo,
1585   IN EFI_AHCI_REGISTERS            *AhciRegisters,
1586   IN UINT8                         Port,
1587   IN UINT8                         PortMultiplier,
1588   IN EFI_IDENTIFY_DATA             *IdentifyData,
1589   IN OUT EFI_ATA_STATUS_BLOCK      *AtaStatusBlock
1590   )
1591 {
1592   EFI_STATUS               Status;
1593   EFI_ATA_COMMAND_BLOCK    AtaCommandBlock;
1594
1595   //
1596   // Detect if the device supports S.M.A.R.T.
1597   //
1598   if ((IdentifyData->AtaData.command_set_supported_82 & 0x0001) != 0x0001) {
1599     //
1600     // S.M.A.R.T is not supported by the device
1601     //
1602     DEBUG ((EFI_D_INFO, "S.M.A.R.T feature is not supported at port [%d] PortMultiplier [%d]!\n",
1603             Port, PortMultiplier));
1604     REPORT_STATUS_CODE (
1605       EFI_ERROR_CODE | EFI_ERROR_MINOR,
1606       (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_NOTSUPPORTED)
1607       );
1608   } else {
1609     //
1610     // Check if the feature is enabled. If not, then enable S.M.A.R.T.
1611     //
1612     if ((IdentifyData->AtaData.command_set_feature_enb_85 & 0x0001) != 0x0001) {
1613
1614       REPORT_STATUS_CODE (
1615         EFI_PROGRESS_CODE,
1616         (EFI_IO_BUS_ATA_ATAPI | EFI_IOB_ATA_BUS_SMART_DISABLE)
1617         );
1618
1619       ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1620
1621       AtaCommandBlock.AtaCommand      = ATA_CMD_SMART;
1622       AtaCommandBlock.AtaFeatures     = ATA_SMART_ENABLE_OPERATION;
1623       AtaCommandBlock.AtaCylinderLow  = ATA_CONSTANT_4F;
1624       AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
1625
1626       //
1627       // Send S.M.A.R.T Enable command to device
1628       //
1629       Status = AhciNonDataTransfer (
1630                  PciIo,
1631                  AhciRegisters,
1632                  (UINT8)Port,
1633                  (UINT8)PortMultiplier,
1634                  NULL,
1635                  0,
1636                  &AtaCommandBlock,
1637                  AtaStatusBlock,
1638                  ATA_ATAPI_TIMEOUT,
1639                  NULL
1640                  );
1641
1642
1643       if (!EFI_ERROR (Status)) {
1644         //
1645         // Send S.M.A.R.T AutoSave command to device
1646         //
1647         ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1648
1649         AtaCommandBlock.AtaCommand      = ATA_CMD_SMART;
1650         AtaCommandBlock.AtaFeatures     = 0xD2;
1651         AtaCommandBlock.AtaSectorCount  = 0xF1;
1652         AtaCommandBlock.AtaCylinderLow  = ATA_CONSTANT_4F;
1653         AtaCommandBlock.AtaCylinderHigh = ATA_CONSTANT_C2;
1654
1655         Status = AhciNonDataTransfer (
1656                    PciIo,
1657                    AhciRegisters,
1658                    (UINT8)Port,
1659                    (UINT8)PortMultiplier,
1660                    NULL,
1661                    0,
1662                    &AtaCommandBlock,
1663                    AtaStatusBlock,
1664                    ATA_ATAPI_TIMEOUT,
1665                    NULL
1666                    );
1667
1668         if (!EFI_ERROR (Status)) {
1669           Status = AhciAtaSmartReturnStatusCheck (
1670                      PciIo,
1671                      AhciRegisters,
1672                      (UINT8)Port,
1673                      (UINT8)PortMultiplier,
1674                      AtaStatusBlock
1675                      );
1676         }
1677       }
1678     }
1679     DEBUG ((EFI_D_INFO, "Enabled S.M.A.R.T feature at port [%d] PortMultiplier [%d]!\n",
1680             Port, PortMultiplier));
1681   }
1682
1683   return ;
1684 }
1685
1686 /**
1687   Send Buffer cmd to specific device.
1688
1689   @param  PciIo               The PCI IO protocol instance.
1690   @param  AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
1691   @param  Port                The number of port.
1692   @param  PortMultiplier      The timeout value of stop.
1693   @param  Buffer              The data buffer to store IDENTIFY PACKET data.
1694
1695   @retval EFI_DEVICE_ERROR    The cmd abort with error occurs.
1696   @retval EFI_TIMEOUT         The operation is time out.
1697   @retval EFI_UNSUPPORTED     The device is not ready for executing.
1698   @retval EFI_SUCCESS         The cmd executes successfully.
1699
1700 **/
1701 EFI_STATUS
1702 EFIAPI
1703 AhciIdentify (
1704   IN EFI_PCI_IO_PROTOCOL      *PciIo,
1705   IN EFI_AHCI_REGISTERS       *AhciRegisters,
1706   IN UINT8                    Port,
1707   IN UINT8                    PortMultiplier,
1708   IN OUT EFI_IDENTIFY_DATA    *Buffer
1709   )
1710 {
1711   EFI_STATUS                   Status;
1712   EFI_ATA_COMMAND_BLOCK        AtaCommandBlock;
1713   EFI_ATA_STATUS_BLOCK         AtaStatusBlock;
1714
1715   if (PciIo == NULL || AhciRegisters == NULL || Buffer == NULL) {
1716     return EFI_INVALID_PARAMETER;
1717   }
1718
1719   ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1720   ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1721
1722   AtaCommandBlock.AtaCommand     = ATA_CMD_IDENTIFY_DRIVE;
1723   AtaCommandBlock.AtaSectorCount = 1;
1724
1725   Status = AhciPioTransfer (
1726              PciIo,
1727              AhciRegisters,
1728              Port,
1729              PortMultiplier,
1730              NULL,
1731              0,
1732              TRUE,
1733              &AtaCommandBlock,
1734              &AtaStatusBlock,
1735              Buffer,
1736              sizeof (EFI_IDENTIFY_DATA),
1737              ATA_ATAPI_TIMEOUT,
1738              NULL
1739              );
1740
1741   return Status;
1742 }
1743
1744 /**
1745   Send Buffer cmd to specific device.
1746
1747   @param  PciIo               The PCI IO protocol instance.
1748   @param  AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
1749   @param  Port                The number of port.
1750   @param  PortMultiplier      The timeout value of stop.
1751   @param  Buffer              The data buffer to store IDENTIFY PACKET data.
1752
1753   @retval EFI_DEVICE_ERROR    The cmd abort with error occurs.
1754   @retval EFI_TIMEOUT         The operation is time out.
1755   @retval EFI_UNSUPPORTED     The device is not ready for executing.
1756   @retval EFI_SUCCESS         The cmd executes successfully.
1757
1758 **/
1759 EFI_STATUS
1760 EFIAPI
1761 AhciIdentifyPacket (
1762   IN EFI_PCI_IO_PROTOCOL      *PciIo,
1763   IN EFI_AHCI_REGISTERS       *AhciRegisters,
1764   IN UINT8                    Port,
1765   IN UINT8                    PortMultiplier,
1766   IN OUT EFI_IDENTIFY_DATA    *Buffer
1767   )
1768 {
1769   EFI_STATUS                   Status;
1770   EFI_ATA_COMMAND_BLOCK        AtaCommandBlock;
1771   EFI_ATA_STATUS_BLOCK         AtaStatusBlock;
1772
1773   if (PciIo == NULL || AhciRegisters == NULL) {
1774     return EFI_INVALID_PARAMETER;
1775   }
1776
1777   ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1778   ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1779
1780   AtaCommandBlock.AtaCommand     = ATA_CMD_IDENTIFY_DEVICE;
1781   AtaCommandBlock.AtaSectorCount = 1;
1782
1783   Status = AhciPioTransfer (
1784              PciIo,
1785              AhciRegisters,
1786              Port,
1787              PortMultiplier,
1788              NULL,
1789              0,
1790              TRUE,
1791              &AtaCommandBlock,
1792              &AtaStatusBlock,
1793              Buffer,
1794              sizeof (EFI_IDENTIFY_DATA),
1795              ATA_ATAPI_TIMEOUT,
1796              NULL
1797              );
1798
1799   return Status;
1800 }
1801
1802 /**
1803   Send SET FEATURE cmd on specific device.
1804
1805   @param  PciIo               The PCI IO protocol instance.
1806   @param  AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
1807   @param  Port                The number of port.
1808   @param  PortMultiplier      The timeout value of stop.
1809   @param  Feature             The data to send Feature register.
1810   @param  FeatureSpecificData The specific data for SET FEATURE cmd.
1811
1812   @retval EFI_DEVICE_ERROR    The cmd abort with error occurs.
1813   @retval EFI_TIMEOUT         The operation is time out.
1814   @retval EFI_UNSUPPORTED     The device is not ready for executing.
1815   @retval EFI_SUCCESS         The cmd executes successfully.
1816
1817 **/
1818 EFI_STATUS
1819 EFIAPI
1820 AhciDeviceSetFeature (
1821   IN EFI_PCI_IO_PROTOCOL    *PciIo,
1822   IN EFI_AHCI_REGISTERS     *AhciRegisters,
1823   IN UINT8                  Port,
1824   IN UINT8                  PortMultiplier,
1825   IN UINT16                 Feature,
1826   IN UINT32                 FeatureSpecificData
1827   )
1828 {
1829   EFI_STATUS               Status;
1830   EFI_ATA_COMMAND_BLOCK    AtaCommandBlock;
1831   EFI_ATA_STATUS_BLOCK     AtaStatusBlock;
1832
1833   ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1834   ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1835
1836   AtaCommandBlock.AtaCommand      = ATA_CMD_SET_FEATURES;
1837   AtaCommandBlock.AtaFeatures     = (UINT8) Feature;
1838   AtaCommandBlock.AtaFeaturesExp  = (UINT8) (Feature >> 8);
1839   AtaCommandBlock.AtaSectorCount  = (UINT8) FeatureSpecificData;
1840   AtaCommandBlock.AtaSectorNumber = (UINT8) (FeatureSpecificData >> 8);
1841   AtaCommandBlock.AtaCylinderLow  = (UINT8) (FeatureSpecificData >> 16);
1842   AtaCommandBlock.AtaCylinderHigh = (UINT8) (FeatureSpecificData >> 24);
1843
1844   Status = AhciNonDataTransfer (
1845              PciIo,
1846              AhciRegisters,
1847              (UINT8)Port,
1848              (UINT8)PortMultiplier,
1849              NULL,
1850              0,
1851              &AtaCommandBlock,
1852              &AtaStatusBlock,
1853              ATA_ATAPI_TIMEOUT,
1854              NULL
1855              );
1856
1857   return Status;
1858 }
1859
1860 /**
1861   This function is used to send out ATAPI commands conforms to the Packet Command
1862   with PIO Protocol.
1863
1864   @param PciIo              The PCI IO protocol instance.
1865   @param AhciRegisters      The pointer to the EFI_AHCI_REGISTERS.
1866   @param Port               The number of port.
1867   @param PortMultiplier     The number of port multiplier.
1868   @param Packet             A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
1869
1870   @retval EFI_SUCCESS       send out the ATAPI packet command successfully
1871                             and device sends data successfully.
1872   @retval EFI_DEVICE_ERROR  the device failed to send data.
1873
1874 **/
1875 EFI_STATUS
1876 EFIAPI
1877 AhciPacketCommandExecute (
1878   IN  EFI_PCI_IO_PROTOCOL                           *PciIo,
1879   IN  EFI_AHCI_REGISTERS                            *AhciRegisters,
1880   IN  UINT8                                         Port,
1881   IN  UINT8                                         PortMultiplier,
1882   IN  EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET    *Packet
1883   )
1884 {
1885   EFI_STATUS                   Status;
1886   VOID                         *Buffer;
1887   UINT32                       Length;
1888   EFI_ATA_COMMAND_BLOCK        AtaCommandBlock;
1889   EFI_ATA_STATUS_BLOCK         AtaStatusBlock;
1890   BOOLEAN                      Read;
1891
1892   if (Packet == NULL || Packet->Cdb == NULL) {
1893     return EFI_INVALID_PARAMETER;
1894   }
1895
1896   ZeroMem (&AtaCommandBlock, sizeof (EFI_ATA_COMMAND_BLOCK));
1897   ZeroMem (&AtaStatusBlock, sizeof (EFI_ATA_STATUS_BLOCK));
1898   AtaCommandBlock.AtaCommand      = ATA_CMD_PACKET;
1899   //
1900   // No OVL; No DMA
1901   //
1902   AtaCommandBlock.AtaFeatures     = 0x00;
1903   //
1904   // set the transfersize to ATAPI_MAX_BYTE_COUNT to let the device
1905   // determine how many data should be transferred.
1906   //
1907   AtaCommandBlock.AtaCylinderLow  = (UINT8) (ATAPI_MAX_BYTE_COUNT & 0x00ff);
1908   AtaCommandBlock.AtaCylinderHigh = (UINT8) (ATAPI_MAX_BYTE_COUNT >> 8);
1909
1910   if (Packet->DataDirection == EFI_EXT_SCSI_DATA_DIRECTION_READ) {
1911     Buffer = Packet->InDataBuffer;
1912     Length = Packet->InTransferLength;
1913     Read = TRUE;
1914   } else {
1915     Buffer = Packet->OutDataBuffer;
1916     Length = Packet->OutTransferLength;
1917     Read = FALSE;
1918   }
1919
1920   if (Length == 0) {
1921     Status = AhciNonDataTransfer (
1922                PciIo,
1923                AhciRegisters,
1924                Port,
1925                PortMultiplier,
1926                Packet->Cdb,
1927                Packet->CdbLength,
1928                &AtaCommandBlock,
1929                &AtaStatusBlock,
1930                Packet->Timeout,
1931                NULL
1932                );
1933   } else {
1934     Status = AhciPioTransfer (
1935                PciIo,
1936                AhciRegisters,
1937                Port,
1938                PortMultiplier,
1939                Packet->Cdb,
1940                Packet->CdbLength,
1941                Read,
1942                &AtaCommandBlock,
1943                &AtaStatusBlock,
1944                Buffer,
1945                Length,
1946                Packet->Timeout,
1947                NULL
1948                );
1949   }
1950   return Status;
1951 }
1952
1953 /**
1954   Allocate transfer-related data struct which is used at AHCI mode.
1955
1956   @param  PciIo                 The PCI IO protocol instance.
1957   @param  AhciRegisters         The pointer to the EFI_AHCI_REGISTERS.
1958
1959 **/
1960 EFI_STATUS
1961 EFIAPI
1962 AhciCreateTransferDescriptor (
1963   IN     EFI_PCI_IO_PROTOCOL    *PciIo,
1964   IN OUT EFI_AHCI_REGISTERS     *AhciRegisters
1965   )
1966 {
1967   EFI_STATUS            Status;
1968   UINTN                 Bytes;
1969   VOID                  *Buffer;
1970
1971   UINT32                Capability;
1972   UINT32                PortImplementBitMap;
1973   UINT8                 MaxPortNumber;
1974   UINT8                 MaxCommandSlotNumber;
1975   BOOLEAN               Support64Bit;
1976   UINT64                MaxReceiveFisSize;
1977   UINT64                MaxCommandListSize;
1978   UINT64                MaxCommandTableSize;
1979   EFI_PHYSICAL_ADDRESS  AhciRFisPciAddr;
1980   EFI_PHYSICAL_ADDRESS  AhciCmdListPciAddr;
1981   EFI_PHYSICAL_ADDRESS  AhciCommandTablePciAddr;
1982
1983   Buffer = NULL;
1984   //
1985   // Collect AHCI controller information
1986   //
1987   Capability           = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
1988   //
1989   // Get the number of command slots per port supported by this HBA.
1990   //
1991   MaxCommandSlotNumber = (UINT8) (((Capability & 0x1F00) >> 8) + 1);
1992   Support64Bit         = (BOOLEAN) (((Capability & BIT31) != 0) ? TRUE : FALSE);
1993
1994   PortImplementBitMap  = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);
1995   //
1996   // Get the highest bit of implemented ports which decides how many bytes are allocated for recived FIS.
1997   //
1998   MaxPortNumber        = (UINT8)(UINTN)(HighBitSet32(PortImplementBitMap) + 1);
1999   if (MaxPortNumber == 0) {
2000     return EFI_DEVICE_ERROR;
2001   }
2002
2003   MaxReceiveFisSize    = MaxPortNumber * sizeof (EFI_AHCI_RECEIVED_FIS);
2004   Status = PciIo->AllocateBuffer (
2005                     PciIo,
2006                     AllocateAnyPages,
2007                     EfiBootServicesData,
2008                     EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),
2009                     &Buffer,
2010                     0
2011                     );
2012
2013   if (EFI_ERROR (Status)) {
2014     return EFI_OUT_OF_RESOURCES;
2015   }
2016
2017   ZeroMem (Buffer, (UINTN)MaxReceiveFisSize);
2018
2019   AhciRegisters->AhciRFis          = Buffer;
2020   AhciRegisters->MaxReceiveFisSize = MaxReceiveFisSize;
2021   Bytes  = (UINTN)MaxReceiveFisSize;
2022
2023   Status = PciIo->Map (
2024                     PciIo,
2025                     EfiPciIoOperationBusMasterCommonBuffer,
2026                     Buffer,
2027                     &Bytes,
2028                     &AhciRFisPciAddr,
2029                     &AhciRegisters->MapRFis
2030                     );
2031
2032   if (EFI_ERROR (Status) || (Bytes != MaxReceiveFisSize)) {
2033     //
2034     // Map error or unable to map the whole RFis buffer into a contiguous region.
2035     //
2036     Status = EFI_OUT_OF_RESOURCES;
2037     goto Error6;
2038   }
2039
2040   if ((!Support64Bit) && (AhciRFisPciAddr > 0x100000000ULL)) {
2041     //
2042     // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2043     //
2044     Status = EFI_DEVICE_ERROR;
2045     goto Error5;
2046   }
2047   AhciRegisters->AhciRFisPciAddr = (EFI_AHCI_RECEIVED_FIS *)(UINTN)AhciRFisPciAddr;
2048
2049   //
2050   // Allocate memory for command list
2051   // Note that the implemenation is a single task model which only use a command list for all ports.
2052   //
2053   Buffer = NULL;
2054   MaxCommandListSize = MaxCommandSlotNumber * sizeof (EFI_AHCI_COMMAND_LIST);
2055   Status = PciIo->AllocateBuffer (
2056                     PciIo,
2057                     AllocateAnyPages,
2058                     EfiBootServicesData,
2059                     EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),
2060                     &Buffer,
2061                     0
2062                     );
2063
2064   if (EFI_ERROR (Status)) {
2065     //
2066     // Free mapped resource.
2067     //
2068     Status = EFI_OUT_OF_RESOURCES;
2069     goto Error5;
2070   }
2071
2072   ZeroMem (Buffer, (UINTN)MaxCommandListSize);
2073
2074   AhciRegisters->AhciCmdList        = Buffer;
2075   AhciRegisters->MaxCommandListSize = MaxCommandListSize;
2076   Bytes  = (UINTN)MaxCommandListSize;
2077
2078   Status = PciIo->Map (
2079                     PciIo,
2080                     EfiPciIoOperationBusMasterCommonBuffer,
2081                     Buffer,
2082                     &Bytes,
2083                     &AhciCmdListPciAddr,
2084                     &AhciRegisters->MapCmdList
2085                     );
2086
2087   if (EFI_ERROR (Status) || (Bytes != MaxCommandListSize)) {
2088     //
2089     // Map error or unable to map the whole cmd list buffer into a contiguous region.
2090     //
2091     Status = EFI_OUT_OF_RESOURCES;
2092     goto Error4;
2093   }
2094
2095   if ((!Support64Bit) && (AhciCmdListPciAddr > 0x100000000ULL)) {
2096     //
2097     // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2098     //
2099     Status = EFI_DEVICE_ERROR;
2100     goto Error3;
2101   }
2102   AhciRegisters->AhciCmdListPciAddr = (EFI_AHCI_COMMAND_LIST *)(UINTN)AhciCmdListPciAddr;
2103
2104   //
2105   // Allocate memory for command table
2106   // According to AHCI 1.3 spec, a PRD table can contain maximum 65535 entries.
2107   //
2108   Buffer = NULL;
2109   MaxCommandTableSize = sizeof (EFI_AHCI_COMMAND_TABLE);
2110
2111   Status = PciIo->AllocateBuffer (
2112                     PciIo,
2113                     AllocateAnyPages,
2114                     EfiBootServicesData,
2115                     EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),
2116                     &Buffer,
2117                     0
2118                     );
2119
2120   if (EFI_ERROR (Status)) {
2121     //
2122     // Free mapped resource.
2123     //
2124     Status = EFI_OUT_OF_RESOURCES;
2125     goto Error3;
2126   }
2127
2128   ZeroMem (Buffer, (UINTN)MaxCommandTableSize);
2129
2130   AhciRegisters->AhciCommandTable    = Buffer;
2131   AhciRegisters->MaxCommandTableSize = MaxCommandTableSize;
2132   Bytes  = (UINTN)MaxCommandTableSize;
2133
2134   Status = PciIo->Map (
2135                     PciIo,
2136                     EfiPciIoOperationBusMasterCommonBuffer,
2137                     Buffer,
2138                     &Bytes,
2139                     &AhciCommandTablePciAddr,
2140                     &AhciRegisters->MapCommandTable
2141                     );
2142
2143   if (EFI_ERROR (Status) || (Bytes != MaxCommandTableSize)) {
2144     //
2145     // Map error or unable to map the whole cmd list buffer into a contiguous region.
2146     //
2147     Status = EFI_OUT_OF_RESOURCES;
2148     goto Error2;
2149   }
2150
2151   if ((!Support64Bit) && (AhciCommandTablePciAddr > 0x100000000ULL)) {
2152     //
2153     // The AHCI HBA doesn't support 64bit addressing, so should not get a >4G pci bus master address.
2154     //
2155     Status = EFI_DEVICE_ERROR;
2156     goto Error1;
2157   }
2158   AhciRegisters->AhciCommandTablePciAddr = (EFI_AHCI_COMMAND_TABLE *)(UINTN)AhciCommandTablePciAddr;
2159
2160   return EFI_SUCCESS;
2161   //
2162   // Map error or unable to map the whole CmdList buffer into a contiguous region.
2163   //
2164 Error1:
2165   PciIo->Unmap (
2166            PciIo,
2167            AhciRegisters->MapCommandTable
2168            );
2169 Error2:
2170   PciIo->FreeBuffer (
2171            PciIo,
2172            EFI_SIZE_TO_PAGES ((UINTN) MaxCommandTableSize),
2173            AhciRegisters->AhciCommandTable
2174            );
2175 Error3:
2176   PciIo->Unmap (
2177            PciIo,
2178            AhciRegisters->MapCmdList
2179            );
2180 Error4:
2181   PciIo->FreeBuffer (
2182            PciIo,
2183            EFI_SIZE_TO_PAGES ((UINTN) MaxCommandListSize),
2184            AhciRegisters->AhciCmdList
2185            );
2186 Error5:
2187   PciIo->Unmap (
2188            PciIo,
2189            AhciRegisters->MapRFis
2190            );
2191 Error6:
2192   PciIo->FreeBuffer (
2193            PciIo,
2194            EFI_SIZE_TO_PAGES ((UINTN) MaxReceiveFisSize),
2195            AhciRegisters->AhciRFis
2196            );
2197
2198   return Status;
2199 }
2200
2201 /**
2202   Initialize ATA host controller at AHCI mode.
2203
2204   The function is designed to initialize ATA host controller.
2205
2206   @param[in]  Instance          A pointer to the ATA_ATAPI_PASS_THRU_INSTANCE instance.
2207
2208 **/
2209 EFI_STATUS
2210 EFIAPI
2211 AhciModeInitialization (
2212   IN  ATA_ATAPI_PASS_THRU_INSTANCE    *Instance
2213   )
2214 {
2215   EFI_STATUS                       Status;
2216   EFI_PCI_IO_PROTOCOL              *PciIo;
2217   EFI_IDE_CONTROLLER_INIT_PROTOCOL *IdeInit;
2218   UINT32                           Capability;
2219   UINT8                            MaxPortNumber;
2220   UINT32                           PortImplementBitMap;
2221
2222   EFI_AHCI_REGISTERS               *AhciRegisters;
2223
2224   UINT8                            Port;
2225   DATA_64                          Data64;
2226   UINT32                           Offset;
2227   UINT32                           Data;
2228   EFI_IDENTIFY_DATA                Buffer;
2229   EFI_ATA_DEVICE_TYPE              DeviceType;
2230   EFI_ATA_COLLECTIVE_MODE          *SupportedModes;
2231   EFI_ATA_TRANSFER_MODE            TransferMode;
2232   UINT32                           PhyDetectDelay;
2233
2234   if (Instance == NULL) {
2235     return EFI_INVALID_PARAMETER;
2236   }
2237
2238   PciIo   = Instance->PciIo;
2239   IdeInit = Instance->IdeControllerInit;
2240
2241   Status = AhciReset (PciIo, EFI_AHCI_BUS_RESET_TIMEOUT);
2242
2243   if (EFI_ERROR (Status)) {
2244     return EFI_DEVICE_ERROR;
2245   }
2246
2247   //
2248   // Enable AE before accessing any AHCI registers
2249   //
2250   AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE);
2251
2252   //
2253   // Collect AHCI controller information
2254   //
2255   Capability           = AhciReadReg(PciIo, EFI_AHCI_CAPABILITY_OFFSET);
2256
2257   //
2258   // Get the number of command slots per port supported by this HBA.
2259   //
2260   MaxPortNumber        = (UINT8) ((Capability & 0x1F) + 1);
2261
2262   //
2263   // Get the bit map of those ports exposed by this HBA.
2264   // It indicates which ports that the HBA supports are available for software to use.
2265   //
2266   PortImplementBitMap  = AhciReadReg(PciIo, EFI_AHCI_PI_OFFSET);
2267
2268   AhciRegisters = &Instance->AhciRegisters;
2269   Status = AhciCreateTransferDescriptor (PciIo, AhciRegisters);
2270
2271   if (EFI_ERROR (Status)) {
2272     return EFI_OUT_OF_RESOURCES;
2273   }
2274
2275   for (Port = 0; Port < EFI_AHCI_MAX_PORTS; Port ++) {
2276     if ((PortImplementBitMap & (BIT0 << Port)) != 0) {
2277       //
2278       // According to AHCI spec, MaxPortNumber should be equal or greater than the number of implemented ports.
2279       //
2280       if ((MaxPortNumber--) == 0) {
2281         //
2282         // Should never be here.
2283         //
2284         ASSERT (FALSE);
2285         return EFI_SUCCESS;
2286       }
2287
2288       IdeInit->NotifyPhase (IdeInit, EfiIdeBeforeChannelEnumeration, Port);
2289
2290       //
2291       // Initialize FIS Base Address Register and Command List Base Address Register for use.
2292       //
2293       Data64.Uint64 = (UINTN) (AhciRegisters->AhciRFisPciAddr) + sizeof (EFI_AHCI_RECEIVED_FIS) * Port;
2294       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FB;
2295       AhciWriteReg (PciIo, Offset, Data64.Uint32.Lower32);
2296       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_FBU;
2297       AhciWriteReg (PciIo, Offset, Data64.Uint32.Upper32);
2298
2299       Data64.Uint64 = (UINTN) (AhciRegisters->AhciCmdListPciAddr);
2300       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLB;
2301       AhciWriteReg (PciIo, Offset, Data64.Uint32.Lower32);
2302       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CLBU;
2303       AhciWriteReg (PciIo, Offset, Data64.Uint32.Upper32);
2304
2305       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
2306       Data = AhciReadReg (PciIo, Offset);
2307       if ((Data & EFI_AHCI_PORT_CMD_CPD) != 0) {
2308         AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_POD);
2309       }
2310
2311       if ((Capability & EFI_AHCI_CAP_SSS) != 0) {
2312         AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_SUD);
2313       }
2314
2315       //
2316       // Disable aggressive power management.
2317       //
2318       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SCTL;
2319       AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_SCTL_IPM_INIT);
2320       //
2321       // Disable the reporting of the corresponding interrupt to system software.
2322       //
2323       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_IE;
2324       AhciAndReg (PciIo, Offset, 0);
2325
2326       //
2327       // Now inform the IDE Controller Init Module.
2328       //
2329       IdeInit->NotifyPhase (IdeInit, EfiIdeBusBeforeDevicePresenceDetection, Port);
2330
2331       //
2332       // Enable FIS Receive DMA engine for the first D2H FIS.
2333       //
2334       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
2335       AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE);
2336       Status = AhciWaitMmioSet (
2337                  PciIo,
2338                  Offset,
2339                  EFI_AHCI_PORT_CMD_FR,
2340                  EFI_AHCI_PORT_CMD_FR,
2341                  EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT
2342                  );
2343       if (EFI_ERROR (Status)) {
2344         continue;
2345       }
2346
2347       //
2348       // Wait no longer than 10 ms to wait the Phy to detect the presence of a device.
2349       // It's the requirment from SATA1.0a spec section 5.2.
2350       //
2351       PhyDetectDelay = EFI_AHCI_BUS_PHY_DETECT_TIMEOUT;
2352       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SSTS;
2353       do {
2354         Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_SSTS_DET_MASK;
2355         if ((Data == EFI_AHCI_PORT_SSTS_DET_PCE) || (Data == EFI_AHCI_PORT_SSTS_DET)) {
2356           break;
2357         }
2358
2359         MicroSecondDelay (1000);
2360         PhyDetectDelay--;
2361       } while (PhyDetectDelay > 0);
2362
2363       if (PhyDetectDelay == 0) {
2364         //
2365         // No device detected at this port.
2366         // Clear PxCMD.SUD for those ports at which there are no device present.
2367         //
2368         Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_CMD;
2369         AhciAndReg (PciIo, Offset, (UINT32) ~(EFI_AHCI_PORT_CMD_SUD));
2370         continue;
2371       }
2372
2373       //
2374       // According to SATA1.0a spec section 5.2, we need to wait for PxTFD.BSY and PxTFD.DRQ
2375       // and PxTFD.ERR to be zero. The maximum wait time is 16s which is defined at ATA spec.
2376       //
2377       PhyDetectDelay = 16 * 1000;
2378       do {
2379         Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SERR;
2380         if (AhciReadReg(PciIo, Offset) != 0) {
2381           AhciWriteReg (PciIo, Offset, AhciReadReg(PciIo, Offset));
2382         }
2383         Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_TFD;
2384
2385         Data = AhciReadReg (PciIo, Offset) & EFI_AHCI_PORT_TFD_MASK;
2386         if (Data == 0) {
2387           break;
2388         }
2389
2390         MicroSecondDelay (1000);
2391         PhyDetectDelay--;
2392       } while (PhyDetectDelay > 0);
2393
2394       if (PhyDetectDelay == 0) {
2395         continue;
2396       }
2397
2398       //
2399       // When the first D2H register FIS is received, the content of PxSIG register is updated.
2400       //
2401       Offset = EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EFI_AHCI_PORT_SIG;
2402       Status = AhciWaitMmioSet (
2403                  PciIo,
2404                  Offset,
2405                  0x0000FFFF,
2406                  0x00000101,
2407                  EFI_TIMER_PERIOD_SECONDS(16)
2408                  );
2409       if (EFI_ERROR (Status)) {
2410         continue;
2411       }
2412
2413       Data = AhciReadReg (PciIo, Offset);
2414       if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATAPI_DEVICE_SIG) {
2415         Status = AhciIdentifyPacket (PciIo, AhciRegisters, Port, 0, &Buffer);
2416
2417         if (EFI_ERROR (Status)) {
2418           continue;
2419         }
2420
2421         DeviceType = EfiIdeCdrom;
2422       } else if ((Data & EFI_AHCI_ATAPI_SIG_MASK) == EFI_AHCI_ATA_DEVICE_SIG) {
2423         Status = AhciIdentify (PciIo, AhciRegisters, Port, 0, &Buffer);
2424
2425         if (EFI_ERROR (Status)) {
2426           REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_EC_NOT_DETECTED));
2427           continue;
2428         }
2429
2430         DeviceType = EfiIdeHarddisk;
2431       } else {
2432         continue;
2433       }
2434       DEBUG ((EFI_D_INFO, "port [%d] port mulitplier [%d] has a [%a]\n",
2435               Port, 0, DeviceType == EfiIdeCdrom ? "cdrom" : "harddisk"));
2436
2437       //
2438       // If the device is a hard disk, then try to enable S.M.A.R.T feature
2439       //
2440       if ((DeviceType == EfiIdeHarddisk) && PcdGetBool (PcdAtaSmartEnable)) {
2441         AhciAtaSmartSupport (
2442           PciIo,
2443           AhciRegisters,
2444           Port,
2445           0,
2446           &Buffer,
2447           NULL
2448           );
2449       }
2450
2451       //
2452       // Submit identify data to IDE controller init driver
2453       //
2454       IdeInit->SubmitData (IdeInit, Port, 0, &Buffer);
2455
2456       //
2457       // Now start to config ide device parameter and transfer mode.
2458       //
2459       Status = IdeInit->CalculateMode (
2460                           IdeInit,
2461                           Port,
2462                           0,
2463                           &SupportedModes
2464                           );
2465       if (EFI_ERROR (Status)) {
2466         DEBUG ((EFI_D_ERROR, "Calculate Mode Fail, Status = %r\n", Status));
2467         continue;
2468       }
2469
2470       //
2471       // Set best supported PIO mode on this IDE device
2472       //
2473       if (SupportedModes->PioMode.Mode <= EfiAtaPioMode2) {
2474         TransferMode.ModeCategory = EFI_ATA_MODE_DEFAULT_PIO;
2475       } else {
2476         TransferMode.ModeCategory = EFI_ATA_MODE_FLOW_PIO;
2477       }
2478
2479       TransferMode.ModeNumber = (UINT8) (SupportedModes->PioMode.Mode);
2480
2481       //
2482       // Set supported DMA mode on this IDE device. Note that UDMA & MDMA cann't
2483       // be set together. Only one DMA mode can be set to a device. If setting
2484       // DMA mode operation fails, we can continue moving on because we only use
2485       // PIO mode at boot time. DMA modes are used by certain kind of OS booting
2486       //
2487       if (SupportedModes->UdmaMode.Valid) {
2488         TransferMode.ModeCategory = EFI_ATA_MODE_UDMA;
2489         TransferMode.ModeNumber = (UINT8) (SupportedModes->UdmaMode.Mode);
2490       } else if (SupportedModes->MultiWordDmaMode.Valid) {
2491         TransferMode.ModeCategory = EFI_ATA_MODE_MDMA;
2492         TransferMode.ModeNumber = (UINT8) SupportedModes->MultiWordDmaMode.Mode;
2493       }
2494
2495       Status = AhciDeviceSetFeature (PciIo, AhciRegisters, Port, 0, 0x03, (UINT32)(*(UINT8 *)&TransferMode));
2496       if (EFI_ERROR (Status)) {
2497         DEBUG ((EFI_D_ERROR, "Set transfer Mode Fail, Status = %r\n", Status));
2498         continue;
2499       }
2500
2501       //
2502       // Found a ATA or ATAPI device, add it into the device list.
2503       //
2504       CreateNewDeviceInfo (Instance, Port, 0, DeviceType, &Buffer);
2505       if (DeviceType == EfiIdeHarddisk) {
2506         REPORT_STATUS_CODE (EFI_PROGRESS_CODE, (EFI_PERIPHERAL_FIXED_MEDIA | EFI_P_PC_ENABLE));
2507       }
2508     }
2509   }
2510
2511   return EFI_SUCCESS;
2512 }
2513