MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h

   1 /** @file
   2   Header file for AHCI mode of ATA host controller.
   3
   4   Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14 #ifndef __ATA_HC_AHCI_MODE_H__
  15 #define __ATA_HC_AHCI_MODE_H__
  16
  17 #define EFI_AHCI_BAR_INDEX                     0x05
  18
  19 #define EFI_AHCI_CAPABILITY_OFFSET             0x0000
  20 #define   EFI_AHCI_CAP_SSS                     BIT27
  21 #define   EFI_AHCI_CAP_S64A                    BIT31
  22 #define EFI_AHCI_GHC_OFFSET                    0x0004
  23 #define   EFI_AHCI_GHC_RESET                   BIT0
  24 #define   EFI_AHCI_GHC_IE                      BIT1
  25 #define   EFI_AHCI_GHC_ENABLE                  BIT31
  26 #define EFI_AHCI_IS_OFFSET                     0x0008
  27 #define EFI_AHCI_PI_OFFSET                     0x000C
  28
  29 typedef struct {
  30   UINT32  Lower32;
  31   UINT32  Upper32;
  32 } DATA_32;
  33
  34 typedef union {
  35   DATA_32   Uint32;
  36   UINT64    Uint64;
  37 } DATA_64;
  38
  39 //
  40 // Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.
  41 //
  42 #define  EFI_AHCI_BUS_PHY_DETECT_TIMEOUT       10
  43 //
  44 // Refer SATA1.0a spec, the FIS enable time should be less than 500ms.
  45 //
  46 #define  EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT    EFI_TIMER_PERIOD_MILLISECONDS(500)
  47 //
  48 // Refer SATA1.0a spec, the bus reset time should be less than 1s.
  49 //
  50 #define  EFI_AHCI_BUS_RESET_TIMEOUT            EFI_TIMER_PERIOD_SECONDS(1)
  51
  52 #define  EFI_AHCI_ATAPI_DEVICE_SIG             0xEB140000
  53 #define  EFI_AHCI_ATA_DEVICE_SIG               0x00000000
  54 #define  EFI_AHCI_PORT_MULTIPLIER_SIG          0x96690000
  55 #define  EFI_AHCI_ATAPI_SIG_MASK               0xFFFF0000
  56
  57 //
  58 // Each PRDT entry can point to a memory block up to 4M byte
  59 //
  60 #define EFI_AHCI_MAX_DATA_PER_PRDT             0x400000
  61
  62 #define EFI_AHCI_FIS_REGISTER_H2D              0x27      //Register FIS - Host to Device
  63 #define   EFI_AHCI_FIS_REGISTER_H2D_LENGTH     20
  64 #define EFI_AHCI_FIS_REGISTER_D2H              0x34      //Register FIS - Device to Host
  65 #define   EFI_AHCI_FIS_REGISTER_D2H_LENGTH     20
  66 #define EFI_AHCI_FIS_DMA_ACTIVATE              0x39      //DMA Activate FIS - Device to Host
  67 #define   EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH     4
  68 #define EFI_AHCI_FIS_DMA_SETUP                 0x41      //DMA Setup FIS - Bi-directional
  69 #define   EFI_AHCI_FIS_DMA_SETUP_LENGTH        28
  70 #define EFI_AHCI_FIS_DATA                      0x46      //Data FIS - Bi-directional
  71 #define EFI_AHCI_FIS_BIST                      0x58      //BIST Activate FIS - Bi-directional
  72 #define   EFI_AHCI_FIS_BIST_LENGTH             12
  73 #define EFI_AHCI_FIS_PIO_SETUP                 0x5F      //PIO Setup FIS - Device to Host
  74 #define   EFI_AHCI_FIS_PIO_SETUP_LENGTH        20
  75 #define EFI_AHCI_FIS_SET_DEVICE                0xA1      //Set Device Bits FIS - Device to Host
  76 #define   EFI_AHCI_FIS_SET_DEVICE_LENGTH       8
  77
  78 #define EFI_AHCI_D2H_FIS_OFFSET                0x40
  79 #define EFI_AHCI_DMA_FIS_OFFSET                0x00
  80 #define EFI_AHCI_PIO_FIS_OFFSET                0x20
  81 #define EFI_AHCI_SDB_FIS_OFFSET                0x58
  82 #define EFI_AHCI_FIS_TYPE_MASK                 0xFF
  83 #define EFI_AHCI_U_FIS_OFFSET                  0x60
  84
  85 //
  86 // Port register
  87 //
  88 #define EFI_AHCI_PORT_START                    0x0100
  89 #define EFI_AHCI_PORT_REG_WIDTH                0x0080
  90 #define EFI_AHCI_PORT_CLB                      0x0000
  91 #define EFI_AHCI_PORT_CLBU                     0x0004
  92 #define EFI_AHCI_PORT_FB                       0x0008
  93 #define EFI_AHCI_PORT_FBU                      0x000C
  94 #define EFI_AHCI_PORT_IS                       0x0010
  95 #define   EFI_AHCI_PORT_IS_DHRS                BIT0
  96 #define   EFI_AHCI_PORT_IS_PSS                 BIT1
  97 #define   EFI_AHCI_PORT_IS_SSS                 BIT2
  98 #define   EFI_AHCI_PORT_IS_SDBS                BIT3
  99 #define   EFI_AHCI_PORT_IS_UFS                 BIT4
 100 #define   EFI_AHCI_PORT_IS_DPS                 BIT5
 101 #define   EFI_AHCI_PORT_IS_PCS                 BIT6
 102 #define   EFI_AHCI_PORT_IS_DIS                 BIT7
 103 #define   EFI_AHCI_PORT_IS_PRCS                BIT22
 104 #define   EFI_AHCI_PORT_IS_IPMS                BIT23
 105 #define   EFI_AHCI_PORT_IS_OFS                 BIT24
 106 #define   EFI_AHCI_PORT_IS_INFS                BIT26
 107 #define   EFI_AHCI_PORT_IS_IFS                 BIT27
 108 #define   EFI_AHCI_PORT_IS_HBDS                BIT28
 109 #define   EFI_AHCI_PORT_IS_HBFS                BIT29
 110 #define   EFI_AHCI_PORT_IS_TFES                BIT30
 111 #define   EFI_AHCI_PORT_IS_CPDS                BIT31
 112 #define   EFI_AHCI_PORT_IS_CLEAR               0xFFFFFFFF
 113 #define   EFI_AHCI_PORT_IS_FIS_CLEAR           0x0000000F
 114
 115 #define EFI_AHCI_PORT_IE                       0x0014
 116 #define EFI_AHCI_PORT_CMD                      0x0018
 117 #define   EFI_AHCI_PORT_CMD_ST_MASK            0xFFFFFFFE
 118 #define   EFI_AHCI_PORT_CMD_ST                 BIT0
 119 #define   EFI_AHCI_PORT_CMD_SUD                BIT1
 120 #define   EFI_AHCI_PORT_CMD_POD                BIT2
 121 #define   EFI_AHCI_PORT_CMD_CLO                BIT3
 122 #define   EFI_AHCI_PORT_CMD_CR                 BIT15
 123 #define   EFI_AHCI_PORT_CMD_FRE                BIT4
 124 #define   EFI_AHCI_PORT_CMD_FR                 BIT14
 125 #define   EFI_AHCI_PORT_CMD_MASK               ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)
 126 #define   EFI_AHCI_PORT_CMD_PMA                BIT17
 127 #define   EFI_AHCI_PORT_CMD_HPCP               BIT18
 128 #define   EFI_AHCI_PORT_CMD_MPSP               BIT19
 129 #define   EFI_AHCI_PORT_CMD_CPD                BIT20
 130 #define   EFI_AHCI_PORT_CMD_ESP                BIT21
 131 #define   EFI_AHCI_PORT_CMD_ATAPI              BIT24
 132 #define   EFI_AHCI_PORT_CMD_DLAE               BIT25
 133 #define   EFI_AHCI_PORT_CMD_ALPE               BIT26
 134 #define   EFI_AHCI_PORT_CMD_ASP                BIT27
 135 #define   EFI_AHCI_PORT_CMD_ICC_MASK           (BIT28 | BIT29 | BIT30 | BIT31)
 136 #define   EFI_AHCI_PORT_CMD_ACTIVE             (1 << 28 )
 137 #define EFI_AHCI_PORT_TFD                      0x0020
 138 #define   EFI_AHCI_PORT_TFD_MASK               (BIT7 | BIT3 | BIT0)
 139 #define   EFI_AHCI_PORT_TFD_BSY                BIT7
 140 #define   EFI_AHCI_PORT_TFD_DRQ                BIT3
 141 #define   EFI_AHCI_PORT_TFD_ERR                BIT0
 142 #define   EFI_AHCI_PORT_TFD_ERR_MASK           0x00FF00
 143 #define EFI_AHCI_PORT_SIG                      0x0024
 144 #define EFI_AHCI_PORT_SSTS                     0x0028
 145 #define   EFI_AHCI_PORT_SSTS_DET_MASK          0x000F
 146 #define   EFI_AHCI_PORT_SSTS_DET               0x0001
 147 #define   EFI_AHCI_PORT_SSTS_DET_PCE           0x0003
 148 #define   EFI_AHCI_PORT_SSTS_SPD_MASK          0x00F0
 149 #define EFI_AHCI_PORT_SCTL                     0x002C
 150 #define   EFI_AHCI_PORT_SCTL_DET_MASK          0x000F
 151 #define   EFI_AHCI_PORT_SCTL_MASK              (~EFI_AHCI_PORT_SCTL_DET_MASK)
 152 #define   EFI_AHCI_PORT_SCTL_DET_INIT          0x0001
 153 #define   EFI_AHCI_PORT_SCTL_DET_PHYCOMM       0x0003
 154 #define   EFI_AHCI_PORT_SCTL_SPD_MASK          0x00F0
 155 #define   EFI_AHCI_PORT_SCTL_IPM_MASK          0x0F00
 156 #define   EFI_AHCI_PORT_SCTL_IPM_INIT          0x0300
 157 #define   EFI_AHCI_PORT_SCTL_IPM_PSD           0x0100
 158 #define   EFI_AHCI_PORT_SCTL_IPM_SSD           0x0200
 159 #define EFI_AHCI_PORT_SERR                     0x0030
 160 #define   EFI_AHCI_PORT_SERR_RDIE              BIT0
 161 #define   EFI_AHCI_PORT_SERR_RCE               BIT1
 162 #define   EFI_AHCI_PORT_SERR_TDIE              BIT8
 163 #define   EFI_AHCI_PORT_SERR_PCDIE             BIT9
 164 #define   EFI_AHCI_PORT_SERR_PE                BIT10
 165 #define   EFI_AHCI_PORT_SERR_IE                BIT11
 166 #define   EFI_AHCI_PORT_SERR_PRC               BIT16
 167 #define   EFI_AHCI_PORT_SERR_PIE               BIT17
 168 #define   EFI_AHCI_PORT_SERR_CW                BIT18
 169 #define   EFI_AHCI_PORT_SERR_BDE               BIT19
 170 #define   EFI_AHCI_PORT_SERR_DE                BIT20
 171 #define   EFI_AHCI_PORT_SERR_CRCE              BIT21
 172 #define   EFI_AHCI_PORT_SERR_HE                BIT22
 173 #define   EFI_AHCI_PORT_SERR_LSE               BIT23
 174 #define   EFI_AHCI_PORT_SERR_TSTE              BIT24
 175 #define   EFI_AHCI_PORT_SERR_UFT               BIT25
 176 #define   EFI_AHCI_PORT_SERR_EX                BIT26
 177 #define   EFI_AHCI_PORT_ERR_CLEAR              0xFFFFFFFF
 178 #define EFI_AHCI_PORT_SACT                     0x0034
 179 #define EFI_AHCI_PORT_CI                       0x0038
 180 #define EFI_AHCI_PORT_SNTF                     0x003C
 181
 182
 183 #pragma pack(1)
 184 //
 185 // Command List structure includes total 32 entries.
 186 // The entry data structure is listed at the following.
 187 //
 188 typedef struct {
 189   UINT32   AhciCmdCfl:5;      //Command FIS Length
 190   UINT32   AhciCmdA:1;        //ATAPI
 191   UINT32   AhciCmdW:1;        //Write
 192   UINT32   AhciCmdP:1;        //Prefetchable
 193   UINT32   AhciCmdR:1;        //Reset
 194   UINT32   AhciCmdB:1;        //BIST
 195   UINT32   AhciCmdC:1;        //Clear Busy upon R_OK
 196   UINT32   AhciCmdRsvd:1;
 197   UINT32   AhciCmdPmp:4;      //Port Multiplier Port
 198   UINT32   AhciCmdPrdtl:16;   //Physical Region Descriptor Table Length
 199   UINT32   AhciCmdPrdbc;      //Physical Region Descriptor Byte Count
 200   UINT32   AhciCmdCtba;       //Command Table Descriptor Base Address
 201   UINT32   AhciCmdCtbau;      //Command Table Descriptor Base Address Upper 32-BITs
 202   UINT32   AhciCmdRsvd1[4];
 203 } EFI_AHCI_COMMAND_LIST;
 204
 205 //
 206 // This is a software constructed FIS.
 207 // For data transfer operations, this is the H2D Register FIS format as
 208 // specified in the Serial ATA Revision 2.6 specification.
 209 //
 210 typedef struct {
 211   UINT8    AhciCFisType;
 212   UINT8    AhciCFisPmNum:4;
 213   UINT8    AhciCFisRsvd:1;
 214   UINT8    AhciCFisRsvd1:1;
 215   UINT8    AhciCFisRsvd2:1;
 216   UINT8    AhciCFisCmdInd:1;
 217   UINT8    AhciCFisCmd;
 218   UINT8    AhciCFisFeature;
 219   UINT8    AhciCFisSecNum;
 220   UINT8    AhciCFisClyLow;
 221   UINT8    AhciCFisClyHigh;
 222   UINT8    AhciCFisDevHead;
 223   UINT8    AhciCFisSecNumExp;
 224   UINT8    AhciCFisClyLowExp;
 225   UINT8    AhciCFisClyHighExp;
 226   UINT8    AhciCFisFeatureExp;
 227   UINT8    AhciCFisSecCount;
 228   UINT8    AhciCFisSecCountExp;
 229   UINT8    AhciCFisRsvd3;
 230   UINT8    AhciCFisControl;
 231   UINT8    AhciCFisRsvd4[4];
 232   UINT8    AhciCFisRsvd5[44];
 233 } EFI_AHCI_COMMAND_FIS;
 234
 235 //
 236 // ACMD: ATAPI command (12 or 16 bytes)
 237 //
 238 typedef struct {
 239   UINT8    AtapiCmd[0x10];
 240 } EFI_AHCI_ATAPI_COMMAND;
 241
 242 //
 243 // Physical Region Descriptor Table includes up to 65535 entries
 244 // The entry data structure is listed at the following.
 245 // the actual entry number comes from the PRDTL field in the command
 246 // list entry for this command slot.
 247 //
 248 typedef struct {
 249   UINT32   AhciPrdtDba;       //Data Base Address
 250   UINT32   AhciPrdtDbau;      //Data Base Address Upper 32-BITs
 251   UINT32   AhciPrdtRsvd;
 252   UINT32   AhciPrdtDbc:22;    //Data Byte Count
 253   UINT32   AhciPrdtRsvd1:9;
 254   UINT32   AhciPrdtIoc:1;     //Interrupt on Completion
 255 } EFI_AHCI_COMMAND_PRDT;
 256
 257 //
 258 // Command table data strucute which is pointed to by the entry in the command list
 259 //
 260 typedef struct {
 261   EFI_AHCI_COMMAND_FIS      CommandFis;       // A software constructed FIS.
 262   EFI_AHCI_ATAPI_COMMAND    AtapiCmd;         // 12 or 16 bytes ATAPI cmd.
 263   UINT8                     Reserved[0x30];
 264   EFI_AHCI_COMMAND_PRDT     PrdtTable[65535];     // The scatter/gather list for data transfer
 265 } EFI_AHCI_COMMAND_TABLE;
 266
 267 //
 268 // Received FIS structure
 269 //
 270 typedef struct {
 271   UINT8    AhciDmaSetupFis[0x1C];         // Dma Setup Fis: offset 0x00
 272   UINT8    AhciDmaSetupFisRsvd[0x04];
 273   UINT8    AhciPioSetupFis[0x14];         // Pio Setup Fis: offset 0x20
 274   UINT8    AhciPioSetupFisRsvd[0x0C];
 275   UINT8    AhciD2HRegisterFis[0x14];      // D2H Register Fis: offset 0x40
 276   UINT8    AhciD2HRegisterFisRsvd[0x04];
 277   UINT64   AhciSetDeviceBitsFis;          // Set Device Bits Fix: offset 0x58
 278   UINT8    AhciUnknownFis[0x40];          // Unkonwn Fis: offset 0x60
 279   UINT8    AhciUnknownFisRsvd[0x60];
 280 } EFI_AHCI_RECEIVED_FIS;
 281
 282 #pragma pack()
 283
 284 typedef struct {
 285   EFI_AHCI_RECEIVED_FIS     *AhciRFis;
 286   EFI_AHCI_COMMAND_LIST     *AhciCmdList;
 287   EFI_AHCI_COMMAND_TABLE    *AhciCommandTable;
 288   EFI_AHCI_RECEIVED_FIS     *AhciRFisPciAddr;
 289   EFI_AHCI_COMMAND_LIST     *AhciCmdListPciAddr;
 290   EFI_AHCI_COMMAND_TABLE    *AhciCommandTablePciAddr;
 291   UINT64                    MaxCommandListSize;
 292   UINT64                    MaxCommandTableSize;
 293   UINT64                    MaxReceiveFisSize;
 294   VOID                      *MapRFis;
 295   VOID                      *MapCmdList;
 296   VOID                      *MapCommandTable;
 297 } EFI_AHCI_REGISTERS;
 298
 299 /**
 300   This function is used to send out ATAPI commands conforms to the Packet Command
 301   with PIO Protocol.
 302
 303   @param PciIo              The PCI IO protocol instance.
 304   @param AhciRegisters      The pointer to the EFI_AHCI_REGISTERS.
 305   @param Port               The number of port.
 306   @param PortMultiplier     The number of port multiplier.
 307   @param Packet             A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
 308
 309   @retval EFI_SUCCESS       send out the ATAPI packet command successfully
 310                             and device sends data successfully.
 311   @retval EFI_DEVICE_ERROR  the device failed to send data.
 312
 313 **/
 314 EFI_STATUS
 315 EFIAPI
 316 AhciPacketCommandExecute (
 317   IN  EFI_PCI_IO_PROTOCOL                           *PciIo,
 318   IN  EFI_AHCI_REGISTERS                            *AhciRegisters,
 319   IN  UINT8                                         Port,
 320   IN  UINT8                                         PortMultiplier,
 321   IN  EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET    *Packet
 322   );
 323
 324 /**
 325   Start command for give slot on specific port.
 326
 327   @param  PciIo              The PCI IO protocol instance.
 328   @param  Port               The number of port.
 329   @param  CommandSlot        The number of CommandSlot.
 330   @param  Timeout            The timeout value of start.
 331
 332   @retval EFI_DEVICE_ERROR   The command start unsuccessfully.
 333   @retval EFI_TIMEOUT        The operation is time out.
 334   @retval EFI_SUCCESS        The command start successfully.
 335
 336 **/
 337 EFI_STATUS
 338 EFIAPI
 339 AhciStartCommand (
 340   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 341   IN  UINT8                     Port,
 342   IN  UINT8                     CommandSlot,
 343   IN  UINT64                    Timeout
 344   );
 345
 346 /**
 347   Stop command running for giving port
 348
 349   @param  PciIo              The PCI IO protocol instance.
 350   @param  Port               The number of port.
 351   @param  Timeout            The timeout value of stop.
 352
 353   @retval EFI_DEVICE_ERROR   The command stop unsuccessfully.
 354   @retval EFI_TIMEOUT        The operation is time out.
 355   @retval EFI_SUCCESS        The command stop successfully.
 356
 357 **/
 358 EFI_STATUS
 359 EFIAPI
 360 AhciStopCommand (
 361   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 362   IN  UINT8                     Port,
 363   IN  UINT64                    Timeout
 364   );
 365
 366 #endif
 367