2 Header file for AHCI mode of ATA host controller.
4 Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #ifndef __ATA_HC_AHCI_MODE_H__
15 #define __ATA_HC_AHCI_MODE_H__
17 #define EFI_AHCI_BAR_INDEX 0x05
19 #define EFI_AHCI_CAPABILITY_OFFSET 0x0000
20 #define EFI_AHCI_CAP_SAM BIT18
21 #define EFI_AHCI_CAP_SSS BIT27
22 #define EFI_AHCI_CAP_S64A BIT31
23 #define EFI_AHCI_GHC_OFFSET 0x0004
24 #define EFI_AHCI_GHC_RESET BIT0
25 #define EFI_AHCI_GHC_IE BIT1
26 #define EFI_AHCI_GHC_ENABLE BIT31
27 #define EFI_AHCI_IS_OFFSET 0x0008
28 #define EFI_AHCI_PI_OFFSET 0x000C
30 #define EFI_AHCI_MAX_PORTS 32
43 // Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.
45 #define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 10
47 // Refer SATA1.0a spec, the FIS enable time should be less than 500ms.
49 #define EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT EFI_TIMER_PERIOD_MILLISECONDS(500)
51 // Refer SATA1.0a spec, the bus reset time should be less than 1s.
53 #define EFI_AHCI_BUS_RESET_TIMEOUT EFI_TIMER_PERIOD_SECONDS(1)
55 #define EFI_AHCI_ATAPI_DEVICE_SIG 0xEB140000
56 #define EFI_AHCI_ATA_DEVICE_SIG 0x00000000
57 #define EFI_AHCI_PORT_MULTIPLIER_SIG 0x96690000
58 #define EFI_AHCI_ATAPI_SIG_MASK 0xFFFF0000
61 // Each PRDT entry can point to a memory block up to 4M byte
63 #define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000
65 #define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device
66 #define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20
67 #define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host
68 #define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20
69 #define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host
70 #define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4
71 #define EFI_AHCI_FIS_DMA_SETUP 0x41 //DMA Setup FIS - Bi-directional
72 #define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28
73 #define EFI_AHCI_FIS_DATA 0x46 //Data FIS - Bi-directional
74 #define EFI_AHCI_FIS_BIST 0x58 //BIST Activate FIS - Bi-directional
75 #define EFI_AHCI_FIS_BIST_LENGTH 12
76 #define EFI_AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host
77 #define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20
78 #define EFI_AHCI_FIS_SET_DEVICE 0xA1 //Set Device Bits FIS - Device to Host
79 #define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8
81 #define EFI_AHCI_D2H_FIS_OFFSET 0x40
82 #define EFI_AHCI_DMA_FIS_OFFSET 0x00
83 #define EFI_AHCI_PIO_FIS_OFFSET 0x20
84 #define EFI_AHCI_SDB_FIS_OFFSET 0x58
85 #define EFI_AHCI_FIS_TYPE_MASK 0xFF
86 #define EFI_AHCI_U_FIS_OFFSET 0x60
91 #define EFI_AHCI_PORT_START 0x0100
92 #define EFI_AHCI_PORT_REG_WIDTH 0x0080
93 #define EFI_AHCI_PORT_CLB 0x0000
94 #define EFI_AHCI_PORT_CLBU 0x0004
95 #define EFI_AHCI_PORT_FB 0x0008
96 #define EFI_AHCI_PORT_FBU 0x000C
97 #define EFI_AHCI_PORT_IS 0x0010
98 #define EFI_AHCI_PORT_IS_DHRS BIT0
99 #define EFI_AHCI_PORT_IS_PSS BIT1
100 #define EFI_AHCI_PORT_IS_SSS BIT2
101 #define EFI_AHCI_PORT_IS_SDBS BIT3
102 #define EFI_AHCI_PORT_IS_UFS BIT4
103 #define EFI_AHCI_PORT_IS_DPS BIT5
104 #define EFI_AHCI_PORT_IS_PCS BIT6
105 #define EFI_AHCI_PORT_IS_DIS BIT7
106 #define EFI_AHCI_PORT_IS_PRCS BIT22
107 #define EFI_AHCI_PORT_IS_IPMS BIT23
108 #define EFI_AHCI_PORT_IS_OFS BIT24
109 #define EFI_AHCI_PORT_IS_INFS BIT26
110 #define EFI_AHCI_PORT_IS_IFS BIT27
111 #define EFI_AHCI_PORT_IS_HBDS BIT28
112 #define EFI_AHCI_PORT_IS_HBFS BIT29
113 #define EFI_AHCI_PORT_IS_TFES BIT30
114 #define EFI_AHCI_PORT_IS_CPDS BIT31
115 #define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF
116 #define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F
118 #define EFI_AHCI_PORT_IE 0x0014
119 #define EFI_AHCI_PORT_CMD 0x0018
120 #define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE
121 #define EFI_AHCI_PORT_CMD_ST BIT0
122 #define EFI_AHCI_PORT_CMD_SUD BIT1
123 #define EFI_AHCI_PORT_CMD_POD BIT2
124 #define EFI_AHCI_PORT_CMD_CLO BIT3
125 #define EFI_AHCI_PORT_CMD_CR BIT15
126 #define EFI_AHCI_PORT_CMD_FRE BIT4
127 #define EFI_AHCI_PORT_CMD_FR BIT14
128 #define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)
129 #define EFI_AHCI_PORT_CMD_PMA BIT17
130 #define EFI_AHCI_PORT_CMD_HPCP BIT18
131 #define EFI_AHCI_PORT_CMD_MPSP BIT19
132 #define EFI_AHCI_PORT_CMD_CPD BIT20
133 #define EFI_AHCI_PORT_CMD_ESP BIT21
134 #define EFI_AHCI_PORT_CMD_ATAPI BIT24
135 #define EFI_AHCI_PORT_CMD_DLAE BIT25
136 #define EFI_AHCI_PORT_CMD_ALPE BIT26
137 #define EFI_AHCI_PORT_CMD_ASP BIT27
138 #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
139 #define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 )
140 #define EFI_AHCI_PORT_TFD 0x0020
141 #define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)
142 #define EFI_AHCI_PORT_TFD_BSY BIT7
143 #define EFI_AHCI_PORT_TFD_DRQ BIT3
144 #define EFI_AHCI_PORT_TFD_ERR BIT0
145 #define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00
146 #define EFI_AHCI_PORT_SIG 0x0024
147 #define EFI_AHCI_PORT_SSTS 0x0028
148 #define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F
149 #define EFI_AHCI_PORT_SSTS_DET 0x0001
150 #define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003
151 #define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0
152 #define EFI_AHCI_PORT_SCTL 0x002C
153 #define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F
154 #define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK)
155 #define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001
156 #define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003
157 #define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0
158 #define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00
159 #define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300
160 #define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100
161 #define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200
162 #define EFI_AHCI_PORT_SERR 0x0030
163 #define EFI_AHCI_PORT_SERR_RDIE BIT0
164 #define EFI_AHCI_PORT_SERR_RCE BIT1
165 #define EFI_AHCI_PORT_SERR_TDIE BIT8
166 #define EFI_AHCI_PORT_SERR_PCDIE BIT9
167 #define EFI_AHCI_PORT_SERR_PE BIT10
168 #define EFI_AHCI_PORT_SERR_IE BIT11
169 #define EFI_AHCI_PORT_SERR_PRC BIT16
170 #define EFI_AHCI_PORT_SERR_PIE BIT17
171 #define EFI_AHCI_PORT_SERR_CW BIT18
172 #define EFI_AHCI_PORT_SERR_BDE BIT19
173 #define EFI_AHCI_PORT_SERR_DE BIT20
174 #define EFI_AHCI_PORT_SERR_CRCE BIT21
175 #define EFI_AHCI_PORT_SERR_HE BIT22
176 #define EFI_AHCI_PORT_SERR_LSE BIT23
177 #define EFI_AHCI_PORT_SERR_TSTE BIT24
178 #define EFI_AHCI_PORT_SERR_UFT BIT25
179 #define EFI_AHCI_PORT_SERR_EX BIT26
180 #define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF
181 #define EFI_AHCI_PORT_SACT 0x0034
182 #define EFI_AHCI_PORT_CI 0x0038
183 #define EFI_AHCI_PORT_SNTF 0x003C
188 // Command List structure includes total 32 entries.
189 // The entry data structure is listed at the following.
192 UINT32 AhciCmdCfl
:5; //Command FIS Length
193 UINT32 AhciCmdA
:1; //ATAPI
194 UINT32 AhciCmdW
:1; //Write
195 UINT32 AhciCmdP
:1; //Prefetchable
196 UINT32 AhciCmdR
:1; //Reset
197 UINT32 AhciCmdB
:1; //BIST
198 UINT32 AhciCmdC
:1; //Clear Busy upon R_OK
199 UINT32 AhciCmdRsvd
:1;
200 UINT32 AhciCmdPmp
:4; //Port Multiplier Port
201 UINT32 AhciCmdPrdtl
:16; //Physical Region Descriptor Table Length
202 UINT32 AhciCmdPrdbc
; //Physical Region Descriptor Byte Count
203 UINT32 AhciCmdCtba
; //Command Table Descriptor Base Address
204 UINT32 AhciCmdCtbau
; //Command Table Descriptor Base Address Upper 32-BITs
205 UINT32 AhciCmdRsvd1
[4];
206 } EFI_AHCI_COMMAND_LIST
;
209 // This is a software constructed FIS.
210 // For data transfer operations, this is the H2D Register FIS format as
211 // specified in the Serial ATA Revision 2.6 specification.
215 UINT8 AhciCFisPmNum
:4;
216 UINT8 AhciCFisRsvd
:1;
217 UINT8 AhciCFisRsvd1
:1;
218 UINT8 AhciCFisRsvd2
:1;
219 UINT8 AhciCFisCmdInd
:1;
221 UINT8 AhciCFisFeature
;
222 UINT8 AhciCFisSecNum
;
223 UINT8 AhciCFisClyLow
;
224 UINT8 AhciCFisClyHigh
;
225 UINT8 AhciCFisDevHead
;
226 UINT8 AhciCFisSecNumExp
;
227 UINT8 AhciCFisClyLowExp
;
228 UINT8 AhciCFisClyHighExp
;
229 UINT8 AhciCFisFeatureExp
;
230 UINT8 AhciCFisSecCount
;
231 UINT8 AhciCFisSecCountExp
;
233 UINT8 AhciCFisControl
;
234 UINT8 AhciCFisRsvd4
[4];
235 UINT8 AhciCFisRsvd5
[44];
236 } EFI_AHCI_COMMAND_FIS
;
239 // ACMD: ATAPI command (12 or 16 bytes)
242 UINT8 AtapiCmd
[0x10];
243 } EFI_AHCI_ATAPI_COMMAND
;
246 // Physical Region Descriptor Table includes up to 65535 entries
247 // The entry data structure is listed at the following.
248 // the actual entry number comes from the PRDTL field in the command
249 // list entry for this command slot.
252 UINT32 AhciPrdtDba
; //Data Base Address
253 UINT32 AhciPrdtDbau
; //Data Base Address Upper 32-BITs
255 UINT32 AhciPrdtDbc
:22; //Data Byte Count
256 UINT32 AhciPrdtRsvd1
:9;
257 UINT32 AhciPrdtIoc
:1; //Interrupt on Completion
258 } EFI_AHCI_COMMAND_PRDT
;
261 // Command table data strucute which is pointed to by the entry in the command list
264 EFI_AHCI_COMMAND_FIS CommandFis
; // A software constructed FIS.
265 EFI_AHCI_ATAPI_COMMAND AtapiCmd
; // 12 or 16 bytes ATAPI cmd.
266 UINT8 Reserved
[0x30];
267 EFI_AHCI_COMMAND_PRDT PrdtTable
[65535]; // The scatter/gather list for data transfer
268 } EFI_AHCI_COMMAND_TABLE
;
271 // Received FIS structure
274 UINT8 AhciDmaSetupFis
[0x1C]; // Dma Setup Fis: offset 0x00
275 UINT8 AhciDmaSetupFisRsvd
[0x04];
276 UINT8 AhciPioSetupFis
[0x14]; // Pio Setup Fis: offset 0x20
277 UINT8 AhciPioSetupFisRsvd
[0x0C];
278 UINT8 AhciD2HRegisterFis
[0x14]; // D2H Register Fis: offset 0x40
279 UINT8 AhciD2HRegisterFisRsvd
[0x04];
280 UINT64 AhciSetDeviceBitsFis
; // Set Device Bits Fix: offset 0x58
281 UINT8 AhciUnknownFis
[0x40]; // Unkonwn Fis: offset 0x60
282 UINT8 AhciUnknownFisRsvd
[0x60];
283 } EFI_AHCI_RECEIVED_FIS
;
288 EFI_AHCI_RECEIVED_FIS
*AhciRFis
;
289 EFI_AHCI_COMMAND_LIST
*AhciCmdList
;
290 EFI_AHCI_COMMAND_TABLE
*AhciCommandTable
;
291 EFI_AHCI_RECEIVED_FIS
*AhciRFisPciAddr
;
292 EFI_AHCI_COMMAND_LIST
*AhciCmdListPciAddr
;
293 EFI_AHCI_COMMAND_TABLE
*AhciCommandTablePciAddr
;
294 UINT64 MaxCommandListSize
;
295 UINT64 MaxCommandTableSize
;
296 UINT64 MaxReceiveFisSize
;
299 VOID
*MapCommandTable
;
300 } EFI_AHCI_REGISTERS
;
303 This function is used to send out ATAPI commands conforms to the Packet Command
306 @param PciIo The PCI IO protocol instance.
307 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
308 @param Port The number of port.
309 @param PortMultiplier The number of port multiplier.
310 @param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
312 @retval EFI_SUCCESS send out the ATAPI packet command successfully
313 and device sends data successfully.
314 @retval EFI_DEVICE_ERROR the device failed to send data.
319 AhciPacketCommandExecute (
320 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
321 IN EFI_AHCI_REGISTERS
*AhciRegisters
,
323 IN UINT8 PortMultiplier
,
324 IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET
*Packet
328 Start command for give slot on specific port.
330 @param PciIo The PCI IO protocol instance.
331 @param Port The number of port.
332 @param CommandSlot The number of CommandSlot.
333 @param Timeout The timeout value of start, uses 100ns as a unit.
335 @retval EFI_DEVICE_ERROR The command start unsuccessfully.
336 @retval EFI_TIMEOUT The operation is time out.
337 @retval EFI_SUCCESS The command start successfully.
343 IN EFI_PCI_IO_PROTOCOL
*PciIo
,
345 IN UINT8 CommandSlot
,
350 Stop command running for giving port
352 @param PciIo The PCI IO protocol instance.
353 @param Port The number of port.
354 @param Timeout The timeout value of stop, uses 100ns as a unit.
356 @retval EFI_DEVICE_ERROR The command stop unsuccessfully.
357 @retval EFI_TIMEOUT The operation is time out.
358 @retval EFI_SUCCESS The command stop successfully.
364 IN EFI_PCI_IO_PROTOCOL
*PciIo
,