MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h

   1 /** @file
   2   Header file for AHCI mode of ATA host controller.
   3
   4   Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
   5   This program and the accompanying materials
   6   are licensed and made available under the terms and conditions of the BSD License
   7   which accompanies this distribution.  The full text of the license may be found at
   8   http://opensource.org/licenses/bsd-license.php
   9
  10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12
  13 **/
  14 #ifndef __ATA_HC_AHCI_MODE_H__
  15 #define __ATA_HC_AHCI_MODE_H__
  16
  17 #define EFI_AHCI_BAR_INDEX                     0x05
  18
  19 #define EFI_AHCI_CAPABILITY_OFFSET             0x0000
  20 #define EFI_AHCI_GHC_OFFSET                    0x0004
  21 #define   EFI_AHCI_GHC_RESET                   BIT0
  22 #define   EFI_AHCI_GHC_IE                      BIT1
  23 #define   EFI_AHCI_GHC_ENABLE                  BIT31
  24 #define EFI_AHCI_IS_OFFSET                     0x0008
  25 #define EFI_AHCI_PI_OFFSET                     0x000C
  26
  27 typedef struct {
  28   UINT32  Lower32;
  29   UINT32  Upper32;
  30 } DATA_32;
  31
  32 typedef union {
  33   DATA_32   Uint32;
  34   UINT64    Uint64;
  35 } DATA_64;
  36
  37 #define  EFI_AHCI_ATAPI_DEVICE_SIG             0xEB140000
  38 #define  EFI_AHCI_ATA_DEVICE_SIG               0x00000000
  39 #define  EFI_AHCI_PORT_MULTIPLIER_SIG          0x96690000
  40 #define  EFI_AHCI_ATAPI_SIG_MASK               0xFFFF0000
  41
  42 //
  43 // Each PRDT entry can point to a memory block up to 4M byte
  44 //
  45 #define EFI_AHCI_MAX_DATA_PER_PRDT             0x400000
  46
  47 #define EFI_AHCI_FIS_REGISTER_H2D              0x27      //Register FIS - Host to Device
  48 #define   EFI_AHCI_FIS_REGISTER_H2D_LENGTH     20
  49 #define EFI_AHCI_FIS_REGISTER_D2H              0x34      //Register FIS - Device to Host
  50 #define   EFI_AHCI_FIS_REGISTER_D2H_LENGTH     20
  51 #define EFI_AHCI_FIS_DMA_ACTIVATE              0x39      //DMA Activate FIS - Device to Host
  52 #define   EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH     4
  53 #define EFI_AHCI_FIS_DMA_SETUP                 0x41      //DMA Setup FIS - Bi-directional
  54 #define   EFI_AHCI_FIS_DMA_SETUP_LENGTH        28
  55 #define EFI_AHCI_FIS_DATA                      0x46      //Data FIS - Bi-directional
  56 #define EFI_AHCI_FIS_BIST                      0x58      //BIST Activate FIS - Bi-directional
  57 #define   EFI_AHCI_FIS_BIST_LENGTH             12
  58 #define EFI_AHCI_FIS_PIO_SETUP                 0x5F      //PIO Setup FIS - Device to Host
  59 #define   EFI_AHCI_FIS_PIO_SETUP_LENGTH        20
  60 #define EFI_AHCI_FIS_SET_DEVICE                0xA1      //Set Device Bits FIS - Device to Host
  61 #define   EFI_AHCI_FIS_SET_DEVICE_LENGTH       8
  62
  63 #define EFI_AHCI_D2H_FIS_OFFSET                0x40
  64 #define EFI_AHCI_DMA_FIS_OFFSET                0x00
  65 #define EFI_AHCI_PIO_FIS_OFFSET                0x20
  66 #define EFI_AHCI_SDB_FIS_OFFSET                0x58
  67 #define EFI_AHCI_FIS_TYPE_MASK                 0xFF
  68 #define EFI_AHCI_U_FIS_OFFSET                  0x60
  69
  70 //
  71 // Port register
  72 //
  73 #define EFI_AHCI_PORT_START                    0x0100
  74 #define EFI_AHCI_PORT_REG_WIDTH                0x0080
  75 #define EFI_AHCI_PORT_CLB                      0x0000
  76 #define EFI_AHCI_PORT_CLBU                     0x0004
  77 #define EFI_AHCI_PORT_FB                       0x0008
  78 #define EFI_AHCI_PORT_FBU                      0x000C
  79 #define EFI_AHCI_PORT_IS                       0x0010
  80 #define   EFI_AHCI_PORT_IS_DHRS                BIT0
  81 #define   EFI_AHCI_PORT_IS_PSS                 BIT1
  82 #define   EFI_AHCI_PORT_IS_SSS                 BIT2
  83 #define   EFI_AHCI_PORT_IS_SDBS                BIT3
  84 #define   EFI_AHCI_PORT_IS_UFS                 BIT4
  85 #define   EFI_AHCI_PORT_IS_DPS                 BIT5
  86 #define   EFI_AHCI_PORT_IS_PCS                 BIT6
  87 #define   EFI_AHCI_PORT_IS_DIS                 BIT7
  88 #define   EFI_AHCI_PORT_IS_PRCS                BIT22
  89 #define   EFI_AHCI_PORT_IS_IPMS                BIT23
  90 #define   EFI_AHCI_PORT_IS_OFS                 BIT24
  91 #define   EFI_AHCI_PORT_IS_INFS                BIT26
  92 #define   EFI_AHCI_PORT_IS_IFS                 BIT27
  93 #define   EFI_AHCI_PORT_IS_HBDS                BIT28
  94 #define   EFI_AHCI_PORT_IS_HBFS                BIT29
  95 #define   EFI_AHCI_PORT_IS_TFES                BIT30
  96 #define   EFI_AHCI_PORT_IS_CPDS                BIT31
  97 #define   EFI_AHCI_PORT_IS_CLEAR               0xFFFFFFFF
  98 #define   EFI_AHCI_PORT_IS_FIS_CLEAR           0x0000000F
  99
 100 #define EFI_AHCI_PORT_IE                       0x0014
 101 #define EFI_AHCI_PORT_CMD                      0x0018
 102 #define   EFI_AHCI_PORT_CMD_ST_MASK            0xFFFFFFFE
 103 #define   EFI_AHCI_PORT_CMD_ST                 BIT0
 104 #define   EFI_AHCI_PORT_CMD_SUD                BIT1
 105 #define   EFI_AHCI_PORT_CMD_POD                BIT2
 106 #define   EFI_AHCI_PORT_CMD_COL                BIT3
 107 #define   EFI_AHCI_PORT_CMD_CR                 BIT15
 108 #define   EFI_AHCI_PORT_CMD_FRE                BIT4
 109 #define   EFI_AHCI_PORT_CMD_FR                 BIT14
 110 #define   EFI_AHCI_PORT_CMD_MASK               ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)
 111 #define   EFI_AHCI_PORT_CMD_PMA                BIT17
 112 #define   EFI_AHCI_PORT_CMD_HPCP               BIT18
 113 #define   EFI_AHCI_PORT_CMD_MPSP               BIT19
 114 #define   EFI_AHCI_PORT_CMD_CPD                BIT20
 115 #define   EFI_AHCI_PORT_CMD_ESP                BIT21
 116 #define   EFI_AHCI_PORT_CMD_ATAPI              BIT24
 117 #define   EFI_AHCI_PORT_CMD_DLAE               BIT25
 118 #define   EFI_AHCI_PORT_CMD_ALPE               BIT26
 119 #define   EFI_AHCI_PORT_CMD_ASP                BIT27
 120 #define   EFI_AHCI_PORT_CMD_ICC_MASK           (BIT28 | BIT29 | BIT30 | BIT31)
 121 #define   EFI_AHCI_PORT_CMD_ACTIVE             (1 << 28 )
 122 #define EFI_AHCI_PORT_TFD                      0x0020
 123 #define   EFI_AHCI_PORT_TFD_MASK               (BIT7 | BIT3 | BIT0)
 124 #define   EFI_AHCI_PORT_TFD_BSY                BIT7
 125 #define   EFI_AHCI_PORT_TFD_DRQ                BIT3
 126 #define   EFI_AHCI_PORT_TFD_ERR                BIT0
 127 #define   EFI_AHCI_PORT_TFD_ERR_MASK           0x00FF00
 128 #define EFI_AHCI_PORT_SIG                      0x0024
 129 #define EFI_AHCI_PORT_SSTS                     0x0028
 130 #define   EFI_AHCI_PORT_SSTS_DET_MASK          0x000F
 131 #define   EFI_AHCI_PORT_SSTS_DET               0x0001
 132 #define   EFI_AHCI_PORT_SSTS_DET_PCE           0x0003
 133 #define   EFI_AHCI_PORT_SSTS_SPD_MASK          0x00F0
 134 #define EFI_AHCI_PORT_SCTL                     0x002C
 135 #define   EFI_AHCI_PORT_SCTL_DET_MASK          0x000F
 136 #define   EFI_AHCI_PORT_SCTL_MASK              (~EFI_AHCI_PORT_SCTL_DET_MASK)
 137 #define   EFI_AHCI_PORT_SCTL_DET_INIT          0x0001
 138 #define   EFI_AHCI_PORT_SCTL_DET_PHYCOMM       0x0003
 139 #define   EFI_AHCI_PORT_SCTL_SPD_MASK          0x00F0
 140 #define   EFI_AHCI_PORT_SCTL_IPM_MASK          0x0F00
 141 #define   EFI_AHCI_PORT_SCTL_IPM_INIT          0x0300
 142 #define   EFI_AHCI_PORT_SCTL_IPM_PSD           0x0100
 143 #define   EFI_AHCI_PORT_SCTL_IPM_SSD           0x0200
 144 #define EFI_AHCI_PORT_SERR                     0x0030
 145 #define   EFI_AHCI_PORT_SERR_RDIE              BIT0
 146 #define   EFI_AHCI_PORT_SERR_RCE               BIT1
 147 #define   EFI_AHCI_PORT_SERR_TDIE              BIT8
 148 #define   EFI_AHCI_PORT_SERR_PCDIE             BIT9
 149 #define   EFI_AHCI_PORT_SERR_PE                BIT10
 150 #define   EFI_AHCI_PORT_SERR_IE                BIT11
 151 #define   EFI_AHCI_PORT_SERR_PRC               BIT16
 152 #define   EFI_AHCI_PORT_SERR_PIE               BIT17
 153 #define   EFI_AHCI_PORT_SERR_CW                BIT18
 154 #define   EFI_AHCI_PORT_SERR_BDE               BIT19
 155 #define   EFI_AHCI_PORT_SERR_DE                BIT20
 156 #define   EFI_AHCI_PORT_SERR_CRCE              BIT21
 157 #define   EFI_AHCI_PORT_SERR_HE                BIT22
 158 #define   EFI_AHCI_PORT_SERR_LSE               BIT23
 159 #define   EFI_AHCI_PORT_SERR_TSTE              BIT24
 160 #define   EFI_AHCI_PORT_SERR_UFT               BIT25
 161 #define   EFI_AHCI_PORT_SERR_EX                BIT26
 162 #define   EFI_AHCI_PORT_ERR_CLEAR              0xFFFFFFFF
 163 #define EFI_AHCI_PORT_SACT                     0x0034
 164 #define EFI_AHCI_PORT_CI                       0x0038
 165 #define EFI_AHCI_PORT_SNTF                     0x003C
 166
 167
 168 #pragma pack(1)
 169 //
 170 // Command List structure includes total 32 entries.
 171 // The entry data structure is listed at the following.
 172 //
 173 typedef struct {
 174   UINT32   AhciCmdCfl:5;      //Command FIS Length
 175   UINT32   AhciCmdA:1;        //ATAPI
 176   UINT32   AhciCmdW:1;        //Write
 177   UINT32   AhciCmdP:1;        //Prefetchable
 178   UINT32   AhciCmdR:1;        //Reset
 179   UINT32   AhciCmdB:1;        //BIST
 180   UINT32   AhciCmdC:1;        //Clear Busy upon R_OK
 181   UINT32   AhciCmdRsvd:1;
 182   UINT32   AhciCmdPmp:4;      //Port Multiplier Port
 183   UINT32   AhciCmdPrdtl:16;   //Physical Region Descriptor Table Length
 184   UINT32   AhciCmdPrdbc;      //Physical Region Descriptor Byte Count
 185   UINT32   AhciCmdCtba;       //Command Table Descriptor Base Address
 186   UINT32   AhciCmdCtbau;      //Command Table Descriptor Base Address Upper 32-BITs
 187   UINT32   AhciCmdRsvd1[4];
 188 } EFI_AHCI_COMMAND_LIST;
 189
 190 //
 191 // This is a software constructed FIS.
 192 // For data transfer operations, this is the H2D Register FIS format as
 193 // specified in the Serial ATA Revision 2.6 specification.
 194 //
 195 typedef struct {
 196   UINT8    AhciCFisType;
 197   UINT8    AhciCFisPmNum:4;
 198   UINT8    AhciCFisRsvd:1;
 199   UINT8    AhciCFisRsvd1:1;
 200   UINT8    AhciCFisRsvd2:1;
 201   UINT8    AhciCFisCmdInd:1;
 202   UINT8    AhciCFisCmd;
 203   UINT8    AhciCFisFeature;
 204   UINT8    AhciCFisSecNum;
 205   UINT8    AhciCFisClyLow;
 206   UINT8    AhciCFisClyHigh;
 207   UINT8    AhciCFisDevHead;
 208   UINT8    AhciCFisSecNumExp;
 209   UINT8    AhciCFisClyLowExp;
 210   UINT8    AhciCFisClyHighExp;
 211   UINT8    AhciCFisFeatureExp;
 212   UINT8    AhciCFisSecCount;
 213   UINT8    AhciCFisSecCountExp;
 214   UINT8    AhciCFisRsvd3;
 215   UINT8    AhciCFisControl;
 216   UINT8    AhciCFisRsvd4[4];
 217   UINT8    AhciCFisRsvd5[44];
 218 } EFI_AHCI_COMMAND_FIS;
 219
 220 //
 221 // ACMD: ATAPI command (12 or 16 bytes)
 222 //
 223 typedef struct {
 224   UINT8    AtapiCmd[0x10];
 225 } EFI_AHCI_ATAPI_COMMAND;
 226
 227 //
 228 // Physical Region Descriptor Table includes up to 65535 entries
 229 // The entry data structure is listed at the following.
 230 // the actual entry number comes from the PRDTL field in the command
 231 // list entry for this command slot.
 232 //
 233 typedef struct {
 234   UINT32   AhciPrdtDba;       //Data Base Address
 235   UINT32   AhciPrdtDbau;      //Data Base Address Upper 32-BITs
 236   UINT32   AhciPrdtRsvd;
 237   UINT32   AhciPrdtDbc:22;    //Data Byte Count
 238   UINT32   AhciPrdtRsvd1:9;
 239   UINT32   AhciPrdtIoc:1;     //Interrupt on Completion
 240 } EFI_AHCI_COMMAND_PRDT;
 241
 242 //
 243 // Command table data strucute which is pointed to by the entry in the command list
 244 //
 245 typedef struct {
 246   EFI_AHCI_COMMAND_FIS      CommandFis;       // A software constructed FIS.
 247   EFI_AHCI_ATAPI_COMMAND    AtapiCmd;         // 12 or 16 bytes ATAPI cmd.
 248   UINT8                     Reserved[0x30];
 249   EFI_AHCI_COMMAND_PRDT     PrdtTable[65535];     // The scatter/gather list for data transfer
 250 } EFI_AHCI_COMMAND_TABLE;
 251
 252 //
 253 // Received FIS structure
 254 //
 255 typedef struct {
 256   UINT8    AhciDmaSetupFis[0x1C];         // Dma Setup Fis: offset 0x00
 257   UINT8    AhciDmaSetupFisRsvd[0x04];
 258   UINT8    AhciPioSetupFis[0x14];         // Pio Setup Fis: offset 0x20
 259   UINT8    AhciPioSetupFisRsvd[0x0C];
 260   UINT8    AhciD2HRegisterFis[0x14];      // D2H Register Fis: offset 0x40
 261   UINT8    AhciD2HRegisterFisRsvd[0x04];
 262   UINT64   AhciSetDeviceBitsFis;          // Set Device Bits Fix: offset 0x58
 263   UINT8    AhciUnknownFis[0x40];          // Unkonwn Fis: offset 0x60
 264   UINT8    AhciUnknownFisRsvd[0x60];
 265 } EFI_AHCI_RECEIVED_FIS;
 266
 267 #pragma pack()
 268
 269 typedef struct {
 270   EFI_AHCI_RECEIVED_FIS     *AhciRFis;
 271   EFI_AHCI_COMMAND_LIST     *AhciCmdList;
 272   EFI_AHCI_COMMAND_TABLE    *AhciCommandTable;
 273   EFI_AHCI_RECEIVED_FIS     *AhciRFisPciAddr;
 274   EFI_AHCI_COMMAND_LIST     *AhciCmdListPciAddr;
 275   EFI_AHCI_COMMAND_TABLE    *AhciCommandTablePciAddr;
 276   UINT64                    MaxCommandListSize;
 277   UINT64                    MaxCommandTableSize;
 278   UINT64                    MaxReceiveFisSize;
 279   VOID                      *MapRFis;
 280   VOID                      *MapCmdList;
 281   VOID                      *MapCommandTable;
 282 } EFI_AHCI_REGISTERS;
 283
 284 /**
 285   This function is used to send out ATAPI commands conforms to the Packet Command
 286   with PIO Protocol.
 287
 288   @param PciIo              The PCI IO protocol instance.
 289   @param AhciRegisters      The pointer to the EFI_AHCI_REGISTERS.
 290   @param Port               The number of port.
 291   @param PortMultiplier     The number of port multiplier.
 292   @param Packet             A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
 293
 294   @retval EFI_SUCCESS       send out the ATAPI packet command successfully
 295                             and device sends data successfully.
 296   @retval EFI_DEVICE_ERROR  the device failed to send data.
 297
 298 **/
 299 EFI_STATUS
 300 EFIAPI
 301 AhciPacketCommandExecute (
 302   IN  EFI_PCI_IO_PROTOCOL                           *PciIo,
 303   IN  EFI_AHCI_REGISTERS                            *AhciRegisters,
 304   IN  UINT8                                         Port,
 305   IN  UINT8                                         PortMultiplier,
 306   IN  EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET    *Packet
 307   );
 308
 309 /**
 310   Start command for give slot on specific port.
 311
 312   @param  PciIo              The PCI IO protocol instance.
 313   @param  Port               The number of port.
 314   @param  CommandSlot        The number of CommandSlot.
 315   @param  Timeout            The timeout value of start.
 316
 317   @retval EFI_DEVICE_ERROR   The command start unsuccessfully.
 318   @retval EFI_TIMEOUT        The operation is time out.
 319   @retval EFI_SUCCESS        The command start successfully.
 320
 321 **/
 322 EFI_STATUS
 323 EFIAPI
 324 AhciStartCommand (
 325   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 326   IN  UINT8                     Port,
 327   IN  UINT8                     CommandSlot,
 328   IN  UINT64                    Timeout
 329   );
 330
 331 /**
 332   Stop command running for giving port
 333
 334   @param  PciIo              The PCI IO protocol instance.
 335   @param  Port               The number of port.
 336   @param  Timeout            The timeout value of stop.
 337
 338   @retval EFI_DEVICE_ERROR   The command stop unsuccessfully.
 339   @retval EFI_TIMEOUT        The operation is time out.
 340   @retval EFI_SUCCESS        The command stop successfully.
 341
 342 **/
 343 EFI_STATUS
 344 EFIAPI
 345 AhciStopCommand (
 346   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 347   IN  UINT8                     Port,
 348   IN  UINT64                    Timeout
 349   );
 350
 351 /**
 352   Start a non data transfer on specific port.
 353
 354   @param  PciIo             The PCI IO protocol instance.
 355   @param  AhciRegisters         The pointer to the EFI_AHCI_REGISTERS.
 356   @param  Port              The number of port.
 357   @param  PortMultiplier      The timeout value of stop.
 358   @param  AtapiCommand      The atapi command will be used for the transfer.
 359   @param  AtapiCommandLength    The length of the atapi command.
 360   @param    AtaCommandBlock       The EFI_ATA_COMMAND_BLOCK data.
 361   @param    AtaStatusBlock        The EFI_ATA_STATUS_BLOCK data.
 362   @param  Timeout               The timeout value of non data transfer.
 363
 364   @retval EFI_DEVICE_ERROR    The non data transfer abort with error occurs.
 365   @retval EFI_TIMEOUT         The operation is time out.
 366   @retval EFI_UNSUPPORTED     The device is not ready for transfer.
 367   @retval EFI_SUCCESS         The non data transfer executes successfully.
 368
 369 **/
 370 EFI_STATUS
 371 EFIAPI
 372 AhciNonDataTransfer (
 373   IN     EFI_PCI_IO_PROTOCOL           *PciIo,
 374   IN     EFI_AHCI_REGISTERS            *AhciRegisters,
 375   IN     UINT8                         Port,
 376   IN     UINT8                         PortMultiplier,
 377   IN     EFI_AHCI_ATAPI_COMMAND        *AtapiCommand OPTIONAL,
 378   IN     UINT8                         AtapiCommandLength,
 379   IN     EFI_ATA_COMMAND_BLOCK         *AtaCommandBlock,
 380   IN OUT EFI_ATA_STATUS_BLOCK          *AtaStatusBlock,
 381   IN     UINT64                        Timeout
 382   );
 383
 384 /**
 385   Start a DMA data transfer on specific port
 386
 387   @param  PciIo         The PCI IO protocol instance.
 388   @param  AhciRegisters         The pointer to the EFI_AHCI_REGISTERS.
 389   @param  Port          The number of port.
 390   @param  PortMultiplier      The timeout value of stop.
 391   @param  AtapiCommand        The atapi command will be used for the transfer.
 392   @param  AtapiCommandLength    The length of the atapi command.
 393   @param  Read                  The transfer direction.
 394   @param  AtaCommandBlock       The EFI_ATA_COMMAND_BLOCK data.
 395   @param  AtaStatusBlock        The EFI_ATA_STATUS_BLOCK data.
 396   @param  MemoryAddr            The pointer to the data buffer.
 397   @param  DataCount             The data count to be transferred.
 398   @param  Timeout               The timeout value of non data transfer.
 399
 400   @retval EFI_DEVICE_ERROR  The DMA data transfer abort with error occurs.
 401   @retval EFI_TIMEOUT     The operation is time out.
 402   @retval EFI_UNSUPPORTED   The device is not ready for transfer.
 403   @retval EFI_SUCCESS     The DMA data transfer executes successfully.
 404
 405 **/
 406 EFI_STATUS
 407 EFIAPI
 408 AhciDmaTransfer (
 409   IN     EFI_PCI_IO_PROTOCOL        *PciIo,
 410   IN     EFI_AHCI_REGISTERS         *AhciRegisters,
 411   IN     UINT8                      Port,
 412   IN     UINT8                      PortMultiplier,
 413   IN     EFI_AHCI_ATAPI_COMMAND     *AtapiCommand OPTIONAL,
 414   IN     UINT8                      AtapiCommandLength,
 415   IN     BOOLEAN                    Read,
 416   IN     EFI_ATA_COMMAND_BLOCK      *AtaCommandBlock,
 417   IN OUT EFI_ATA_STATUS_BLOCK       *AtaStatusBlock,
 418   IN OUT VOID                       *MemoryAddr,
 419   IN     UINTN                      DataCount,
 420   IN     UINT64                     Timeout
 421   );
 422
 423 /**
 424   Start a PIO data transfer on specific port.
 425
 426   @param  PciIo             The PCI IO protocol instance.
 427   @param  AhciRegisters       The pointer to the EFI_AHCI_REGISTERS.
 428   @param  Port              The number of port.
 429   @param  PortMultiplier    The timeout value of stop.
 430   @param  AtapiCommand      The atapi command will be used for the transfer.
 431   @param  AtapiCommandLength  The length of the atapi command.
 432   @param  Read                The transfer direction.
 433   @param  AtaCommandBlock     The EFI_ATA_COMMAND_BLOCK data.
 434   @param  AtaStatusBlock      The EFI_ATA_STATUS_BLOCK data.
 435   @param  MemoryAddr          The pointer to the data buffer.
 436   @param  DataCount           The data count to be transferred.
 437   @param  Timeout             The timeout value of non data transfer.
 438
 439   @retval EFI_DEVICE_ERROR    The PIO data transfer abort with error occurs.
 440   @retval EFI_TIMEOUT         The operation is time out.
 441   @retval EFI_UNSUPPORTED     The device is not ready for transfer.
 442   @retval EFI_SUCCESS         The PIO data transfer executes successfully.
 443
 444 **/
 445 EFI_STATUS
 446 EFIAPI
 447 AhciPioTransfer (
 448   IN     EFI_PCI_IO_PROTOCOL        *PciIo,
 449   IN     EFI_AHCI_REGISTERS         *AhciRegisters,
 450   IN     UINT8                      Port,
 451   IN     UINT8                      PortMultiplier,
 452   IN     EFI_AHCI_ATAPI_COMMAND     *AtapiCommand OPTIONAL,
 453   IN     UINT8                      AtapiCommandLength,
 454   IN     BOOLEAN                    Read,
 455   IN     EFI_ATA_COMMAND_BLOCK      *AtaCommandBlock,
 456   IN OUT EFI_ATA_STATUS_BLOCK       *AtaStatusBlock,
 457   IN OUT VOID                       *MemoryAddr,
 458   IN     UINT32                     DataCount,
 459   IN     UINT64                     Timeout
 460   );
 461
 462
 463 #endif
 464