MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h

   1 /** @file
   2   Header file for AHCI mode of ATA host controller.
   3
   4   Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8 #ifndef __ATA_HC_AHCI_MODE_H__
   9 #define __ATA_HC_AHCI_MODE_H__
  10
  11 #define EFI_AHCI_BAR_INDEX                     0x05
  12
  13 #define EFI_AHCI_CAPABILITY_OFFSET             0x0000
  14 #define   EFI_AHCI_CAP_SAM                     BIT18
  15 #define   EFI_AHCI_CAP_SSS                     BIT27
  16 #define   EFI_AHCI_CAP_S64A                    BIT31
  17 #define EFI_AHCI_GHC_OFFSET                    0x0004
  18 #define   EFI_AHCI_GHC_RESET                   BIT0
  19 #define   EFI_AHCI_GHC_IE                      BIT1
  20 #define   EFI_AHCI_GHC_ENABLE                  BIT31
  21 #define EFI_AHCI_IS_OFFSET                     0x0008
  22 #define EFI_AHCI_PI_OFFSET                     0x000C
  23
  24 #define EFI_AHCI_MAX_PORTS                     32
  25
  26 #define AHCI_CAPABILITY2_OFFSET                0x0024
  27 #define   AHCI_CAP2_SDS                        BIT3
  28 #define   AHCI_CAP2_SADM                       BIT4
  29
  30 typedef struct {
  31   UINT32  Lower32;
  32   UINT32  Upper32;
  33 } DATA_32;
  34
  35 typedef union {
  36   DATA_32   Uint32;
  37   UINT64    Uint64;
  38 } DATA_64;
  39
  40 //
  41 // Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.
  42 // Add a bit of margin for robustness.
  43 //
  44 #define  EFI_AHCI_BUS_PHY_DETECT_TIMEOUT       15
  45 //
  46 // Refer SATA1.0a spec, the FIS enable time should be less than 500ms.
  47 //
  48 #define  EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT    EFI_TIMER_PERIOD_MILLISECONDS(500)
  49 //
  50 // Refer SATA1.0a spec, the bus reset time should be less than 1s.
  51 //
  52 #define  EFI_AHCI_BUS_RESET_TIMEOUT            EFI_TIMER_PERIOD_SECONDS(1)
  53
  54 #define  EFI_AHCI_ATAPI_DEVICE_SIG             0xEB140000
  55 #define  EFI_AHCI_ATA_DEVICE_SIG               0x00000000
  56 #define  EFI_AHCI_PORT_MULTIPLIER_SIG          0x96690000
  57 #define  EFI_AHCI_ATAPI_SIG_MASK               0xFFFF0000
  58
  59 //
  60 // Each PRDT entry can point to a memory block up to 4M byte
  61 //
  62 #define EFI_AHCI_MAX_DATA_PER_PRDT             0x400000
  63
  64 #define EFI_AHCI_FIS_REGISTER_H2D              0x27      //Register FIS - Host to Device
  65 #define   EFI_AHCI_FIS_REGISTER_H2D_LENGTH     20
  66 #define EFI_AHCI_FIS_REGISTER_D2H              0x34      //Register FIS - Device to Host
  67 #define   EFI_AHCI_FIS_REGISTER_D2H_LENGTH     20
  68 #define EFI_AHCI_FIS_DMA_ACTIVATE              0x39      //DMA Activate FIS - Device to Host
  69 #define   EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH     4
  70 #define EFI_AHCI_FIS_DMA_SETUP                 0x41      //DMA Setup FIS - Bi-directional
  71 #define   EFI_AHCI_FIS_DMA_SETUP_LENGTH        28
  72 #define EFI_AHCI_FIS_DATA                      0x46      //Data FIS - Bi-directional
  73 #define EFI_AHCI_FIS_BIST                      0x58      //BIST Activate FIS - Bi-directional
  74 #define   EFI_AHCI_FIS_BIST_LENGTH             12
  75 #define EFI_AHCI_FIS_PIO_SETUP                 0x5F      //PIO Setup FIS - Device to Host
  76 #define   EFI_AHCI_FIS_PIO_SETUP_LENGTH        20
  77 #define EFI_AHCI_FIS_SET_DEVICE                0xA1      //Set Device Bits FIS - Device to Host
  78 #define   EFI_AHCI_FIS_SET_DEVICE_LENGTH       8
  79
  80 #define EFI_AHCI_D2H_FIS_OFFSET                0x40
  81 #define EFI_AHCI_DMA_FIS_OFFSET                0x00
  82 #define EFI_AHCI_PIO_FIS_OFFSET                0x20
  83 #define EFI_AHCI_SDB_FIS_OFFSET                0x58
  84 #define EFI_AHCI_FIS_TYPE_MASK                 0xFF
  85 #define EFI_AHCI_U_FIS_OFFSET                  0x60
  86
  87 //
  88 // Port register
  89 //
  90 #define EFI_AHCI_PORT_START                    0x0100
  91 #define EFI_AHCI_PORT_REG_WIDTH                0x0080
  92 #define EFI_AHCI_PORT_CLB                      0x0000
  93 #define EFI_AHCI_PORT_CLBU                     0x0004
  94 #define EFI_AHCI_PORT_FB                       0x0008
  95 #define EFI_AHCI_PORT_FBU                      0x000C
  96 #define EFI_AHCI_PORT_IS                       0x0010
  97 #define   EFI_AHCI_PORT_IS_DHRS                BIT0
  98 #define   EFI_AHCI_PORT_IS_PSS                 BIT1
  99 #define   EFI_AHCI_PORT_IS_DSS                 BIT2
 100 #define   EFI_AHCI_PORT_IS_SDBS                BIT3
 101 #define   EFI_AHCI_PORT_IS_UFS                 BIT4
 102 #define   EFI_AHCI_PORT_IS_DPS                 BIT5
 103 #define   EFI_AHCI_PORT_IS_PCS                 BIT6
 104 #define   EFI_AHCI_PORT_IS_DIS                 BIT7
 105 #define   EFI_AHCI_PORT_IS_PRCS                BIT22
 106 #define   EFI_AHCI_PORT_IS_IPMS                BIT23
 107 #define   EFI_AHCI_PORT_IS_OFS                 BIT24
 108 #define   EFI_AHCI_PORT_IS_INFS                BIT26
 109 #define   EFI_AHCI_PORT_IS_IFS                 BIT27
 110 #define   EFI_AHCI_PORT_IS_HBDS                BIT28
 111 #define   EFI_AHCI_PORT_IS_HBFS                BIT29
 112 #define   EFI_AHCI_PORT_IS_TFES                BIT30
 113 #define   EFI_AHCI_PORT_IS_CPDS                BIT31
 114 #define   EFI_AHCI_PORT_IS_CLEAR               0xFFFFFFFF
 115 #define   EFI_AHCI_PORT_IS_FIS_CLEAR           0x0000000F
 116 #define   EFI_AHCI_PORT_IS_ERROR_MASK          (EFI_AHCI_PORT_IS_INFS | EFI_AHCI_PORT_IS_IFS | EFI_AHCI_PORT_IS_HBDS | EFI_AHCI_PORT_IS_HBFS | EFI_AHCI_PORT_IS_TFES)
 117 #define   EFI_AHCI_PORT_IS_FATAL_ERROR_MASK    (EFI_AHCI_PORT_IS_IFS | EFI_AHCI_PORT_IS_HBDS | EFI_AHCI_PORT_IS_HBFS | EFI_AHCI_PORT_IS_TFES)
 118
 119 #define EFI_AHCI_PORT_IE                       0x0014
 120 #define EFI_AHCI_PORT_CMD                      0x0018
 121 #define   EFI_AHCI_PORT_CMD_ST_MASK            0xFFFFFFFE
 122 #define   EFI_AHCI_PORT_CMD_ST                 BIT0
 123 #define   EFI_AHCI_PORT_CMD_SUD                BIT1
 124 #define   EFI_AHCI_PORT_CMD_POD                BIT2
 125 #define   EFI_AHCI_PORT_CMD_CLO                BIT3
 126 #define   EFI_AHCI_PORT_CMD_FRE                BIT4
 127 #define   EFI_AHCI_PORT_CMD_CCS_MASK           (BIT8 | BIT9 | BIT10 | BIT11 | BIT12)
 128 #define   EFI_AHCI_PORT_CMD_CCS_SHIFT          8
 129 #define   EFI_AHCI_PORT_CMD_FR                 BIT14
 130 #define   EFI_AHCI_PORT_CMD_CR                 BIT15
 131 #define   EFI_AHCI_PORT_CMD_MASK               ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)
 132 #define   EFI_AHCI_PORT_CMD_PMA                BIT17
 133 #define   EFI_AHCI_PORT_CMD_HPCP               BIT18
 134 #define   EFI_AHCI_PORT_CMD_MPSP               BIT19
 135 #define   EFI_AHCI_PORT_CMD_CPD                BIT20
 136 #define   EFI_AHCI_PORT_CMD_ESP                BIT21
 137 #define   EFI_AHCI_PORT_CMD_ATAPI              BIT24
 138 #define   EFI_AHCI_PORT_CMD_DLAE               BIT25
 139 #define   EFI_AHCI_PORT_CMD_ALPE               BIT26
 140 #define   EFI_AHCI_PORT_CMD_ASP                BIT27
 141 #define   EFI_AHCI_PORT_CMD_ICC_MASK           (BIT28 | BIT29 | BIT30 | BIT31)
 142 #define   EFI_AHCI_PORT_CMD_ACTIVE             (1 << 28 )
 143 #define EFI_AHCI_PORT_TFD                      0x0020
 144 #define   EFI_AHCI_PORT_TFD_MASK               (BIT7 | BIT3 | BIT0)
 145 #define   EFI_AHCI_PORT_TFD_BSY                BIT7
 146 #define   EFI_AHCI_PORT_TFD_DRQ                BIT3
 147 #define   EFI_AHCI_PORT_TFD_ERR                BIT0
 148 #define   EFI_AHCI_PORT_TFD_ERR_MASK           0x00FF00
 149 #define EFI_AHCI_PORT_SIG                      0x0024
 150 #define EFI_AHCI_PORT_SSTS                     0x0028
 151 #define   EFI_AHCI_PORT_SSTS_DET_MASK          0x000F
 152 #define   EFI_AHCI_PORT_SSTS_DET               0x0001
 153 #define   EFI_AHCI_PORT_SSTS_DET_PCE           0x0003
 154 #define   EFI_AHCI_PORT_SSTS_SPD_MASK          0x00F0
 155 #define EFI_AHCI_PORT_SCTL                     0x002C
 156 #define   EFI_AHCI_PORT_SCTL_DET_MASK          0x000F
 157 #define   EFI_AHCI_PORT_SCTL_MASK              (~EFI_AHCI_PORT_SCTL_DET_MASK)
 158 #define   EFI_AHCI_PORT_SCTL_DET_INIT          0x0001
 159 #define   EFI_AHCI_PORT_SCTL_DET_PHYCOMM       0x0003
 160 #define   EFI_AHCI_PORT_SCTL_SPD_MASK          0x00F0
 161 #define   EFI_AHCI_PORT_SCTL_IPM_MASK          0x0F00
 162 #define   EFI_AHCI_PORT_SCTL_IPM_INIT          0x0300
 163 #define   EFI_AHCI_PORT_SCTL_IPM_PSD           0x0100
 164 #define   EFI_AHCI_PORT_SCTL_IPM_SSD           0x0200
 165 #define EFI_AHCI_PORT_SERR                     0x0030
 166 #define   EFI_AHCI_PORT_SERR_RDIE              BIT0
 167 #define   EFI_AHCI_PORT_SERR_RCE               BIT1
 168 #define   EFI_AHCI_PORT_SERR_TDIE              BIT8
 169 #define   EFI_AHCI_PORT_SERR_PCDIE             BIT9
 170 #define   EFI_AHCI_PORT_SERR_PE                BIT10
 171 #define   EFI_AHCI_PORT_SERR_IE                BIT11
 172 #define   EFI_AHCI_PORT_SERR_PRC               BIT16
 173 #define   EFI_AHCI_PORT_SERR_PIE               BIT17
 174 #define   EFI_AHCI_PORT_SERR_CW                BIT18
 175 #define   EFI_AHCI_PORT_SERR_BDE               BIT19
 176 #define   EFI_AHCI_PORT_SERR_DE                BIT20
 177 #define   EFI_AHCI_PORT_SERR_CRCE              BIT21
 178 #define   EFI_AHCI_PORT_SERR_HE                BIT22
 179 #define   EFI_AHCI_PORT_SERR_LSE               BIT23
 180 #define   EFI_AHCI_PORT_SERR_TSTE              BIT24
 181 #define   EFI_AHCI_PORT_SERR_UFT               BIT25
 182 #define   EFI_AHCI_PORT_SERR_EX                BIT26
 183 #define   EFI_AHCI_PORT_ERR_CLEAR              0xFFFFFFFF
 184 #define EFI_AHCI_PORT_SACT                     0x0034
 185 #define EFI_AHCI_PORT_CI                       0x0038
 186 #define EFI_AHCI_PORT_SNTF                     0x003C
 187 #define AHCI_PORT_DEVSLP                       0x0044
 188 #define   AHCI_PORT_DEVSLP_ADSE                BIT0
 189 #define   AHCI_PORT_DEVSLP_DSP                 BIT1
 190 #define   AHCI_PORT_DEVSLP_DETO_MASK           0x000003FC
 191 #define   AHCI_PORT_DEVSLP_MDAT_MASK           0x00007C00
 192 #define   AHCI_PORT_DEVSLP_DITO_MASK           0x01FF8000
 193 #define   AHCI_PORT_DEVSLP_DM_MASK             0x1E000000
 194
 195 #define AHCI_COMMAND_RETRIES  5
 196
 197 #pragma pack(1)
 198 //
 199 // Command List structure includes total 32 entries.
 200 // The entry data structure is listed at the following.
 201 //
 202 typedef struct {
 203   UINT32   AhciCmdCfl:5;      //Command FIS Length
 204   UINT32   AhciCmdA:1;        //ATAPI
 205   UINT32   AhciCmdW:1;        //Write
 206   UINT32   AhciCmdP:1;        //Prefetchable
 207   UINT32   AhciCmdR:1;        //Reset
 208   UINT32   AhciCmdB:1;        //BIST
 209   UINT32   AhciCmdC:1;        //Clear Busy upon R_OK
 210   UINT32   AhciCmdRsvd:1;
 211   UINT32   AhciCmdPmp:4;      //Port Multiplier Port
 212   UINT32   AhciCmdPrdtl:16;   //Physical Region Descriptor Table Length
 213   UINT32   AhciCmdPrdbc;      //Physical Region Descriptor Byte Count
 214   UINT32   AhciCmdCtba;       //Command Table Descriptor Base Address
 215   UINT32   AhciCmdCtbau;      //Command Table Descriptor Base Address Upper 32-BITs
 216   UINT32   AhciCmdRsvd1[4];
 217 } EFI_AHCI_COMMAND_LIST;
 218
 219 //
 220 // This is a software constructed FIS.
 221 // For data transfer operations, this is the H2D Register FIS format as
 222 // specified in the Serial ATA Revision 2.6 specification.
 223 //
 224 typedef struct {
 225   UINT8    AhciCFisType;
 226   UINT8    AhciCFisPmNum:4;
 227   UINT8    AhciCFisRsvd:1;
 228   UINT8    AhciCFisRsvd1:1;
 229   UINT8    AhciCFisRsvd2:1;
 230   UINT8    AhciCFisCmdInd:1;
 231   UINT8    AhciCFisCmd;
 232   UINT8    AhciCFisFeature;
 233   UINT8    AhciCFisSecNum;
 234   UINT8    AhciCFisClyLow;
 235   UINT8    AhciCFisClyHigh;
 236   UINT8    AhciCFisDevHead;
 237   UINT8    AhciCFisSecNumExp;
 238   UINT8    AhciCFisClyLowExp;
 239   UINT8    AhciCFisClyHighExp;
 240   UINT8    AhciCFisFeatureExp;
 241   UINT8    AhciCFisSecCount;
 242   UINT8    AhciCFisSecCountExp;
 243   UINT8    AhciCFisRsvd3;
 244   UINT8    AhciCFisControl;
 245   UINT8    AhciCFisRsvd4[4];
 246   UINT8    AhciCFisRsvd5[44];
 247 } EFI_AHCI_COMMAND_FIS;
 248
 249 typedef enum {
 250   SataFisD2H = 0,
 251   SataFisPioSetup,
 252   SataFisDmaSetup
 253 } SATA_FIS_TYPE;
 254
 255 //
 256 // ACMD: ATAPI command (12 or 16 bytes)
 257 //
 258 typedef struct {
 259   UINT8    AtapiCmd[0x10];
 260 } EFI_AHCI_ATAPI_COMMAND;
 261
 262 //
 263 // Physical Region Descriptor Table includes up to 65535 entries
 264 // The entry data structure is listed at the following.
 265 // the actual entry number comes from the PRDTL field in the command
 266 // list entry for this command slot.
 267 //
 268 typedef struct {
 269   UINT32   AhciPrdtDba;       //Data Base Address
 270   UINT32   AhciPrdtDbau;      //Data Base Address Upper 32-BITs
 271   UINT32   AhciPrdtRsvd;
 272   UINT32   AhciPrdtDbc:22;    //Data Byte Count
 273   UINT32   AhciPrdtRsvd1:9;
 274   UINT32   AhciPrdtIoc:1;     //Interrupt on Completion
 275 } EFI_AHCI_COMMAND_PRDT;
 276
 277 //
 278 // Command table data structure which is pointed to by the entry in the command list
 279 //
 280 typedef struct {
 281   EFI_AHCI_COMMAND_FIS      CommandFis;       // A software constructed FIS.
 282   EFI_AHCI_ATAPI_COMMAND    AtapiCmd;         // 12 or 16 bytes ATAPI cmd.
 283   UINT8                     Reserved[0x30];
 284   EFI_AHCI_COMMAND_PRDT     PrdtTable[65535];     // The scatter/gather list for data transfer
 285 } EFI_AHCI_COMMAND_TABLE;
 286
 287 //
 288 // Received FIS structure
 289 //
 290 typedef struct {
 291   UINT8    AhciDmaSetupFis[0x1C];         // Dma Setup Fis: offset 0x00
 292   UINT8    AhciDmaSetupFisRsvd[0x04];
 293   UINT8    AhciPioSetupFis[0x14];         // Pio Setup Fis: offset 0x20
 294   UINT8    AhciPioSetupFisRsvd[0x0C];
 295   UINT8    AhciD2HRegisterFis[0x14];      // D2H Register Fis: offset 0x40
 296   UINT8    AhciD2HRegisterFisRsvd[0x04];
 297   UINT64   AhciSetDeviceBitsFis;          // Set Device Bits Fix: offset 0x58
 298   UINT8    AhciUnknownFis[0x40];          // Unknown Fis: offset 0x60
 299   UINT8    AhciUnknownFisRsvd[0x60];
 300 } EFI_AHCI_RECEIVED_FIS;
 301
 302 typedef struct {
 303   UINT8  Madt : 5;
 304   UINT8  Reserved_5 : 3;
 305   UINT8  Deto;
 306   UINT16 Reserved_16;
 307   UINT32 Reserved_32 : 31;
 308   UINT32 Supported : 1;
 309 } DEVSLP_TIMING_VARIABLES;
 310
 311 #pragma pack()
 312
 313 typedef struct {
 314   EFI_AHCI_RECEIVED_FIS     *AhciRFis;
 315   EFI_AHCI_COMMAND_LIST     *AhciCmdList;
 316   EFI_AHCI_COMMAND_TABLE    *AhciCommandTable;
 317   EFI_AHCI_RECEIVED_FIS     *AhciRFisPciAddr;
 318   EFI_AHCI_COMMAND_LIST     *AhciCmdListPciAddr;
 319   EFI_AHCI_COMMAND_TABLE    *AhciCommandTablePciAddr;
 320   UINT64                    MaxCommandListSize;
 321   UINT64                    MaxCommandTableSize;
 322   UINT64                    MaxReceiveFisSize;
 323   VOID                      *MapRFis;
 324   VOID                      *MapCmdList;
 325   VOID                      *MapCommandTable;
 326 } EFI_AHCI_REGISTERS;
 327
 328 /**
 329   This function is used to send out ATAPI commands conforms to the Packet Command
 330   with PIO Protocol.
 331
 332   @param PciIo              The PCI IO protocol instance.
 333   @param AhciRegisters      The pointer to the EFI_AHCI_REGISTERS.
 334   @param Port               The number of port.
 335   @param PortMultiplier     The number of port multiplier.
 336   @param Packet             A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
 337
 338   @retval EFI_SUCCESS       send out the ATAPI packet command successfully
 339                             and device sends data successfully.
 340   @retval EFI_DEVICE_ERROR  the device failed to send data.
 341
 342 **/
 343 EFI_STATUS
 344 EFIAPI
 345 AhciPacketCommandExecute (
 346   IN  EFI_PCI_IO_PROTOCOL                           *PciIo,
 347   IN  EFI_AHCI_REGISTERS                            *AhciRegisters,
 348   IN  UINT8                                         Port,
 349   IN  UINT8                                         PortMultiplier,
 350   IN  EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET    *Packet
 351   );
 352
 353 /**
 354   Start command for give slot on specific port.
 355
 356   @param  PciIo              The PCI IO protocol instance.
 357   @param  Port               The number of port.
 358   @param  CommandSlot        The number of CommandSlot.
 359   @param  Timeout            The timeout value of start, uses 100ns as a unit.
 360
 361   @retval EFI_DEVICE_ERROR   The command start unsuccessfully.
 362   @retval EFI_TIMEOUT        The operation is time out.
 363   @retval EFI_SUCCESS        The command start successfully.
 364
 365 **/
 366 EFI_STATUS
 367 EFIAPI
 368 AhciStartCommand (
 369   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 370   IN  UINT8                     Port,
 371   IN  UINT8                     CommandSlot,
 372   IN  UINT64                    Timeout
 373   );
 374
 375 /**
 376   Stop command running for giving port
 377
 378   @param  PciIo              The PCI IO protocol instance.
 379   @param  Port               The number of port.
 380   @param  Timeout            The timeout value of stop, uses 100ns as a unit.
 381
 382   @retval EFI_DEVICE_ERROR   The command stop unsuccessfully.
 383   @retval EFI_TIMEOUT        The operation is time out.
 384   @retval EFI_SUCCESS        The command stop successfully.
 385
 386 **/
 387 EFI_STATUS
 388 EFIAPI
 389 AhciStopCommand (
 390   IN  EFI_PCI_IO_PROTOCOL       *PciIo,
 391   IN  UINT8                     Port,
 392   IN  UINT64                    Timeout
 393   );
 394
 395 #endif
 396