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1 /** @file
2 Header file for AHCI mode of ATA host controller.
3
4 Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13 **/
14 #ifndef __ATA_HC_AHCI_MODE_H__
15 #define __ATA_HC_AHCI_MODE_H__
16
17 #define EFI_AHCI_BAR_INDEX 0x05
18
19 #define EFI_AHCI_CAPABILITY_OFFSET 0x0000
20 #define EFI_AHCI_CAP_SSS BIT27
21 #define EFI_AHCI_CAP_S64A BIT31
22 #define EFI_AHCI_GHC_OFFSET 0x0004
23 #define EFI_AHCI_GHC_RESET BIT0
24 #define EFI_AHCI_GHC_IE BIT1
25 #define EFI_AHCI_GHC_ENABLE BIT31
26 #define EFI_AHCI_IS_OFFSET 0x0008
27 #define EFI_AHCI_PI_OFFSET 0x000C
28
29 #define EFI_AHCI_MAX_PORTS 32
30
31 typedef struct {
32 UINT32 Lower32;
33 UINT32 Upper32;
34 } DATA_32;
35
36 typedef union {
37 DATA_32 Uint32;
38 UINT64 Uint64;
39 } DATA_64;
40
41 //
42 // Refer SATA1.0a spec section 5.2, the Phy detection time should be less than 10ms.
43 //
44 #define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 10
45 //
46 // Refer SATA1.0a spec, the FIS enable time should be less than 500ms.
47 //
48 #define EFI_AHCI_PORT_CMD_FR_CLEAR_TIMEOUT EFI_TIMER_PERIOD_MILLISECONDS(500)
49 //
50 // Refer SATA1.0a spec, the bus reset time should be less than 1s.
51 //
52 #define EFI_AHCI_BUS_RESET_TIMEOUT EFI_TIMER_PERIOD_SECONDS(1)
53
54 #define EFI_AHCI_ATAPI_DEVICE_SIG 0xEB140000
55 #define EFI_AHCI_ATA_DEVICE_SIG 0x00000000
56 #define EFI_AHCI_PORT_MULTIPLIER_SIG 0x96690000
57 #define EFI_AHCI_ATAPI_SIG_MASK 0xFFFF0000
58
59 //
60 // Each PRDT entry can point to a memory block up to 4M byte
61 //
62 #define EFI_AHCI_MAX_DATA_PER_PRDT 0x400000
63
64 #define EFI_AHCI_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device
65 #define EFI_AHCI_FIS_REGISTER_H2D_LENGTH 20
66 #define EFI_AHCI_FIS_REGISTER_D2H 0x34 //Register FIS - Device to Host
67 #define EFI_AHCI_FIS_REGISTER_D2H_LENGTH 20
68 #define EFI_AHCI_FIS_DMA_ACTIVATE 0x39 //DMA Activate FIS - Device to Host
69 #define EFI_AHCI_FIS_DMA_ACTIVATE_LENGTH 4
70 #define EFI_AHCI_FIS_DMA_SETUP 0x41 //DMA Setup FIS - Bi-directional
71 #define EFI_AHCI_FIS_DMA_SETUP_LENGTH 28
72 #define EFI_AHCI_FIS_DATA 0x46 //Data FIS - Bi-directional
73 #define EFI_AHCI_FIS_BIST 0x58 //BIST Activate FIS - Bi-directional
74 #define EFI_AHCI_FIS_BIST_LENGTH 12
75 #define EFI_AHCI_FIS_PIO_SETUP 0x5F //PIO Setup FIS - Device to Host
76 #define EFI_AHCI_FIS_PIO_SETUP_LENGTH 20
77 #define EFI_AHCI_FIS_SET_DEVICE 0xA1 //Set Device Bits FIS - Device to Host
78 #define EFI_AHCI_FIS_SET_DEVICE_LENGTH 8
79
80 #define EFI_AHCI_D2H_FIS_OFFSET 0x40
81 #define EFI_AHCI_DMA_FIS_OFFSET 0x00
82 #define EFI_AHCI_PIO_FIS_OFFSET 0x20
83 #define EFI_AHCI_SDB_FIS_OFFSET 0x58
84 #define EFI_AHCI_FIS_TYPE_MASK 0xFF
85 #define EFI_AHCI_U_FIS_OFFSET 0x60
86
87 //
88 // Port register
89 //
90 #define EFI_AHCI_PORT_START 0x0100
91 #define EFI_AHCI_PORT_REG_WIDTH 0x0080
92 #define EFI_AHCI_PORT_CLB 0x0000
93 #define EFI_AHCI_PORT_CLBU 0x0004
94 #define EFI_AHCI_PORT_FB 0x0008
95 #define EFI_AHCI_PORT_FBU 0x000C
96 #define EFI_AHCI_PORT_IS 0x0010
97 #define EFI_AHCI_PORT_IS_DHRS BIT0
98 #define EFI_AHCI_PORT_IS_PSS BIT1
99 #define EFI_AHCI_PORT_IS_SSS BIT2
100 #define EFI_AHCI_PORT_IS_SDBS BIT3
101 #define EFI_AHCI_PORT_IS_UFS BIT4
102 #define EFI_AHCI_PORT_IS_DPS BIT5
103 #define EFI_AHCI_PORT_IS_PCS BIT6
104 #define EFI_AHCI_PORT_IS_DIS BIT7
105 #define EFI_AHCI_PORT_IS_PRCS BIT22
106 #define EFI_AHCI_PORT_IS_IPMS BIT23
107 #define EFI_AHCI_PORT_IS_OFS BIT24
108 #define EFI_AHCI_PORT_IS_INFS BIT26
109 #define EFI_AHCI_PORT_IS_IFS BIT27
110 #define EFI_AHCI_PORT_IS_HBDS BIT28
111 #define EFI_AHCI_PORT_IS_HBFS BIT29
112 #define EFI_AHCI_PORT_IS_TFES BIT30
113 #define EFI_AHCI_PORT_IS_CPDS BIT31
114 #define EFI_AHCI_PORT_IS_CLEAR 0xFFFFFFFF
115 #define EFI_AHCI_PORT_IS_FIS_CLEAR 0x0000000F
116
117 #define EFI_AHCI_PORT_IE 0x0014
118 #define EFI_AHCI_PORT_CMD 0x0018
119 #define EFI_AHCI_PORT_CMD_ST_MASK 0xFFFFFFFE
120 #define EFI_AHCI_PORT_CMD_ST BIT0
121 #define EFI_AHCI_PORT_CMD_SUD BIT1
122 #define EFI_AHCI_PORT_CMD_POD BIT2
123 #define EFI_AHCI_PORT_CMD_CLO BIT3
124 #define EFI_AHCI_PORT_CMD_CR BIT15
125 #define EFI_AHCI_PORT_CMD_FRE BIT4
126 #define EFI_AHCI_PORT_CMD_FR BIT14
127 #define EFI_AHCI_PORT_CMD_MASK ~(EFI_AHCI_PORT_CMD_ST | EFI_AHCI_PORT_CMD_FRE | EFI_AHCI_PORT_CMD_COL)
128 #define EFI_AHCI_PORT_CMD_PMA BIT17
129 #define EFI_AHCI_PORT_CMD_HPCP BIT18
130 #define EFI_AHCI_PORT_CMD_MPSP BIT19
131 #define EFI_AHCI_PORT_CMD_CPD BIT20
132 #define EFI_AHCI_PORT_CMD_ESP BIT21
133 #define EFI_AHCI_PORT_CMD_ATAPI BIT24
134 #define EFI_AHCI_PORT_CMD_DLAE BIT25
135 #define EFI_AHCI_PORT_CMD_ALPE BIT26
136 #define EFI_AHCI_PORT_CMD_ASP BIT27
137 #define EFI_AHCI_PORT_CMD_ICC_MASK (BIT28 | BIT29 | BIT30 | BIT31)
138 #define EFI_AHCI_PORT_CMD_ACTIVE (1 << 28 )
139 #define EFI_AHCI_PORT_TFD 0x0020
140 #define EFI_AHCI_PORT_TFD_MASK (BIT7 | BIT3 | BIT0)
141 #define EFI_AHCI_PORT_TFD_BSY BIT7
142 #define EFI_AHCI_PORT_TFD_DRQ BIT3
143 #define EFI_AHCI_PORT_TFD_ERR BIT0
144 #define EFI_AHCI_PORT_TFD_ERR_MASK 0x00FF00
145 #define EFI_AHCI_PORT_SIG 0x0024
146 #define EFI_AHCI_PORT_SSTS 0x0028
147 #define EFI_AHCI_PORT_SSTS_DET_MASK 0x000F
148 #define EFI_AHCI_PORT_SSTS_DET 0x0001
149 #define EFI_AHCI_PORT_SSTS_DET_PCE 0x0003
150 #define EFI_AHCI_PORT_SSTS_SPD_MASK 0x00F0
151 #define EFI_AHCI_PORT_SCTL 0x002C
152 #define EFI_AHCI_PORT_SCTL_DET_MASK 0x000F
153 #define EFI_AHCI_PORT_SCTL_MASK (~EFI_AHCI_PORT_SCTL_DET_MASK)
154 #define EFI_AHCI_PORT_SCTL_DET_INIT 0x0001
155 #define EFI_AHCI_PORT_SCTL_DET_PHYCOMM 0x0003
156 #define EFI_AHCI_PORT_SCTL_SPD_MASK 0x00F0
157 #define EFI_AHCI_PORT_SCTL_IPM_MASK 0x0F00
158 #define EFI_AHCI_PORT_SCTL_IPM_INIT 0x0300
159 #define EFI_AHCI_PORT_SCTL_IPM_PSD 0x0100
160 #define EFI_AHCI_PORT_SCTL_IPM_SSD 0x0200
161 #define EFI_AHCI_PORT_SERR 0x0030
162 #define EFI_AHCI_PORT_SERR_RDIE BIT0
163 #define EFI_AHCI_PORT_SERR_RCE BIT1
164 #define EFI_AHCI_PORT_SERR_TDIE BIT8
165 #define EFI_AHCI_PORT_SERR_PCDIE BIT9
166 #define EFI_AHCI_PORT_SERR_PE BIT10
167 #define EFI_AHCI_PORT_SERR_IE BIT11
168 #define EFI_AHCI_PORT_SERR_PRC BIT16
169 #define EFI_AHCI_PORT_SERR_PIE BIT17
170 #define EFI_AHCI_PORT_SERR_CW BIT18
171 #define EFI_AHCI_PORT_SERR_BDE BIT19
172 #define EFI_AHCI_PORT_SERR_DE BIT20
173 #define EFI_AHCI_PORT_SERR_CRCE BIT21
174 #define EFI_AHCI_PORT_SERR_HE BIT22
175 #define EFI_AHCI_PORT_SERR_LSE BIT23
176 #define EFI_AHCI_PORT_SERR_TSTE BIT24
177 #define EFI_AHCI_PORT_SERR_UFT BIT25
178 #define EFI_AHCI_PORT_SERR_EX BIT26
179 #define EFI_AHCI_PORT_ERR_CLEAR 0xFFFFFFFF
180 #define EFI_AHCI_PORT_SACT 0x0034
181 #define EFI_AHCI_PORT_CI 0x0038
182 #define EFI_AHCI_PORT_SNTF 0x003C
183
184
185 #pragma pack(1)
186 //
187 // Command List structure includes total 32 entries.
188 // The entry data structure is listed at the following.
189 //
190 typedef struct {
191 UINT32 AhciCmdCfl:5; //Command FIS Length
192 UINT32 AhciCmdA:1; //ATAPI
193 UINT32 AhciCmdW:1; //Write
194 UINT32 AhciCmdP:1; //Prefetchable
195 UINT32 AhciCmdR:1; //Reset
196 UINT32 AhciCmdB:1; //BIST
197 UINT32 AhciCmdC:1; //Clear Busy upon R_OK
198 UINT32 AhciCmdRsvd:1;
199 UINT32 AhciCmdPmp:4; //Port Multiplier Port
200 UINT32 AhciCmdPrdtl:16; //Physical Region Descriptor Table Length
201 UINT32 AhciCmdPrdbc; //Physical Region Descriptor Byte Count
202 UINT32 AhciCmdCtba; //Command Table Descriptor Base Address
203 UINT32 AhciCmdCtbau; //Command Table Descriptor Base Address Upper 32-BITs
204 UINT32 AhciCmdRsvd1[4];
205 } EFI_AHCI_COMMAND_LIST;
206
207 //
208 // This is a software constructed FIS.
209 // For data transfer operations, this is the H2D Register FIS format as
210 // specified in the Serial ATA Revision 2.6 specification.
211 //
212 typedef struct {
213 UINT8 AhciCFisType;
214 UINT8 AhciCFisPmNum:4;
215 UINT8 AhciCFisRsvd:1;
216 UINT8 AhciCFisRsvd1:1;
217 UINT8 AhciCFisRsvd2:1;
218 UINT8 AhciCFisCmdInd:1;
219 UINT8 AhciCFisCmd;
220 UINT8 AhciCFisFeature;
221 UINT8 AhciCFisSecNum;
222 UINT8 AhciCFisClyLow;
223 UINT8 AhciCFisClyHigh;
224 UINT8 AhciCFisDevHead;
225 UINT8 AhciCFisSecNumExp;
226 UINT8 AhciCFisClyLowExp;
227 UINT8 AhciCFisClyHighExp;
228 UINT8 AhciCFisFeatureExp;
229 UINT8 AhciCFisSecCount;
230 UINT8 AhciCFisSecCountExp;
231 UINT8 AhciCFisRsvd3;
232 UINT8 AhciCFisControl;
233 UINT8 AhciCFisRsvd4[4];
234 UINT8 AhciCFisRsvd5[44];
235 } EFI_AHCI_COMMAND_FIS;
236
237 //
238 // ACMD: ATAPI command (12 or 16 bytes)
239 //
240 typedef struct {
241 UINT8 AtapiCmd[0x10];
242 } EFI_AHCI_ATAPI_COMMAND;
243
244 //
245 // Physical Region Descriptor Table includes up to 65535 entries
246 // The entry data structure is listed at the following.
247 // the actual entry number comes from the PRDTL field in the command
248 // list entry for this command slot.
249 //
250 typedef struct {
251 UINT32 AhciPrdtDba; //Data Base Address
252 UINT32 AhciPrdtDbau; //Data Base Address Upper 32-BITs
253 UINT32 AhciPrdtRsvd;
254 UINT32 AhciPrdtDbc:22; //Data Byte Count
255 UINT32 AhciPrdtRsvd1:9;
256 UINT32 AhciPrdtIoc:1; //Interrupt on Completion
257 } EFI_AHCI_COMMAND_PRDT;
258
259 //
260 // Command table data strucute which is pointed to by the entry in the command list
261 //
262 typedef struct {
263 EFI_AHCI_COMMAND_FIS CommandFis; // A software constructed FIS.
264 EFI_AHCI_ATAPI_COMMAND AtapiCmd; // 12 or 16 bytes ATAPI cmd.
265 UINT8 Reserved[0x30];
266 EFI_AHCI_COMMAND_PRDT PrdtTable[65535]; // The scatter/gather list for data transfer
267 } EFI_AHCI_COMMAND_TABLE;
268
269 //
270 // Received FIS structure
271 //
272 typedef struct {
273 UINT8 AhciDmaSetupFis[0x1C]; // Dma Setup Fis: offset 0x00
274 UINT8 AhciDmaSetupFisRsvd[0x04];
275 UINT8 AhciPioSetupFis[0x14]; // Pio Setup Fis: offset 0x20
276 UINT8 AhciPioSetupFisRsvd[0x0C];
277 UINT8 AhciD2HRegisterFis[0x14]; // D2H Register Fis: offset 0x40
278 UINT8 AhciD2HRegisterFisRsvd[0x04];
279 UINT64 AhciSetDeviceBitsFis; // Set Device Bits Fix: offset 0x58
280 UINT8 AhciUnknownFis[0x40]; // Unkonwn Fis: offset 0x60
281 UINT8 AhciUnknownFisRsvd[0x60];
282 } EFI_AHCI_RECEIVED_FIS;
283
284 #pragma pack()
285
286 typedef struct {
287 EFI_AHCI_RECEIVED_FIS *AhciRFis;
288 EFI_AHCI_COMMAND_LIST *AhciCmdList;
289 EFI_AHCI_COMMAND_TABLE *AhciCommandTable;
290 EFI_AHCI_RECEIVED_FIS *AhciRFisPciAddr;
291 EFI_AHCI_COMMAND_LIST *AhciCmdListPciAddr;
292 EFI_AHCI_COMMAND_TABLE *AhciCommandTablePciAddr;
293 UINT64 MaxCommandListSize;
294 UINT64 MaxCommandTableSize;
295 UINT64 MaxReceiveFisSize;
296 VOID *MapRFis;
297 VOID *MapCmdList;
298 VOID *MapCommandTable;
299 } EFI_AHCI_REGISTERS;
300
301 /**
302 This function is used to send out ATAPI commands conforms to the Packet Command
303 with PIO Protocol.
304
305 @param PciIo The PCI IO protocol instance.
306 @param AhciRegisters The pointer to the EFI_AHCI_REGISTERS.
307 @param Port The number of port.
308 @param PortMultiplier The number of port multiplier.
309 @param Packet A pointer to EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET structure.
310
311 @retval EFI_SUCCESS send out the ATAPI packet command successfully
312 and device sends data successfully.
313 @retval EFI_DEVICE_ERROR the device failed to send data.
314
315 **/
316 EFI_STATUS
317 EFIAPI
318 AhciPacketCommandExecute (
319 IN EFI_PCI_IO_PROTOCOL *PciIo,
320 IN EFI_AHCI_REGISTERS *AhciRegisters,
321 IN UINT8 Port,
322 IN UINT8 PortMultiplier,
323 IN EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet
324 );
325
326 /**
327 Start command for give slot on specific port.
328
329 @param PciIo The PCI IO protocol instance.
330 @param Port The number of port.
331 @param CommandSlot The number of CommandSlot.
332 @param Timeout The timeout value of start, uses 100ns as a unit.
333
334 @retval EFI_DEVICE_ERROR The command start unsuccessfully.
335 @retval EFI_TIMEOUT The operation is time out.
336 @retval EFI_SUCCESS The command start successfully.
337
338 **/
339 EFI_STATUS
340 EFIAPI
341 AhciStartCommand (
342 IN EFI_PCI_IO_PROTOCOL *PciIo,
343 IN UINT8 Port,
344 IN UINT8 CommandSlot,
345 IN UINT64 Timeout
346 );
347
348 /**
349 Stop command running for giving port
350
351 @param PciIo The PCI IO protocol instance.
352 @param Port The number of port.
353 @param Timeout The timeout value of stop, uses 100ns as a unit.
354
355 @retval EFI_DEVICE_ERROR The command stop unsuccessfully.
356 @retval EFI_TIMEOUT The operation is time out.
357 @retval EFI_SUCCESS The command stop successfully.
358
359 **/
360 EFI_STATUS
361 EFIAPI
362 AhciStopCommand (
363 IN EFI_PCI_IO_PROTOCOL *PciIo,
364 IN UINT8 Port,
365 IN UINT64 Timeout
366 );
367
368 #endif
369